arm: tegra: pm269: 12.75mhz emc rate
[linux-2.6.git] / arch / arm / mach-tegra / board-cardhu-memory.c
1 /*
2  * Copyright (C) 2011-2012 NVIDIA Corporation. All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program; if not, write to the Free Software
15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
16  * 02111-1307, USA
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21
22 #include <mach/hardware.h>
23
24 #include "board.h"
25 #include "board-cardhu.h"
26 #include "tegra3_emc.h"
27 #include "fuse.h"
28
29 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g[] = {
30         {
31                 0x30,           /* Rev 3.0 */
32                 27000,          /* SDRAM frquency */
33                 {
34                         0x00000001,   /* EMC_RC */
35                         0x00000004,   /* EMC_RFC */
36                         0x00000000,   /* EMC_RAS */
37                         0x00000000,   /* EMC_RP */
38                         0x00000002,   /* EMC_R2W */
39                         0x0000000a,   /* EMC_W2R */
40                         0x00000003,   /* EMC_R2P */
41                         0x0000000b,   /* EMC_W2P */
42                         0x00000000,   /* EMC_RD_RCD */
43                         0x00000000,   /* EMC_WR_RCD */
44                         0x00000003,   /* EMC_RRD */
45                         0x00000001,   /* EMC_REXT */
46                         0x00000000,   /* EMC_WEXT */
47                         0x00000005,   /* EMC_WDV */
48                         0x00000005,   /* EMC_QUSE */
49                         0x00000004,   /* EMC_QRST */
50                         0x00000007,   /* EMC_QSAFE */
51                         0x0000000d,   /* EMC_RDV */
52                         0x000000cb,   /* EMC_REFRESH */
53                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
54                         0x00000032,   /* EMC_PRE_REFRESH_REQ_CNT */
55                         0x00000002,   /* EMC_PDEX2WR */
56                         0x00000002,   /* EMC_PDEX2RD */
57                         0x00000001,   /* EMC_PCHG2PDEN */
58                         0x00000000,   /* EMC_ACT2PDEN */
59                         0x00000007,   /* EMC_AR2PDEN */
60                         0x0000000f,   /* EMC_RW2PDEN */
61                         0x00000005,   /* EMC_TXSR */
62                         0x00000005,   /* EMC_TXSRDLL */
63                         0x00000004,   /* EMC_TCKE */
64                         0x00000001,   /* EMC_TFAW */
65                         0x00000000,   /* EMC_TRPAB */
66                         0x00000004,   /* EMC_TCLKSTABLE */
67                         0x00000005,   /* EMC_TCLKSTOP */
68                         0x000000d3,   /* EMC_TREFBW */
69                         0x00000000,   /* EMC_QUSE_EXTRA */
70                         0x00000004,   /* EMC_FBIO_CFG6 */
71                         0x00000000,   /* EMC_ODT_WRITE */
72                         0x00000000,   /* EMC_ODT_READ */
73                         0x00006288,   /* EMC_FBIO_CFG5 */
74                         0xd0780421,   /* EMC_CFG_DIG_DLL */
75                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
76                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
77                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
78                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
79                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
80                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
81                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
82                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
83                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
84                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
85                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
86                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
87                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
88                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
89                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
90                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
91                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
92                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
93                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
94                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
95                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
96                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
97                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
98                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
99                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
100                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
101                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
102                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
103                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
104                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
105                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
106                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
107                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
108                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
109                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
110                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
111                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
112                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
113                         0x00000802,   /* EMC_CTT_TERM_CTRL */
114                         0x00000000,   /* EMC_ZCAL_INTERVAL */
115                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
116                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
117                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
118                         0x00000000,   /* EMC_CTT */
119                         0x00000000,   /* EMC_CTT_DURATION */
120                         0x8000029e,   /* EMC_DYN_SELF_REF_CONTROL */
121                         0x00000001,   /* MC_EMEM_ARB_CFG */
122                         0x8000000d,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
123                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
124                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
125                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
126                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
127                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
128                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
129                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
130                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
131                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
132                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
133                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
134                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
135                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
136                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
137                         0x78430306,   /* MC_EMEM_ARB_MISC0 */
138                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
139                 },
140                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
141                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
142                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
143                 0x00001221,     /* Mode Register 0 */
144                 0x00100003,     /* Mode Register 1 */
145                 0x00200008,     /* Mode Register 2 */
146         },
147         {
148                 0x30,           /* Rev 3.0 */
149                 54000,          /* SDRAM frquency */
150                 {
151                         0x00000002,   /* EMC_RC */
152                         0x00000008,   /* EMC_RFC */
153                         0x00000001,   /* EMC_RAS */
154                         0x00000000,   /* EMC_RP */
155                         0x00000002,   /* EMC_R2W */
156                         0x0000000a,   /* EMC_W2R */
157                         0x00000003,   /* EMC_R2P */
158                         0x0000000b,   /* EMC_W2P */
159                         0x00000000,   /* EMC_RD_RCD */
160                         0x00000000,   /* EMC_WR_RCD */
161                         0x00000003,   /* EMC_RRD */
162                         0x00000001,   /* EMC_REXT */
163                         0x00000000,   /* EMC_WEXT */
164                         0x00000005,   /* EMC_WDV */
165                         0x00000005,   /* EMC_QUSE */
166                         0x00000004,   /* EMC_QRST */
167                         0x00000007,   /* EMC_QSAFE */
168                         0x0000000d,   /* EMC_RDV */
169                         0x00000198,   /* EMC_REFRESH */
170                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
171                         0x00000066,   /* EMC_PRE_REFRESH_REQ_CNT */
172                         0x00000002,   /* EMC_PDEX2WR */
173                         0x00000002,   /* EMC_PDEX2RD */
174                         0x00000001,   /* EMC_PCHG2PDEN */
175                         0x00000000,   /* EMC_ACT2PDEN */
176                         0x00000007,   /* EMC_AR2PDEN */
177                         0x0000000f,   /* EMC_RW2PDEN */
178                         0x0000000a,   /* EMC_TXSR */
179                         0x0000000a,   /* EMC_TXSRDLL */
180                         0x00000004,   /* EMC_TCKE */
181                         0x00000002,   /* EMC_TFAW */
182                         0x00000000,   /* EMC_TRPAB */
183                         0x00000004,   /* EMC_TCLKSTABLE */
184                         0x00000005,   /* EMC_TCLKSTOP */
185                         0x000001a6,   /* EMC_TREFBW */
186                         0x00000000,   /* EMC_QUSE_EXTRA */
187                         0x00000004,   /* EMC_FBIO_CFG6 */
188                         0x00000000,   /* EMC_ODT_WRITE */
189                         0x00000000,   /* EMC_ODT_READ */
190                         0x00006288,   /* EMC_FBIO_CFG5 */
191                         0xd0780421,   /* EMC_CFG_DIG_DLL */
192                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
193                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
194                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
195                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
196                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
197                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
198                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
199                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
200                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
201                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
202                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
203                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
204                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
205                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
206                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
207                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
208                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
209                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
210                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
211                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
212                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
213                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
214                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
215                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
216                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
217                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
218                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
219                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
220                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
221                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
222                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
223                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
224                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
225                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
226                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
227                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
228                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
229                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
230                         0x00000802,   /* EMC_CTT_TERM_CTRL */
231                         0x00000000,   /* EMC_ZCAL_INTERVAL */
232                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
233                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
234                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
235                         0x00000000,   /* EMC_CTT */
236                         0x00000000,   /* EMC_CTT_DURATION */
237                         0x80000439,   /* EMC_DYN_SELF_REF_CONTROL */
238                         0x00000001,   /* MC_EMEM_ARB_CFG */
239                         0x80000014,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
240                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
241                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
242                         0x00000005,   /* MC_EMEM_ARB_TIMING_RC */
243                         0x00000001,   /* MC_EMEM_ARB_TIMING_RAS */
244                         0x00000001,   /* MC_EMEM_ARB_TIMING_FAW */
245                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
246                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
247                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
248                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
249                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
250                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
251                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
252                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
253                         0x00140905,   /* MC_EMEM_ARB_DA_COVERS */
254                         0x78430506,   /* MC_EMEM_ARB_MISC0 */
255                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
256                 },
257                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
258                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
259                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
260                 0x00001221,     /* Mode Register 0 */
261                 0x00100003,     /* Mode Register 1 */
262                 0x00200008,     /* Mode Register 2 */
263         },
264         {
265                 0x30,           /* Rev 3.0 */
266                 108000,         /* SDRAM frquency */
267                 {
268                         0x00000005,   /* EMC_RC */
269                         0x00000011,   /* EMC_RFC */
270                         0x00000003,   /* EMC_RAS */
271                         0x00000001,   /* EMC_RP */
272                         0x00000002,   /* EMC_R2W */
273                         0x0000000a,   /* EMC_W2R */
274                         0x00000003,   /* EMC_R2P */
275                         0x0000000b,   /* EMC_W2P */
276                         0x00000001,   /* EMC_RD_RCD */
277                         0x00000001,   /* EMC_WR_RCD */
278                         0x00000003,   /* EMC_RRD */
279                         0x00000001,   /* EMC_REXT */
280                         0x00000000,   /* EMC_WEXT */
281                         0x00000005,   /* EMC_WDV */
282                         0x00000005,   /* EMC_QUSE */
283                         0x00000004,   /* EMC_QRST */
284                         0x00000007,   /* EMC_QSAFE */
285                         0x0000000d,   /* EMC_RDV */
286                         0x00000330,   /* EMC_REFRESH */
287                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
288                         0x000000cc,   /* EMC_PRE_REFRESH_REQ_CNT */
289                         0x00000002,   /* EMC_PDEX2WR */
290                         0x00000002,   /* EMC_PDEX2RD */
291                         0x00000001,   /* EMC_PCHG2PDEN */
292                         0x00000000,   /* EMC_ACT2PDEN */
293                         0x00000007,   /* EMC_AR2PDEN */
294                         0x0000000f,   /* EMC_RW2PDEN */
295                         0x00000013,   /* EMC_TXSR */
296                         0x00000013,   /* EMC_TXSRDLL */
297                         0x00000004,   /* EMC_TCKE */
298                         0x00000004,   /* EMC_TFAW */
299                         0x00000000,   /* EMC_TRPAB */
300                         0x00000004,   /* EMC_TCLKSTABLE */
301                         0x00000005,   /* EMC_TCLKSTOP */
302                         0x0000034b,   /* EMC_TREFBW */
303                         0x00000000,   /* EMC_QUSE_EXTRA */
304                         0x00000004,   /* EMC_FBIO_CFG6 */
305                         0x00000000,   /* EMC_ODT_WRITE */
306                         0x00000000,   /* EMC_ODT_READ */
307                         0x00006288,   /* EMC_FBIO_CFG5 */
308                         0xd0780421,   /* EMC_CFG_DIG_DLL */
309                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
310                         0x00080000,   /* EMC_DLL_XFORM_DQS0 */
311                         0x00080000,   /* EMC_DLL_XFORM_DQS1 */
312                         0x00080000,   /* EMC_DLL_XFORM_DQS2 */
313                         0x00080000,   /* EMC_DLL_XFORM_DQS3 */
314                         0x00080000,   /* EMC_DLL_XFORM_DQS4 */
315                         0x00080000,   /* EMC_DLL_XFORM_DQS5 */
316                         0x00080000,   /* EMC_DLL_XFORM_DQS6 */
317                         0x00080000,   /* EMC_DLL_XFORM_DQS7 */
318                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
319                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
320                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
321                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
322                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
323                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
324                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
325                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
326                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
327                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
328                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
329                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
330                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
331                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
332                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
333                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
334                         0x00080000,   /* EMC_DLL_XFORM_DQ0 */
335                         0x00080000,   /* EMC_DLL_XFORM_DQ1 */
336                         0x00080000,   /* EMC_DLL_XFORM_DQ2 */
337                         0x00080000,   /* EMC_DLL_XFORM_DQ3 */
338                         0x000003e0,   /* EMC_XM2CMDPADCTRL */
339                         0x0800211d,   /* EMC_XM2DQSPADCTRL2 */
340                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
341                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
342                         0x01f1f108,   /* EMC_XM2COMPPADCTRL */
343                         0x07075504,   /* EMC_XM2VTTGENPADCTRL */
344                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
345                         0x0800012d,   /* EMC_XM2QUSEPADCTRL */
346                         0x08000000,   /* EMC_XM2DQSPADCTRL3 */
347                         0x00000802,   /* EMC_CTT_TERM_CTRL */
348                         0x00000000,   /* EMC_ZCAL_INTERVAL */
349                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
350                         0x000c000c,   /* EMC_MRS_WAIT_CNT */
351                         0xa0f10000,   /* EMC_AUTO_CAL_CONFIG */
352                         0x00000000,   /* EMC_CTT */
353                         0x00000000,   /* EMC_CTT_DURATION */
354                         0x8000076e,   /* EMC_DYN_SELF_REF_CONTROL */
355                         0x00000003,   /* MC_EMEM_ARB_CFG */
356                         0x80000027,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
357                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
358                         0x00000004,   /* MC_EMEM_ARB_TIMING_RP */
359                         0x00000006,   /* MC_EMEM_ARB_TIMING_RC */
360                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAS */
361                         0x00000003,   /* MC_EMEM_ARB_TIMING_FAW */
362                         0x00000003,   /* MC_EMEM_ARB_TIMING_RRD */
363                         0x00000004,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
364                         0x0000000f,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
365                         0x00000006,   /* MC_EMEM_ARB_TIMING_R2R */
366                         0x00000005,   /* MC_EMEM_ARB_TIMING_W2W */
367                         0x00000007,   /* MC_EMEM_ARB_TIMING_R2W */
368                         0x0000000f,   /* MC_EMEM_ARB_TIMING_W2R */
369                         0x0f070506,   /* MC_EMEM_ARB_DA_TURNS */
370                         0x00140906,   /* MC_EMEM_ARB_DA_COVERS */
371                         0x78440a07,   /* MC_EMEM_ARB_MISC0 */
372                         0x001f0001,   /* MC_EMEM_ARB_RING1_THROTTLE */
373                 },
374                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
375                 0x001fffff,     /* EMC_AUTO_CAL_INTERVAL */
376                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
377                 0x00001221,     /* Mode Register 0 */
378                 0x00100003,     /* Mode Register 1 */
379                 0x00200008,     /* Mode Register 2 */
380         },
381         {
382                 0x30,           /* Rev 3.0 */
383                 416000,         /* SDRAM frequency */
384                 {
385                         0x00000013,   /* EMC_RC */
386                         0x00000041,   /* EMC_RFC */
387                         0x0000000d,   /* EMC_RAS */
388                         0x00000004,   /* EMC_RP */
389                         0x00000002,   /* EMC_R2W */
390                         0x00000009,   /* EMC_W2R */
391                         0x00000002,   /* EMC_R2P */
392                         0x0000000c,   /* EMC_W2P */
393                         0x00000004,   /* EMC_RD_RCD */
394                         0x00000004,   /* EMC_WR_RCD */
395                         0x00000002,   /* EMC_RRD */
396                         0x00000001,   /* EMC_REXT */
397                         0x00000000,   /* EMC_WEXT */
398                         0x00000005,   /* EMC_WDV */
399                         0x00000008,   /* EMC_QUSE */
400                         0x00000006,   /* EMC_QRST */
401                         0x00000008,   /* EMC_QSAFE */
402                         0x00000010,   /* EMC_RDV */
403                         0x00000c6c,   /* EMC_REFRESH */
404                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
405                         0x0000031b,   /* EMC_PRE_REFRESH_REQ_CNT */
406                         0x00000001,   /* EMC_PDEX2WR */
407                         0x00000001,   /* EMC_PDEX2RD */
408                         0x00000001,   /* EMC_PCHG2PDEN */
409                         0x00000000,   /* EMC_ACT2PDEN */
410                         0x00000008,   /* EMC_AR2PDEN */
411                         0x00000011,   /* EMC_RW2PDEN */
412                         0x00000047,   /* EMC_TXSR */
413                         0x00000200,   /* EMC_TXSRDLL */
414                         0x00000004,   /* EMC_TCKE */
415                         0x0000000d,   /* EMC_TFAW */
416                         0x00000000,   /* EMC_TRPAB */
417                         0x00000004,   /* EMC_TCLKSTABLE */
418                         0x00000005,   /* EMC_TCLKSTOP */
419                         0x00000cad,   /* EMC_TREFBW */
420                         0x00000000,   /* EMC_QUSE_EXTRA */
421                         0x00000006,   /* EMC_FBIO_CFG6 */
422                         0x00000000,   /* EMC_ODT_WRITE */
423                         0x00000000,   /* EMC_ODT_READ */
424                         0x00007088,   /* EMC_FBIO_CFG5 */
425                         0xf0120441,   /* EMC_CFG_DIG_DLL */
426                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
427                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
428                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
429                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
430                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
431                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
432                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
433                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
434                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
435                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
436                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
437                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
438                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
439                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
440                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
441                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
442                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
443                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
444                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
445                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
446                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
447                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
448                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
449                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
450                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
451                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
452                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
453                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
454                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
455                         0x000006a0,   /* EMC_XM2CMDPADCTRL */
456                         0x0800013d,   /* EMC_XM2DQSPADCTRL2 */
457                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
458                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
459                         0x01f1f50f,   /* EMC_XM2COMPPADCTRL */
460                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
461                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
462                         0x0800011d,   /* EMC_XM2QUSEPADCTRL */
463                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
464                         0x00000802,   /* EMC_CTT_TERM_CTRL */
465                         0x00000000,   /* EMC_ZCAL_INTERVAL */
466                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
467                         0x01be000c,   /* EMC_MRS_WAIT_CNT */
468                         0xa0f10404,   /* EMC_AUTO_CAL_CONFIG */
469                         0x00000000,   /* EMC_CTT */
470                         0x00000000,   /* EMC_CTT_DURATION */
471                         0x000020ae,   /* EMC_DYN_SELF_REF_CONTROL */
472                         0x00000006,   /* MC_EMEM_ARB_CFG */
473                         0x8000004b,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
474                         0x00000001,   /* MC_EMEM_ARB_TIMING_RCD */
475                         0x00000002,   /* MC_EMEM_ARB_TIMING_RP */
476                         0x0000000a,   /* MC_EMEM_ARB_TIMING_RC */
477                         0x00000006,   /* MC_EMEM_ARB_TIMING_RAS */
478                         0x00000006,   /* MC_EMEM_ARB_TIMING_FAW */
479                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
480                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
481                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
482                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
483                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
484                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
485                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
486                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
487                         0x000e070a,   /* MC_EMEM_ARB_DA_COVERS */
488                         0x7027130b,   /* MC_EMEM_ARB_MISC0 */
489                         0x001f0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
490                 },
491                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
492                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
493                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
494                 0x00001941,     /* Mode Register 0 */
495                 0x00100002,     /* Mode Register 1 */
496                 0x00200008,     /* Mode Register 2 */
497         },
498         {
499                 0x30,           /* Rev 3.0 */
500                 533000,         /* SDRAM frquency */
501                 {
502                         0x00000018,   /* EMC_RC */
503                         0x00000054,   /* EMC_RFC */
504                         0x00000011,   /* EMC_RAS */
505                         0x00000006,   /* EMC_RP */
506                         0x00000003,   /* EMC_R2W */
507                         0x00000009,   /* EMC_W2R */
508                         0x00000002,   /* EMC_R2P */
509                         0x0000000d,   /* EMC_W2P */
510                         0x00000006,   /* EMC_RD_RCD */
511                         0x00000006,   /* EMC_WR_RCD */
512                         0x00000002,   /* EMC_RRD */
513                         0x00000001,   /* EMC_REXT */
514                         0x00000000,   /* EMC_WEXT */
515                         0x00000005,   /* EMC_WDV */
516                         0x00000008,   /* EMC_QUSE */
517                         0x00000006,   /* EMC_QRST */
518                         0x00000008,   /* EMC_QSAFE */
519                         0x00000010,   /* EMC_RDV */
520                         0x00000ffd,   /* EMC_REFRESH */
521                         0x00000000,   /* EMC_BURST_REFRESH_NUM */
522                         0x000003ff,   /* EMC_PRE_REFRESH_REQ_CNT */
523                         0x00000002,   /* EMC_PDEX2WR */
524                         0x00000002,   /* EMC_PDEX2RD */
525                         0x00000001,   /* EMC_PCHG2PDEN */
526                         0x00000000,   /* EMC_ACT2PDEN */
527                         0x0000000a,   /* EMC_AR2PDEN */
528                         0x00000012,   /* EMC_RW2PDEN */
529                         0x0000005b,   /* EMC_TXSR */
530                         0x00000200,   /* EMC_TXSRDLL */
531                         0x00000004,   /* EMC_TCKE */
532                         0x00000010,   /* EMC_TFAW */
533                         0x00000000,   /* EMC_TRPAB */
534                         0x00000005,   /* EMC_TCLKSTABLE */
535                         0x00000006,   /* EMC_TCLKSTOP */
536                         0x0000103e,   /* EMC_TREFBW */
537                         0x00000000,   /* EMC_QUSE_EXTRA */
538                         0x00000006,   /* EMC_FBIO_CFG6 */
539                         0x00000000,   /* EMC_ODT_WRITE */
540                         0x00000000,   /* EMC_ODT_READ */
541                         0x00007088,   /* EMC_FBIO_CFG5 */
542                         0xf0120441,   /* EMC_CFG_DIG_DLL */
543                         0x00008000,   /* EMC_CFG_DIG_DLL_PERIOD */
544                         0x00010000,   /* EMC_DLL_XFORM_DQS0 */
545                         0x00010000,   /* EMC_DLL_XFORM_DQS1 */
546                         0x00010000,   /* EMC_DLL_XFORM_DQS2 */
547                         0x00010000,   /* EMC_DLL_XFORM_DQS3 */
548                         0x00010000,   /* EMC_DLL_XFORM_DQS4 */
549                         0x00010000,   /* EMC_DLL_XFORM_DQS5 */
550                         0x00010000,   /* EMC_DLL_XFORM_DQS6 */
551                         0x00010000,   /* EMC_DLL_XFORM_DQS7 */
552                         0x00000000,   /* EMC_DLL_XFORM_QUSE0 */
553                         0x00000000,   /* EMC_DLL_XFORM_QUSE1 */
554                         0x00000000,   /* EMC_DLL_XFORM_QUSE2 */
555                         0x00000000,   /* EMC_DLL_XFORM_QUSE3 */
556                         0x00000000,   /* EMC_DLL_XFORM_QUSE4 */
557                         0x00000000,   /* EMC_DLL_XFORM_QUSE5 */
558                         0x00000000,   /* EMC_DLL_XFORM_QUSE6 */
559                         0x00000000,   /* EMC_DLL_XFORM_QUSE7 */
560                         0x00000000,   /* EMC_DLI_TRIM_TXDQS0 */
561                         0x00000000,   /* EMC_DLI_TRIM_TXDQS1 */
562                         0x00000000,   /* EMC_DLI_TRIM_TXDQS2 */
563                         0x00000000,   /* EMC_DLI_TRIM_TXDQS3 */
564                         0x00000000,   /* EMC_DLI_TRIM_TXDQS4 */
565                         0x00000000,   /* EMC_DLI_TRIM_TXDQS5 */
566                         0x00000000,   /* EMC_DLI_TRIM_TXDQS6 */
567                         0x00000000,   /* EMC_DLI_TRIM_TXDQS7 */
568                         0x00020000,   /* EMC_DLL_XFORM_DQ0 */
569                         0x00020000,   /* EMC_DLL_XFORM_DQ1 */
570                         0x00020000,   /* EMC_DLL_XFORM_DQ2 */
571                         0x00020000,   /* EMC_DLL_XFORM_DQ3 */
572                         0x000006a0,   /* EMC_XM2CMDPADCTRL */
573                         0x0800013d,   /* EMC_XM2DQSPADCTRL2 */
574                         0x00000000,   /* EMC_XM2DQPADCTRL2 */
575                         0x77ffc084,   /* EMC_XM2CLKPADCTRL */
576                         0x01f1f50f,   /* EMC_XM2COMPPADCTRL */
577                         0x07077404,   /* EMC_XM2VTTGENPADCTRL */
578                         0x00000007,   /* EMC_XM2VTTGENPADCTRL2 */
579                         0x0800011d,   /* EMC_XM2QUSEPADCTRL */
580                         0x08000021,   /* EMC_XM2DQSPADCTRL3 */
581                         0x00000802,   /* EMC_CTT_TERM_CTRL */
582                         0x00000000,   /* EMC_ZCAL_INTERVAL */
583                         0x00000040,   /* EMC_ZCAL_WAIT_CNT */
584                         0x01ab000c,   /* EMC_MRS_WAIT_CNT */
585                         0xa0f10404,   /* EMC_AUTO_CAL_CONFIG */
586                         0x00000000,   /* EMC_CTT */
587                         0x00000000,   /* EMC_CTT_DURATION */
588                         0x000020ae,   /* EMC_DYN_SELF_REF_CONTROL */
589                         0x00000008,   /* MC_EMEM_ARB_CFG */
590                         0x80000060,   /* MC_EMEM_ARB_OUTSTANDING_REQ */
591                         0x00000002,   /* MC_EMEM_ARB_TIMING_RCD */
592                         0x00000003,   /* MC_EMEM_ARB_TIMING_RP */
593                         0x0000000d,   /* MC_EMEM_ARB_TIMING_RC */
594                         0x00000008,   /* MC_EMEM_ARB_TIMING_RAS */
595                         0x00000007,   /* MC_EMEM_ARB_TIMING_FAW */
596                         0x00000001,   /* MC_EMEM_ARB_TIMING_RRD */
597                         0x00000002,   /* MC_EMEM_ARB_TIMING_RAP2PRE */
598                         0x00000009,   /* MC_EMEM_ARB_TIMING_WAP2PRE */
599                         0x00000002,   /* MC_EMEM_ARB_TIMING_R2R */
600                         0x00000002,   /* MC_EMEM_ARB_TIMING_W2W */
601                         0x00000003,   /* MC_EMEM_ARB_TIMING_R2W */
602                         0x00000006,   /* MC_EMEM_ARB_TIMING_W2R */
603                         0x06030202,   /* MC_EMEM_ARB_DA_TURNS */
604                         0x0010090d,   /* MC_EMEM_ARB_DA_COVERS */
605                         0x7028180e,   /* MC_EMEM_ARB_MISC0 */
606                         0x001f0000,   /* MC_EMEM_ARB_RING1_THROTTLE */
607                 },
608                 0x00000040,     /* EMC_ZCAL_WAIT_CNT after clock change */
609                 0x00000010,     /* EMC_AUTO_CAL_INTERVAL */
610                 0x00000000,     /* EMC_CFG.PERIODIC_QRST */
611                 0x00001941,     /* Mode Register 0 */
612                 0x00100002,     /* Mode Register 1 */
613                 0x00200008,     /* Mode Register 2 */
614         },
615 };
616
617 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = {
618         {
619                 0x32,       /* Rev 3.2 */
620                 25500,      /* SDRAM frequency */
621                 {
622                         0x00000001, /* EMC_RC */
623                         0x00000003, /* EMC_RFC */
624                         0x00000000, /* EMC_RAS */
625                         0x00000000, /* EMC_RP */
626                         0x00000002, /* EMC_R2W */
627                         0x0000000a, /* EMC_W2R */
628                         0x00000003, /* EMC_R2P */
629                         0x0000000b, /* EMC_W2P */
630                         0x00000000, /* EMC_RD_RCD */
631                         0x00000000, /* EMC_WR_RCD */
632                         0x00000003, /* EMC_RRD */
633                         0x00000001, /* EMC_REXT */
634                         0x00000000, /* EMC_WEXT */
635                         0x00000005, /* EMC_WDV */
636                         0x00000005, /* EMC_QUSE */
637                         0x00000004, /* EMC_QRST */
638                         0x00000007, /* EMC_QSAFE */
639                         0x0000000c, /* EMC_RDV */
640                         0x000000bd, /* EMC_REFRESH */
641                         0x00000000, /* EMC_BURST_REFRESH_NUM */
642                         0x0000002f, /* EMC_PRE_REFRESH_REQ_CNT */
643                         0x00000002, /* EMC_PDEX2WR */
644                         0x00000002, /* EMC_PDEX2RD */
645                         0x00000001, /* EMC_PCHG2PDEN */
646                         0x00000000, /* EMC_ACT2PDEN */
647                         0x00000007, /* EMC_AR2PDEN */
648                         0x0000000f, /* EMC_RW2PDEN */
649                         0x00000005, /* EMC_TXSR */
650                         0x00000005, /* EMC_TXSRDLL */
651                         0x00000004, /* EMC_TCKE */
652                         0x00000001, /* EMC_TFAW */
653                         0x00000000, /* EMC_TRPAB */
654                         0x00000004, /* EMC_TCLKSTABLE */
655                         0x00000005, /* EMC_TCLKSTOP */
656                         0x000000c3, /* EMC_TREFBW */
657                         0x00000000, /* EMC_QUSE_EXTRA */
658                         0x00000004, /* EMC_FBIO_CFG6 */
659                         0x00000000, /* EMC_ODT_WRITE */
660                         0x00000000, /* EMC_ODT_READ */
661                         0x00006288, /* EMC_FBIO_CFG5 */
662                         0x007800a4, /* EMC_CFG_DIG_DLL */
663                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
664                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
665                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
666                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
667                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
668                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
669                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
670                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
671                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
672                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
673                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
674                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
675                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
676                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
677                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
678                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
679                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
680                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
681                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
682                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
683                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
684                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
685                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
686                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
687                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
688                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
689                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
690                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
691                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
692                         0x000002a0, /* EMC_XM2CMDPADCTRL */
693                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
694                         0x00000000, /* EMC_XM2DQPADCTRL2 */
695                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
696                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
697                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
698                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
699                         0x08000168, /* EMC_XM2QUSEPADCTRL */
700                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
701                         0x00000802, /* EMC_CTT_TERM_CTRL */
702                         0x00000000, /* EMC_ZCAL_INTERVAL */
703                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
704                         0x000c000c, /* EMC_MRS_WAIT_CNT */
705                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
706                         0x00000000, /* EMC_CTT */
707                         0x00000000, /* EMC_CTT_DURATION */
708                         0x80000280, /* EMC_DYN_SELF_REF_CONTROL */
709                         0x00020001, /* MC_EMEM_ARB_CFG */
710                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
711                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
712                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
713                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
714                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
715                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
716                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
717                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
718                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
719                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
720                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
721                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
722                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
723                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
724                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
725                         0x74430303, /* MC_EMEM_ARB_MISC0 */
726                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
727                         0xd8000000, /* EMC_FBIO_SPARE */
728                         0xff00ff00, /* EMC_CFG_RSV */
729                 },
730                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
731                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
732                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
733                 0x80001221, /* Mode Register 0 */
734                 0x80100003, /* Mode Register 1 */
735                 0x80200008, /* Mode Register 2 */
736                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
737         },
738         {
739                 0x32,       /* Rev 3.2 */
740                 51000,      /* SDRAM frequency */
741                 {
742                         0x00000002, /* EMC_RC */
743                         0x00000008, /* EMC_RFC */
744                         0x00000001, /* EMC_RAS */
745                         0x00000000, /* EMC_RP */
746                         0x00000002, /* EMC_R2W */
747                         0x0000000a, /* EMC_W2R */
748                         0x00000003, /* EMC_R2P */
749                         0x0000000b, /* EMC_W2P */
750                         0x00000000, /* EMC_RD_RCD */
751                         0x00000000, /* EMC_WR_RCD */
752                         0x00000003, /* EMC_RRD */
753                         0x00000001, /* EMC_REXT */
754                         0x00000000, /* EMC_WEXT */
755                         0x00000005, /* EMC_WDV */
756                         0x00000005, /* EMC_QUSE */
757                         0x00000004, /* EMC_QRST */
758                         0x00000007, /* EMC_QSAFE */
759                         0x0000000c, /* EMC_RDV */
760                         0x00000181, /* EMC_REFRESH */
761                         0x00000000, /* EMC_BURST_REFRESH_NUM */
762                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
763                         0x00000002, /* EMC_PDEX2WR */
764                         0x00000002, /* EMC_PDEX2RD */
765                         0x00000001, /* EMC_PCHG2PDEN */
766                         0x00000000, /* EMC_ACT2PDEN */
767                         0x00000007, /* EMC_AR2PDEN */
768                         0x0000000f, /* EMC_RW2PDEN */
769                         0x00000009, /* EMC_TXSR */
770                         0x00000009, /* EMC_TXSRDLL */
771                         0x00000004, /* EMC_TCKE */
772                         0x00000002, /* EMC_TFAW */
773                         0x00000000, /* EMC_TRPAB */
774                         0x00000004, /* EMC_TCLKSTABLE */
775                         0x00000005, /* EMC_TCLKSTOP */
776                         0x0000018e, /* EMC_TREFBW */
777                         0x00000000, /* EMC_QUSE_EXTRA */
778                         0x00000004, /* EMC_FBIO_CFG6 */
779                         0x00000000, /* EMC_ODT_WRITE */
780                         0x00000000, /* EMC_ODT_READ */
781                         0x00006288, /* EMC_FBIO_CFG5 */
782                         0x007800a4, /* EMC_CFG_DIG_DLL */
783                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
784                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
785                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
786                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
787                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
788                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
789                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
790                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
791                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
792                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
793                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
794                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
795                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
796                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
797                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
798                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
799                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
800                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
801                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
802                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
803                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
804                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
805                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
806                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
807                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
808                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
809                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
810                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
811                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
812                         0x000002a0, /* EMC_XM2CMDPADCTRL */
813                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
814                         0x00000000, /* EMC_XM2DQPADCTRL2 */
815                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
816                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
817                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
818                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
819                         0x08000168, /* EMC_XM2QUSEPADCTRL */
820                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
821                         0x00000802, /* EMC_CTT_TERM_CTRL */
822                         0x00000000, /* EMC_ZCAL_INTERVAL */
823                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
824                         0x000c000c, /* EMC_MRS_WAIT_CNT */
825                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
826                         0x00000000, /* EMC_CTT */
827                         0x00000000, /* EMC_CTT_DURATION */
828                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
829                         0x00000001, /* MC_EMEM_ARB_CFG */
830                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
831                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
832                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
833                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
834                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
835                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
836                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
837                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
838                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
839                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
840                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
841                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
842                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
843                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
844                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
845                         0x73430303, /* MC_EMEM_ARB_MISC0 */
846                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
847                         0xd8000000, /* EMC_FBIO_SPARE */
848                         0xff00ff00, /* EMC_CFG_RSV */
849                 },
850                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
851                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
852                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
853                 0x80001221, /* Mode Register 0 */
854                 0x80100003, /* Mode Register 1 */
855                 0x80200008, /* Mode Register 2 */
856                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
857         },
858         {
859                 0x32,       /* Rev 3.2 */
860                 102000,     /* SDRAM frequency */
861                 {
862                         0x00000004, /* EMC_RC */
863                         0x00000010, /* EMC_RFC */
864                         0x00000003, /* EMC_RAS */
865                         0x00000001, /* EMC_RP */
866                         0x00000002, /* EMC_R2W */
867                         0x0000000a, /* EMC_W2R */
868                         0x00000003, /* EMC_R2P */
869                         0x0000000b, /* EMC_W2P */
870                         0x00000001, /* EMC_RD_RCD */
871                         0x00000001, /* EMC_WR_RCD */
872                         0x00000003, /* EMC_RRD */
873                         0x00000001, /* EMC_REXT */
874                         0x00000000, /* EMC_WEXT */
875                         0x00000005, /* EMC_WDV */
876                         0x00000005, /* EMC_QUSE */
877                         0x00000004, /* EMC_QRST */
878                         0x00000007, /* EMC_QSAFE */
879                         0x0000000c, /* EMC_RDV */
880                         0x00000303, /* EMC_REFRESH */
881                         0x00000000, /* EMC_BURST_REFRESH_NUM */
882                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
883                         0x00000002, /* EMC_PDEX2WR */
884                         0x00000002, /* EMC_PDEX2RD */
885                         0x00000001, /* EMC_PCHG2PDEN */
886                         0x00000000, /* EMC_ACT2PDEN */
887                         0x00000007, /* EMC_AR2PDEN */
888                         0x0000000f, /* EMC_RW2PDEN */
889                         0x00000012, /* EMC_TXSR */
890                         0x00000012, /* EMC_TXSRDLL */
891                         0x00000004, /* EMC_TCKE */
892                         0x00000004, /* EMC_TFAW */
893                         0x00000000, /* EMC_TRPAB */
894                         0x00000004, /* EMC_TCLKSTABLE */
895                         0x00000005, /* EMC_TCLKSTOP */
896                         0x0000031c, /* EMC_TREFBW */
897                         0x00000000, /* EMC_QUSE_EXTRA */
898                         0x00000004, /* EMC_FBIO_CFG6 */
899                         0x00000000, /* EMC_ODT_WRITE */
900                         0x00000000, /* EMC_ODT_READ */
901                         0x00006288, /* EMC_FBIO_CFG5 */
902                         0x007800a4, /* EMC_CFG_DIG_DLL */
903                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
904                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
905                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
906                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
907                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
908                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
909                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
910                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
911                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
912                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
913                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
914                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
915                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
916                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
917                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
918                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
919                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
920                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
921                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
922                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
923                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
924                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
925                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
926                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
927                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
928                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
929                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
930                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
931                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
932                         0x000002a0, /* EMC_XM2CMDPADCTRL */
933                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
934                         0x00000000, /* EMC_XM2DQPADCTRL2 */
935                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
936                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
937                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
938                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
939                         0x08000168, /* EMC_XM2QUSEPADCTRL */
940                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
941                         0x00000802, /* EMC_CTT_TERM_CTRL */
942                         0x00000000, /* EMC_ZCAL_INTERVAL */
943                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
944                         0x000c000c, /* EMC_MRS_WAIT_CNT */
945                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
946                         0x00000000, /* EMC_CTT */
947                         0x00000000, /* EMC_CTT_DURATION */
948                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
949                         0x00000001, /* MC_EMEM_ARB_CFG */
950                         0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
951                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
952                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
953                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
954                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
955                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
956                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
957                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
958                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
959                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
960                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
961                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
962                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
963                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
964                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
965                         0x72830504, /* MC_EMEM_ARB_MISC0 */
966                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
967                         0xd8000000, /* EMC_FBIO_SPARE */
968                         0xff00ff00, /* EMC_CFG_RSV */
969                 },
970                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
971                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
972                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
973                 0x80001221, /* Mode Register 0 */
974                 0x80100003, /* Mode Register 1 */
975                 0x80200008, /* Mode Register 2 */
976                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
977         },
978         {
979                 0x32,       /* Rev 3.2 */
980                 204000,     /* SDRAM frequency */
981                 {
982                         0x00000009, /* EMC_RC */
983                         0x00000020, /* EMC_RFC */
984                         0x00000007, /* EMC_RAS */
985                         0x00000002, /* EMC_RP */
986                         0x00000002, /* EMC_R2W */
987                         0x0000000a, /* EMC_W2R */
988                         0x00000005, /* EMC_R2P */
989                         0x0000000b, /* EMC_W2P */
990                         0x00000002, /* EMC_RD_RCD */
991                         0x00000002, /* EMC_WR_RCD */
992                         0x00000003, /* EMC_RRD */
993                         0x00000001, /* EMC_REXT */
994                         0x00000000, /* EMC_WEXT */
995                         0x00000005, /* EMC_WDV */
996                         0x00000005, /* EMC_QUSE */
997                         0x00000004, /* EMC_QRST */
998                         0x00000009, /* EMC_QSAFE */
999                         0x0000000b, /* EMC_RDV */
1000                         0x00000607, /* EMC_REFRESH */
1001                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1002                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
1003                         0x00000002, /* EMC_PDEX2WR */
1004                         0x00000002, /* EMC_PDEX2RD */
1005                         0x00000001, /* EMC_PCHG2PDEN */
1006                         0x00000000, /* EMC_ACT2PDEN */
1007                         0x00000007, /* EMC_AR2PDEN */
1008                         0x0000000f, /* EMC_RW2PDEN */
1009                         0x00000023, /* EMC_TXSR */
1010                         0x00000023, /* EMC_TXSRDLL */
1011                         0x00000004, /* EMC_TCKE */
1012                         0x00000007, /* EMC_TFAW */
1013                         0x00000000, /* EMC_TRPAB */
1014                         0x00000004, /* EMC_TCLKSTABLE */
1015                         0x00000005, /* EMC_TCLKSTOP */
1016                         0x00000638, /* EMC_TREFBW */
1017                         0x00000006, /* EMC_QUSE_EXTRA */
1018                         0x00000004, /* EMC_FBIO_CFG6 */
1019                         0x00000000, /* EMC_ODT_WRITE */
1020                         0x00000000, /* EMC_ODT_READ */
1021                         0x00004288, /* EMC_FBIO_CFG5 */
1022                         0x004400a4, /* EMC_CFG_DIG_DLL */
1023                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1024                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
1025                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
1026                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
1027                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
1028                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
1029                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
1030                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
1031                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
1032                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1033                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1034                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1035                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1036                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1037                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1038                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1039                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1040                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1041                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1042                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1043                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1044                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1045                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1046                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1047                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1048                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
1049                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
1050                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
1051                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
1052                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1053                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
1054                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1055                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1056                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
1057                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1058                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1059                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1060                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
1061                         0x00000802, /* EMC_CTT_TERM_CTRL */
1062                         0x00020000, /* EMC_ZCAL_INTERVAL */
1063                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1064                         0x000c000c, /* EMC_MRS_WAIT_CNT */
1065                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1066                         0x00000000, /* EMC_CTT */
1067                         0x00000000, /* EMC_CTT_DURATION */
1068                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
1069                         0x00000003, /* MC_EMEM_ARB_CFG */
1070                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1071                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1072                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
1073                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
1074                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
1075                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
1076                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1077                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1078                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1079                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1080                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
1081                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
1082                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1083                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
1084                         0x000a0505, /* MC_EMEM_ARB_DA_COVERS */
1085                         0x72440a06, /* MC_EMEM_ARB_MISC0 */
1086                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1087                         0xe8000000, /* EMC_FBIO_SPARE */
1088                         0xff00ff00, /* EMC_CFG_RSV */
1089                 },
1090                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1091                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1092                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1093                 0x80001221, /* Mode Register 0 */
1094                 0x80100003, /* Mode Register 1 */
1095                 0x80200008, /* Mode Register 2 */
1096                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
1097         },
1098         {
1099                 0x32,       /* Rev 3.2 */
1100                 375000,     /* SDRAM frequency */
1101                 {
1102                         0x00000011, /* EMC_RC */
1103                         0x0000003a, /* EMC_RFC */
1104                         0x0000000c, /* EMC_RAS */
1105                         0x00000004, /* EMC_RP */
1106                         0x00000003, /* EMC_R2W */
1107                         0x00000008, /* EMC_W2R */
1108                         0x00000002, /* EMC_R2P */
1109                         0x0000000a, /* EMC_W2P */
1110                         0x00000004, /* EMC_RD_RCD */
1111                         0x00000004, /* EMC_WR_RCD */
1112                         0x00000002, /* EMC_RRD */
1113                         0x00000001, /* EMC_REXT */
1114                         0x00000000, /* EMC_WEXT */
1115                         0x00000004, /* EMC_WDV */
1116                         0x00000006, /* EMC_QUSE */
1117                         0x00000004, /* EMC_QRST */
1118                         0x00000008, /* EMC_QSAFE */
1119                         0x0000000d, /* EMC_RDV */
1120                         0x00000b2d, /* EMC_REFRESH */
1121                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1122                         0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
1123                         0x00000008, /* EMC_PDEX2WR */
1124                         0x00000008, /* EMC_PDEX2RD */
1125                         0x00000001, /* EMC_PCHG2PDEN */
1126                         0x00000000, /* EMC_ACT2PDEN */
1127                         0x00000007, /* EMC_AR2PDEN */
1128                         0x0000000f, /* EMC_RW2PDEN */
1129                         0x00000040, /* EMC_TXSR */
1130                         0x00000200, /* EMC_TXSRDLL */
1131                         0x00000009, /* EMC_TCKE */
1132                         0x0000000c, /* EMC_TFAW */
1133                         0x00000000, /* EMC_TRPAB */
1134                         0x00000004, /* EMC_TCLKSTABLE */
1135                         0x00000005, /* EMC_TCLKSTOP */
1136                         0x00000b6d, /* EMC_TREFBW */
1137                         0x00000000, /* EMC_QUSE_EXTRA */
1138                         0x00000006, /* EMC_FBIO_CFG6 */
1139                         0x00000000, /* EMC_ODT_WRITE */
1140                         0x00000000, /* EMC_ODT_READ */
1141                         0x00007088, /* EMC_FBIO_CFG5 */
1142                         0x00200084, /* EMC_CFG_DIG_DLL */
1143                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1144                         0x0003c000, /* EMC_DLL_XFORM_DQS0 */
1145                         0x0003c000, /* EMC_DLL_XFORM_DQS1 */
1146                         0x0003c000, /* EMC_DLL_XFORM_DQS2 */
1147                         0x0003c000, /* EMC_DLL_XFORM_DQS3 */
1148                         0x0003c000, /* EMC_DLL_XFORM_DQS4 */
1149                         0x0003c000, /* EMC_DLL_XFORM_DQS5 */
1150                         0x0003c000, /* EMC_DLL_XFORM_DQS6 */
1151                         0x0003c000, /* EMC_DLL_XFORM_DQS7 */
1152                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1153                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1154                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1155                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1156                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1157                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1158                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1159                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1160                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1161                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1162                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1163                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1164                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1165                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1166                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1167                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1168                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
1169                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
1170                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
1171                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
1172                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1173                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1174                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1175                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1176                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1177                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1178                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1179                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1180                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1181                         0x00000802, /* EMC_CTT_TERM_CTRL */
1182                         0x00020000, /* EMC_ZCAL_INTERVAL */
1183                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1184                         0x0184000c, /* EMC_MRS_WAIT_CNT */
1185                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1186                         0x00000000, /* EMC_CTT */
1187                         0x00000000, /* EMC_CTT_DURATION */
1188                         0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
1189                         0x00000005, /* MC_EMEM_ARB_CFG */
1190                         0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1191                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1192                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1193                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
1194                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
1195                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
1196                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1197                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1198                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1199                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1200                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1201                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1202                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1203                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1204                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
1205                         0x75c6110a, /* MC_EMEM_ARB_MISC0 */
1206                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1207                         0x58000000, /* EMC_FBIO_SPARE */
1208                         0xff00ff88, /* EMC_CFG_RSV */
1209                 },
1210                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1211                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1212                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1213                 0x80000521, /* Mode Register 0 */
1214                 0x80100002, /* Mode Register 1 */
1215                 0x80200000, /* Mode Register 2 */
1216                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1217         },
1218         {
1219                 0x32,       /* Rev 3.2 */
1220                 400000,     /* SDRAM frequency */
1221                 {
1222                         0x00000012, /* EMC_RC */
1223                         0x00000040, /* EMC_RFC */
1224                         0x0000000d, /* EMC_RAS */
1225                         0x00000004, /* EMC_RP */
1226                         0x00000002, /* EMC_R2W */
1227                         0x00000009, /* EMC_W2R */
1228                         0x00000002, /* EMC_R2P */
1229                         0x0000000c, /* EMC_W2P */
1230                         0x00000004, /* EMC_RD_RCD */
1231                         0x00000004, /* EMC_WR_RCD */
1232                         0x00000002, /* EMC_RRD */
1233                         0x00000001, /* EMC_REXT */
1234                         0x00000000, /* EMC_WEXT */
1235                         0x00000005, /* EMC_WDV */
1236                         0x00000007, /* EMC_QUSE */
1237                         0x00000005, /* EMC_QRST */
1238                         0x00000008, /* EMC_QSAFE */
1239                         0x0000000e, /* EMC_RDV */
1240                         0x00000c2e, /* EMC_REFRESH */
1241                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1242                         0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */
1243                         0x00000008, /* EMC_PDEX2WR */
1244                         0x00000008, /* EMC_PDEX2RD */
1245                         0x00000001, /* EMC_PCHG2PDEN */
1246                         0x00000000, /* EMC_ACT2PDEN */
1247                         0x00000008, /* EMC_AR2PDEN */
1248                         0x00000011, /* EMC_RW2PDEN */
1249                         0x00000046, /* EMC_TXSR */
1250                         0x00000200, /* EMC_TXSRDLL */
1251                         0x0000000a, /* EMC_TCKE */
1252                         0x0000000d, /* EMC_TFAW */
1253                         0x00000000, /* EMC_TRPAB */
1254                         0x00000004, /* EMC_TCLKSTABLE */
1255                         0x00000005, /* EMC_TCLKSTOP */
1256                         0x00000c6f, /* EMC_TREFBW */
1257                         0x00000000, /* EMC_QUSE_EXTRA */
1258                         0x00000006, /* EMC_FBIO_CFG6 */
1259                         0x00000000, /* EMC_ODT_WRITE */
1260                         0x00000000, /* EMC_ODT_READ */
1261                         0x00007088, /* EMC_FBIO_CFG5 */
1262                         0x001c0084, /* EMC_CFG_DIG_DLL */
1263                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1264                         0x00034000, /* EMC_DLL_XFORM_DQS0 */
1265                         0x00034000, /* EMC_DLL_XFORM_DQS1 */
1266                         0x00034000, /* EMC_DLL_XFORM_DQS2 */
1267                         0x00034000, /* EMC_DLL_XFORM_DQS3 */
1268                         0x00034000, /* EMC_DLL_XFORM_DQS4 */
1269                         0x00034000, /* EMC_DLL_XFORM_DQS5 */
1270                         0x00034000, /* EMC_DLL_XFORM_DQS6 */
1271                         0x00034000, /* EMC_DLL_XFORM_DQS7 */
1272                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1273                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1274                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1275                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1276                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1277                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1278                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1279                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1280                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1281                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1282                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1283                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1284                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1285                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1286                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1287                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1288                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
1289                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
1290                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
1291                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
1292                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1293                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1294                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1295                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1296                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1297                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1298                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1299                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1300                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1301                         0x00000802, /* EMC_CTT_TERM_CTRL */
1302                         0x00020000, /* EMC_ZCAL_INTERVAL */
1303                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1304                         0x017f000c, /* EMC_MRS_WAIT_CNT */
1305                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1306                         0x00000000, /* EMC_CTT */
1307                         0x00000000, /* EMC_CTT_DURATION */
1308                         0x80001941, /* EMC_DYN_SELF_REF_CONTROL */
1309                         0x00000006, /* MC_EMEM_ARB_CFG */
1310                         0x8000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1311                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
1312                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
1313                         0x0000000a, /* MC_EMEM_ARB_TIMING_RC */
1314                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1315                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1316                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1317                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1318                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1319                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1320                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1321                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1322                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1323                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1324                         0x000e070a, /* MC_EMEM_ARB_DA_COVERS */
1325                         0x7547130b, /* MC_EMEM_ARB_MISC0 */
1326                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1327                         0x58000000, /* EMC_FBIO_SPARE */
1328                         0xff00ff88, /* EMC_CFG_RSV */
1329                 },
1330                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1331                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1332                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1333                 0x80000731, /* Mode Register 0 */
1334                 0x80100002, /* Mode Register 1 */
1335                 0x80200008, /* Mode Register 2 */
1336                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1337         },
1338         {
1339                 0x32,       /* Rev 3.2 */
1340                 450000,     /* SDRAM frequency */
1341                 {
1342                         0x00000014, /* EMC_RC */
1343                         0x00000046, /* EMC_RFC */
1344                         0x0000000e, /* EMC_RAS */
1345                         0x00000005, /* EMC_RP */
1346                         0x00000003, /* EMC_R2W */
1347                         0x00000009, /* EMC_W2R */
1348                         0x00000002, /* EMC_R2P */
1349                         0x0000000c, /* EMC_W2P */
1350                         0x00000005, /* EMC_RD_RCD */
1351                         0x00000005, /* EMC_WR_RCD */
1352                         0x00000002, /* EMC_RRD */
1353                         0x00000001, /* EMC_REXT */
1354                         0x00000000, /* EMC_WEXT */
1355                         0x00000005, /* EMC_WDV */
1356                         0x00000007, /* EMC_QUSE */
1357                         0x00000005, /* EMC_QRST */
1358                         0x0000000a, /* EMC_QSAFE */
1359                         0x0000000e, /* EMC_RDV */
1360                         0x00000d76, /* EMC_REFRESH */
1361                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1362                         0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */
1363                         0x00000001, /* EMC_PDEX2WR */
1364                         0x00000009, /* EMC_PDEX2RD */
1365                         0x00000001, /* EMC_PCHG2PDEN */
1366                         0x00000000, /* EMC_ACT2PDEN */
1367                         0x00000009, /* EMC_AR2PDEN */
1368                         0x00000011, /* EMC_RW2PDEN */
1369                         0x0000004d, /* EMC_TXSR */
1370                         0x00000200, /* EMC_TXSRDLL */
1371                         0x00000004, /* EMC_TCKE */
1372                         0x0000000e, /* EMC_TFAW */
1373                         0x00000000, /* EMC_TRPAB */
1374                         0x00000004, /* EMC_TCLKSTABLE */
1375                         0x00000005, /* EMC_TCLKSTOP */
1376                         0x00000db6, /* EMC_TREFBW */
1377                         0x00000000, /* EMC_QUSE_EXTRA */
1378                         0x00000006, /* EMC_FBIO_CFG6 */
1379                         0x00000000, /* EMC_ODT_WRITE */
1380                         0x00000000, /* EMC_ODT_READ */
1381                         0x00007088, /* EMC_FBIO_CFG5 */
1382                         0x00180084, /* EMC_CFG_DIG_DLL */
1383                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1384                         0x00022000, /* EMC_DLL_XFORM_DQS0 */
1385                         0x00022000, /* EMC_DLL_XFORM_DQS1 */
1386                         0x00022000, /* EMC_DLL_XFORM_DQS2 */
1387                         0x00022000, /* EMC_DLL_XFORM_DQS3 */
1388                         0x00022000, /* EMC_DLL_XFORM_DQS4 */
1389                         0x00022000, /* EMC_DLL_XFORM_DQS5 */
1390                         0x00022000, /* EMC_DLL_XFORM_DQS6 */
1391                         0x00022000, /* EMC_DLL_XFORM_DQS7 */
1392                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1393                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1394                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1395                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1396                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1397                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1398                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1399                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1400                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1401                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1402                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1403                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1404                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1405                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1406                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1407                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1408                         0x00030000, /* EMC_DLL_XFORM_DQ0 */
1409                         0x00030000, /* EMC_DLL_XFORM_DQ1 */
1410                         0x00030000, /* EMC_DLL_XFORM_DQ2 */
1411                         0x00030000, /* EMC_DLL_XFORM_DQ3 */
1412                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1413                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1414                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1415                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1416                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1417                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1418                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1419                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1420                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1421                         0x00000802, /* EMC_CTT_TERM_CTRL */
1422                         0x00020000, /* EMC_ZCAL_INTERVAL */
1423                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1424                         0x0178000c, /* EMC_MRS_WAIT_CNT */
1425                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1426                         0x00000000, /* EMC_CTT */
1427                         0x00000000, /* EMC_CTT_DURATION */
1428                         0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */
1429                         0x00000006, /* MC_EMEM_ARB_CFG */
1430                         0x80000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1431                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1432                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1433                         0x0000000b, /* MC_EMEM_ARB_TIMING_RC */
1434                         0x00000006, /* MC_EMEM_ARB_TIMING_RAS */
1435                         0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
1436                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1437                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1438                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1439                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1440                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1441                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1442                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1443                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1444                         0x000f080b, /* MC_EMEM_ARB_DA_COVERS */
1445                         0x70a7150c, /* MC_EMEM_ARB_MISC0 */
1446                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1447                         0xe8000000, /* EMC_FBIO_SPARE */
1448                         0xff00ff8b, /* EMC_CFG_RSV */
1449                 },
1450                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1451                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1452                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1453                 0x80000731, /* Mode Register 0 */
1454                 0x80100002, /* Mode Register 1 */
1455                 0x80200008, /* Mode Register 2 */
1456                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1457         },
1458         {
1459                 0x32,       /* Rev 3.2 */
1460                 533000,     /* SDRAM frequency */
1461                 {
1462                         0x00000018, /* EMC_RC */
1463                         0x00000054, /* EMC_RFC */
1464                         0x00000011, /* EMC_RAS */
1465                         0x00000006, /* EMC_RP */
1466                         0x00000003, /* EMC_R2W */
1467                         0x00000009, /* EMC_W2R */
1468                         0x00000002, /* EMC_R2P */
1469                         0x0000000d, /* EMC_W2P */
1470                         0x00000006, /* EMC_RD_RCD */
1471                         0x00000006, /* EMC_WR_RCD */
1472                         0x00000002, /* EMC_RRD */
1473                         0x00000001, /* EMC_REXT */
1474                         0x00000000, /* EMC_WEXT */
1475                         0x00000005, /* EMC_WDV */
1476                         0x00000008, /* EMC_QUSE */
1477                         0x00000006, /* EMC_QRST */
1478                         0x00000008, /* EMC_QSAFE */
1479                         0x00000010, /* EMC_RDV */
1480                         0x00000ffd, /* EMC_REFRESH */
1481                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1482                         0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */
1483                         0x0000000b, /* EMC_PDEX2WR */
1484                         0x0000000b, /* EMC_PDEX2RD */
1485                         0x00000001, /* EMC_PCHG2PDEN */
1486                         0x00000000, /* EMC_ACT2PDEN */
1487                         0x0000000a, /* EMC_AR2PDEN */
1488                         0x00000012, /* EMC_RW2PDEN */
1489                         0x0000005b, /* EMC_TXSR */
1490                         0x00000200, /* EMC_TXSRDLL */
1491                         0x0000000d, /* EMC_TCKE */
1492                         0x00000010, /* EMC_TFAW */
1493                         0x00000000, /* EMC_TRPAB */
1494                         0x00000005, /* EMC_TCLKSTABLE */
1495                         0x00000006, /* EMC_TCLKSTOP */
1496                         0x0000103e, /* EMC_TREFBW */
1497                         0x00000000, /* EMC_QUSE_EXTRA */
1498                         0x00000006, /* EMC_FBIO_CFG6 */
1499                         0x00000000, /* EMC_ODT_WRITE */
1500                         0x00000000, /* EMC_ODT_READ */
1501                         0x00007088, /* EMC_FBIO_CFG5 */
1502                         0x00120084, /* EMC_CFG_DIG_DLL */
1503                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1504                         0x00010000, /* EMC_DLL_XFORM_DQS0 */
1505                         0x00010000, /* EMC_DLL_XFORM_DQS1 */
1506                         0x00010000, /* EMC_DLL_XFORM_DQS2 */
1507                         0x00010000, /* EMC_DLL_XFORM_DQS3 */
1508                         0x00010000, /* EMC_DLL_XFORM_DQS4 */
1509                         0x00010000, /* EMC_DLL_XFORM_DQS5 */
1510                         0x00010000, /* EMC_DLL_XFORM_DQS6 */
1511                         0x00010000, /* EMC_DLL_XFORM_DQS7 */
1512                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1513                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1514                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1515                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1516                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1517                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1518                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1519                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1520                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1521                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1522                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1523                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1524                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1525                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1526                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1527                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1528                         0x00020000, /* EMC_DLL_XFORM_DQ0 */
1529                         0x00020000, /* EMC_DLL_XFORM_DQ1 */
1530                         0x00020000, /* EMC_DLL_XFORM_DQ2 */
1531                         0x00020000, /* EMC_DLL_XFORM_DQ3 */
1532                         0x000006a0, /* EMC_XM2CMDPADCTRL */
1533                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
1534                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1535                         0x77ffc084, /* EMC_XM2CLKPADCTRL */
1536                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1537                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
1538                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
1539                         0x08000168, /* EMC_XM2QUSEPADCTRL */
1540                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
1541                         0x00000802, /* EMC_CTT_TERM_CTRL */
1542                         0x00000000, /* EMC_ZCAL_INTERVAL */
1543                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
1544                         0x01ab000c, /* EMC_MRS_WAIT_CNT */
1545                         0xa0f10404, /* EMC_AUTO_CAL_CONFIG */
1546                         0x00000000, /* EMC_CTT */
1547                         0x00000000, /* EMC_CTT_DURATION */
1548                         0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */
1549                         0x00000008, /* MC_EMEM_ARB_CFG */
1550                         0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1551                         0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
1552                         0x00000003, /* MC_EMEM_ARB_TIMING_RP */
1553                         0x0000000d, /* MC_EMEM_ARB_TIMING_RC */
1554                         0x00000008, /* MC_EMEM_ARB_TIMING_RAS */
1555                         0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
1556                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1557                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1558                         0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1559                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1560                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1561                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
1562                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
1563                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
1564                         0x0010090d, /* MC_EMEM_ARB_DA_COVERS */
1565                         0x7028180e, /* MC_EMEM_ARB_MISC0 */
1566                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1567                         0x00000000, /* EMC_FBIO_SPARE */
1568                         0xff00ff00, /* EMC_CFG_RSV */
1569                 },
1570                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1571                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1572                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
1573                 0x80000941, /* Mode Register 0 */
1574                 0x80100002, /* Mode Register 1 */
1575                 0x80200008, /* Mode Register 2 */
1576                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1577         },
1578         {
1579                 0x32,       /* Rev 3.2 */
1580                 667000,     /* SDRAM frequency */
1581                 {
1582                         0x0000001f, /* EMC_RC */
1583                         0x00000069, /* EMC_RFC */
1584                         0x00000016, /* EMC_RAS */
1585                         0x00000008, /* EMC_RP */
1586                         0x00000004, /* EMC_R2W */
1587                         0x0000000c, /* EMC_W2R */
1588                         0x00000003, /* EMC_R2P */
1589                         0x00000011, /* EMC_W2P */
1590                         0x00000008, /* EMC_RD_RCD */
1591                         0x00000008, /* EMC_WR_RCD */
1592                         0x00000002, /* EMC_RRD */
1593                         0x00000001, /* EMC_REXT */
1594                         0x00000000, /* EMC_WEXT */
1595                         0x00000007, /* EMC_WDV */
1596                         0x0000000b, /* EMC_QUSE */
1597                         0x00000009, /* EMC_QRST */
1598                         0x0000000c, /* EMC_QSAFE */
1599                         0x00000011, /* EMC_RDV */
1600                         0x00001412, /* EMC_REFRESH */
1601                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1602                         0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
1603                         0x0000000e, /* EMC_PDEX2WR */
1604                         0x0000000e, /* EMC_PDEX2RD */
1605                         0x00000001, /* EMC_PCHG2PDEN */
1606                         0x00000000, /* EMC_ACT2PDEN */
1607                         0x0000000c, /* EMC_AR2PDEN */
1608                         0x00000016, /* EMC_RW2PDEN */
1609                         0x00000072, /* EMC_TXSR */
1610                         0x00000200, /* EMC_TXSRDLL */
1611                         0x00000010, /* EMC_TCKE */
1612                         0x00000015, /* EMC_TFAW */
1613                         0x00000000, /* EMC_TRPAB */
1614                         0x00000006, /* EMC_TCLKSTABLE */
1615                         0x00000007, /* EMC_TCLKSTOP */
1616                         0x00001453, /* EMC_TREFBW */
1617                         0x0000000c, /* EMC_QUSE_EXTRA */
1618                         0x00000004, /* EMC_FBIO_CFG6 */
1619                         0x00000000, /* EMC_ODT_WRITE */
1620                         0x00000000, /* EMC_ODT_READ */
1621                         0x00005088, /* EMC_FBIO_CFG5 */
1622                         0x40070191, /* EMC_CFG_DIG_DLL */
1623                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1624                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
1625                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
1626                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
1627                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
1628                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
1629                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
1630                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
1631                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
1632                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1633                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1634                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1635                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1636                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1637                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1638                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1639                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1640                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1641                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1642                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1643                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1644                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1645                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1646                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1647                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1648                         0x00000008, /* EMC_DLL_XFORM_DQ0 */
1649                         0x00000008, /* EMC_DLL_XFORM_DQ1 */
1650                         0x00000008, /* EMC_DLL_XFORM_DQ2 */
1651                         0x00000008, /* EMC_DLL_XFORM_DQ3 */
1652                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1653                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
1654                         0x00000000, /* EMC_XM2DQPADCTRL2 */
1655                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1656                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
1657                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
1658                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
1659                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1660                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
1661                         0x00000802, /* EMC_CTT_TERM_CTRL */
1662                         0x00020000, /* EMC_ZCAL_INTERVAL */
1663                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1664                         0x01d6000c, /* EMC_MRS_WAIT_CNT */
1665                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1666                         0x00000000, /* EMC_CTT */
1667                         0x00000000, /* EMC_CTT_DURATION */
1668                         0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
1669                         0x0000000a, /* MC_EMEM_ARB_CFG */
1670                         0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1671                         0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
1672                         0x00000004, /* MC_EMEM_ARB_TIMING_RP */
1673                         0x00000010, /* MC_EMEM_ARB_TIMING_RC */
1674                         0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */
1675                         0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
1676                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
1677                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1678                         0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1679                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1680                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1681                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1682                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
1683                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
1684                         0x00140c10, /* MC_EMEM_ARB_DA_COVERS */
1685                         0x734a1f11, /* MC_EMEM_ARB_MISC0 */
1686                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1687                         0xf8000000, /* EMC_FBIO_SPARE */
1688                         0xff00ff01, /* EMC_CFG_RSV */
1689                 },
1690                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1691                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1692                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1693                 0x80000b71, /* Mode Register 0 */
1694                 0x80100002, /* Mode Register 1 */
1695                 0x80200018, /* Mode Register 2 */
1696                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1697         },
1698         {
1699                 0x32,       /* Rev 3.2 */
1700                 750000,     /* SDRAM frequency */
1701                 {
1702                         0x00000025, /* EMC_RC */
1703                         0x0000007e, /* EMC_RFC */
1704                         0x0000001a, /* EMC_RAS */
1705                         0x00000009, /* EMC_RP */
1706                         0x00000004, /* EMC_R2W */
1707                         0x0000000d, /* EMC_W2R */
1708                         0x00000004, /* EMC_R2P */
1709                         0x00000013, /* EMC_W2P */
1710                         0x00000009, /* EMC_RD_RCD */
1711                         0x00000009, /* EMC_WR_RCD */
1712                         0x00000003, /* EMC_RRD */
1713                         0x00000001, /* EMC_REXT */
1714                         0x00000000, /* EMC_WEXT */
1715                         0x00000007, /* EMC_WDV */
1716                         0x0000000b, /* EMC_QUSE */
1717                         0x00000009, /* EMC_QRST */
1718                         0x0000000c, /* EMC_QSAFE */
1719                         0x00000011, /* EMC_RDV */
1720                         0x0000169a, /* EMC_REFRESH */
1721                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1722                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
1723                         0x00000012, /* EMC_PDEX2WR */
1724                         0x00000012, /* EMC_PDEX2RD */
1725                         0x00000001, /* EMC_PCHG2PDEN */
1726                         0x00000000, /* EMC_ACT2PDEN */
1727                         0x0000000f, /* EMC_AR2PDEN */
1728                         0x00000018, /* EMC_RW2PDEN */
1729                         0x00000088, /* EMC_TXSR */
1730                         0x00000200, /* EMC_TXSRDLL */
1731                         0x00000014, /* EMC_TCKE */
1732                         0x00000018, /* EMC_TFAW */
1733                         0x00000000, /* EMC_TRPAB */
1734                         0x00000007, /* EMC_TCLKSTABLE */
1735                         0x00000008, /* EMC_TCLKSTOP */
1736                         0x00001860, /* EMC_TREFBW */
1737                         0x0000000c, /* EMC_QUSE_EXTRA */
1738                         0x00000004, /* EMC_FBIO_CFG6 */
1739                         0x00000000, /* EMC_ODT_WRITE */
1740                         0x00000000, /* EMC_ODT_READ */
1741                         0x00005088, /* EMC_FBIO_CFG5 */
1742                         0xf0080191, /* EMC_CFG_DIG_DLL */
1743                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1744                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
1745                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
1746                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
1747                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
1748                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
1749                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
1750                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
1751                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
1752                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1753                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1754                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1755                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1756                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1757                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1758                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1759                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1760                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1761                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1762                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1763                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1764                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1765                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1766                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1767                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1768                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
1769                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
1770                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
1771                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
1772                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1773                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
1774                         0x22220000, /* EMC_XM2DQPADCTRL2 */
1775                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1776                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
1777                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
1778                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
1779                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1780                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
1781                         0x00000802, /* EMC_CTT_TERM_CTRL */
1782                         0x00020000, /* EMC_ZCAL_INTERVAL */
1783                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1784                         0x0180000c, /* EMC_MRS_WAIT_CNT */
1785                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1786                         0x00000000, /* EMC_CTT */
1787                         0x00000000, /* EMC_CTT_DURATION */
1788                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
1789                         0x0000000c, /* MC_EMEM_ARB_CFG */
1790                         0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1791                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
1792                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
1793                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
1794                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
1795                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
1796                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1797                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1798                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1799                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1800                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1801                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1802                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
1803                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
1804                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
1805                         0x72ac2414, /* MC_EMEM_ARB_MISC0 */
1806                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1807                         0xf8000000, /* EMC_FBIO_SPARE */
1808                         0xff00ff49, /* EMC_CFG_RSV */
1809                 },
1810                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1811                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1812                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1813                 0x80000d71, /* Mode Register 0 */
1814                 0x80100002, /* Mode Register 1 */
1815                 0x80200018, /* Mode Register 2 */
1816                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1817         },
1818         {
1819                 0x32,       /* Rev 3.2 */
1820                 800000,     /* SDRAM frequency */
1821                 {
1822                         0x00000025, /* EMC_RC */
1823                         0x0000007e, /* EMC_RFC */
1824                         0x0000001a, /* EMC_RAS */
1825                         0x00000009, /* EMC_RP */
1826                         0x00000004, /* EMC_R2W */
1827                         0x0000000d, /* EMC_W2R */
1828                         0x00000004, /* EMC_R2P */
1829                         0x00000013, /* EMC_W2P */
1830                         0x00000009, /* EMC_RD_RCD */
1831                         0x00000009, /* EMC_WR_RCD */
1832                         0x00000003, /* EMC_RRD */
1833                         0x00000001, /* EMC_REXT */
1834                         0x00000000, /* EMC_WEXT */
1835                         0x00000007, /* EMC_WDV */
1836                         0x0000000b, /* EMC_QUSE */
1837                         0x00000009, /* EMC_QRST */
1838                         0x0000000c, /* EMC_QSAFE */
1839                         0x00000011, /* EMC_RDV */
1840                         0x00001820, /* EMC_REFRESH */
1841                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1842                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
1843                         0x00000012, /* EMC_PDEX2WR */
1844                         0x00000012, /* EMC_PDEX2RD */
1845                         0x00000001, /* EMC_PCHG2PDEN */
1846                         0x00000000, /* EMC_ACT2PDEN */
1847                         0x0000000f, /* EMC_AR2PDEN */
1848                         0x00000018, /* EMC_RW2PDEN */
1849                         0x00000088, /* EMC_TXSR */
1850                         0x00000200, /* EMC_TXSRDLL */
1851                         0x00000014, /* EMC_TCKE */
1852                         0x00000018, /* EMC_TFAW */
1853                         0x00000000, /* EMC_TRPAB */
1854                         0x00000007, /* EMC_TCLKSTABLE */
1855                         0x00000008, /* EMC_TCLKSTOP */
1856                         0x00001860, /* EMC_TREFBW */
1857                         0x0000000c, /* EMC_QUSE_EXTRA */
1858                         0x00000004, /* EMC_FBIO_CFG6 */
1859                         0x00000000, /* EMC_ODT_WRITE */
1860                         0x00000000, /* EMC_ODT_READ */
1861                         0x00005088, /* EMC_FBIO_CFG5 */
1862                         0xf0070191, /* EMC_CFG_DIG_DLL */
1863                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1864                         0x0000800a, /* EMC_DLL_XFORM_DQS0 */
1865                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1866                         0x0000000a, /* EMC_DLL_XFORM_DQS2 */
1867                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1868                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1869                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1870                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1871                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1872                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
1873                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
1874                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
1875                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
1876                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
1877                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
1878                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
1879                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
1880                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
1881                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
1882                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
1883                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
1884                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
1885                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
1886                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
1887                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
1888                         0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
1889                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
1890                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
1891                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
1892                         0x000002a0, /* EMC_XM2CMDPADCTRL */
1893                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
1894                         0x22220000, /* EMC_XM2DQPADCTRL2 */
1895                         0x77fff884, /* EMC_XM2CLKPADCTRL */
1896                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
1897                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
1898                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
1899                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
1900                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
1901                         0x00000802, /* EMC_CTT_TERM_CTRL */
1902                         0x00020000, /* EMC_ZCAL_INTERVAL */
1903                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
1904                         0x0180000c, /* EMC_MRS_WAIT_CNT */
1905                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
1906                         0x00000000, /* EMC_CTT */
1907                         0x00000000, /* EMC_CTT_DURATION */
1908                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
1909                         0x0000000c, /* MC_EMEM_ARB_CFG */
1910                         0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
1911                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
1912                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
1913                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
1914                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
1915                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
1916                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
1917                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
1918                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
1919                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
1920                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
1921                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
1922                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
1923                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
1924                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
1925                         0x72ac2414, /* MC_EMEM_ARB_MISC0 */
1926                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
1927                         0xf8000000, /* EMC_FBIO_SPARE */
1928                         0xff00ff49, /* EMC_CFG_RSV */
1929                 },
1930                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
1931                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
1932                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
1933                 0x80000d71, /* Mode Register 0 */
1934                 0x80100002, /* Mode Register 1 */
1935                 0x80200018, /* Mode Register 2 */
1936                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
1937         },
1938         {
1939                 0x32,       /* Rev 3.2 */
1940                 900000,     /* SDRAM frequency */
1941                 {
1942                         0x0000002a, /* EMC_RC */
1943                         0x0000008e, /* EMC_RFC */
1944                         0x0000001e, /* EMC_RAS */
1945                         0x0000000b, /* EMC_RP */
1946                         0x00000006, /* EMC_R2W */
1947                         0x0000000f, /* EMC_W2R */
1948                         0x00000005, /* EMC_R2P */
1949                         0x00000016, /* EMC_W2P */
1950                         0x0000000b, /* EMC_RD_RCD */
1951                         0x0000000b, /* EMC_WR_RCD */
1952                         0x00000004, /* EMC_RRD */
1953                         0x00000001, /* EMC_REXT */
1954                         0x00000000, /* EMC_WEXT */
1955                         0x00000008, /* EMC_WDV */
1956                         0x0000000d, /* EMC_QUSE */
1957                         0x0000000b, /* EMC_QRST */
1958                         0x0000000b, /* EMC_QSAFE */
1959                         0x00000014, /* EMC_RDV */
1960                         0x00001b2c, /* EMC_REFRESH */
1961                         0x00000000, /* EMC_BURST_REFRESH_NUM */
1962                         0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */
1963                         0x00000004, /* EMC_PDEX2WR */
1964                         0x00000014, /* EMC_PDEX2RD */
1965                         0x00000001, /* EMC_PCHG2PDEN */
1966                         0x00000000, /* EMC_ACT2PDEN */
1967                         0x00000011, /* EMC_AR2PDEN */
1968                         0x0000001b, /* EMC_RW2PDEN */
1969                         0x00000099, /* EMC_TXSR */
1970                         0x00000200, /* EMC_TXSRDLL */
1971                         0x00000006, /* EMC_TCKE */
1972                         0x0000001b, /* EMC_TFAW */
1973                         0x00000000, /* EMC_TRPAB */
1974                         0x00000008, /* EMC_TCLKSTABLE */
1975                         0x00000009, /* EMC_TCLKSTOP */
1976                         0x00001b6c, /* EMC_TREFBW */
1977                         0x0000000e, /* EMC_QUSE_EXTRA */
1978                         0x00000004, /* EMC_FBIO_CFG6 */
1979                         0x00000000, /* EMC_ODT_WRITE */
1980                         0x00000000, /* EMC_ODT_READ */
1981                         0x00005088, /* EMC_FBIO_CFG5 */
1982                         0xf0040191, /* EMC_CFG_DIG_DLL */
1983                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
1984                         0x0000800a, /* EMC_DLL_XFORM_DQS0 */
1985                         0x0000000a, /* EMC_DLL_XFORM_DQS1 */
1986                         0x007fc00a, /* EMC_DLL_XFORM_DQS2 */
1987                         0x0000000a, /* EMC_DLL_XFORM_DQS3 */
1988                         0x0000000a, /* EMC_DLL_XFORM_DQS4 */
1989                         0x0000000a, /* EMC_DLL_XFORM_DQS5 */
1990                         0x0000000a, /* EMC_DLL_XFORM_DQS6 */
1991                         0x0000000a, /* EMC_DLL_XFORM_DQS7 */
1992                         0x0001c000, /* EMC_DLL_XFORM_QUSE0 */
1993                         0x0001c000, /* EMC_DLL_XFORM_QUSE1 */
1994                         0x0001c000, /* EMC_DLL_XFORM_QUSE2 */
1995                         0x0001c000, /* EMC_DLL_XFORM_QUSE3 */
1996                         0x0001c000, /* EMC_DLL_XFORM_QUSE4 */
1997                         0x0001c000, /* EMC_DLL_XFORM_QUSE5 */
1998                         0x0001c000, /* EMC_DLL_XFORM_QUSE6 */
1999                         0x0001c000, /* EMC_DLL_XFORM_QUSE7 */
2000                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2001                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2002                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2003                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2004                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2005                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2006                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2007                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2008                         0x007fc00a, /* EMC_DLL_XFORM_DQ0 */
2009                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
2010                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
2011                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
2012                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2013                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2014                         0x22220000, /* EMC_XM2DQPADCTRL2 */
2015                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2016                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
2017                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
2018                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2019                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2020                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
2021                         0x00000802, /* EMC_CTT_TERM_CTRL */
2022                         0x00020000, /* EMC_ZCAL_INTERVAL */
2023                         0x00000120, /* EMC_ZCAL_WAIT_CNT */
2024                         0x0128000c, /* EMC_MRS_WAIT_CNT */
2025                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2026                         0x00000000, /* EMC_CTT */
2027                         0x00000000, /* EMC_CTT_DURATION */
2028                         0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */
2029                         0x0000000d, /* MC_EMEM_ARB_CFG */
2030                         0x800000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2031                         0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
2032                         0x00000006, /* MC_EMEM_ARB_TIMING_RP */
2033                         0x00000016, /* MC_EMEM_ARB_TIMING_RC */
2034                         0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
2035                         0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
2036                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2037                         0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2038                         0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2039                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2040                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2041                         0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
2042                         0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
2043                         0x09050202, /* MC_EMEM_ARB_DA_TURNS */
2044                         0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
2045                         0x714e2917, /* MC_EMEM_ARB_MISC0 */
2046                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2047                         0xe8000000, /* EMC_FBIO_SPARE */
2048                         0xff00ff4b, /* EMC_CFG_RSV */
2049                 },
2050                 0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
2051                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2052                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2053                 0x80000f15, /* Mode Register 0 */
2054                 0x80100002, /* Mode Register 1 */
2055                 0x80200020, /* Mode Register 2 */
2056                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2057         },
2058 };
2059
2060 static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2_2GB1R[] = {
2061         {
2062                 0x32,       /* Rev 3.2 */
2063                 51000,      /* SDRAM frequency */
2064                 {
2065                         0x00000002, /* EMC_RC */
2066                         0x0000000d, /* EMC_RFC */
2067                         0x00000001, /* EMC_RAS */
2068                         0x00000000, /* EMC_RP */
2069                         0x00000002, /* EMC_R2W */
2070                         0x0000000a, /* EMC_W2R */
2071                         0x00000003, /* EMC_R2P */
2072                         0x0000000b, /* EMC_W2P */
2073                         0x00000000, /* EMC_RD_RCD */
2074                         0x00000000, /* EMC_WR_RCD */
2075                         0x00000003, /* EMC_RRD */
2076                         0x00000001, /* EMC_REXT */
2077                         0x00000000, /* EMC_WEXT */
2078                         0x00000005, /* EMC_WDV */
2079                         0x00000005, /* EMC_QUSE */
2080                         0x00000004, /* EMC_QRST */
2081                         0x00000009, /* EMC_QSAFE */
2082                         0x0000000b, /* EMC_RDV */
2083                         0x00000181, /* EMC_REFRESH */
2084                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2085                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
2086                         0x00000002, /* EMC_PDEX2WR */
2087                         0x00000002, /* EMC_PDEX2RD */
2088                         0x00000001, /* EMC_PCHG2PDEN */
2089                         0x00000000, /* EMC_ACT2PDEN */
2090                         0x00000007, /* EMC_AR2PDEN */
2091                         0x0000000f, /* EMC_RW2PDEN */
2092                         0x0000000e, /* EMC_TXSR */
2093                         0x0000000e, /* EMC_TXSRDLL */
2094                         0x00000004, /* EMC_TCKE */
2095                         0x00000002, /* EMC_TFAW */
2096                         0x00000000, /* EMC_TRPAB */
2097                         0x00000004, /* EMC_TCLKSTABLE */
2098                         0x00000005, /* EMC_TCLKSTOP */
2099                         0x0000018e, /* EMC_TREFBW */
2100                         0x00000006, /* EMC_QUSE_EXTRA */
2101                         0x00000004, /* EMC_FBIO_CFG6 */
2102                         0x00000000, /* EMC_ODT_WRITE */
2103                         0x00000000, /* EMC_ODT_READ */
2104                         0x00004288, /* EMC_FBIO_CFG5 */
2105                         0x007800a4, /* EMC_CFG_DIG_DLL */
2106                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2107                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2108                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2109                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2110                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2111                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2112                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2113                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2114                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2115                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2116                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2117                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2118                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2119                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2120                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2121                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2122                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2123                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2124                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2125                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2126                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2127                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2128                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2129                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2130                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2131                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2132                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2133                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2134                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2135                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2136                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2137                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2138                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2139                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2140                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2141                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2142                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2143                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2144                         0x00000802, /* EMC_CTT_TERM_CTRL */
2145                         0x00000000, /* EMC_ZCAL_INTERVAL */
2146                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2147                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2148                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2149                         0x00000000, /* EMC_CTT */
2150                         0x00000000, /* EMC_CTT_DURATION */
2151                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
2152                         0x00010001, /* MC_EMEM_ARB_CFG */
2153                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2154                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2155                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2156                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2157                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2158                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2159                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2160                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2161                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2162                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2163                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2164                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2165                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2166                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2167                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2168                         0x74630303, /* MC_EMEM_ARB_MISC0 */
2169                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2170                         0xe8000000, /* EMC_FBIO_SPARE */
2171                         0xff00ff00, /* EMC_CFG_RSV */
2172                 },
2173                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2174                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2175                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2176                 0x80001221, /* Mode Register 0 */
2177                 0x80100003, /* Mode Register 1 */
2178                 0x80200008, /* Mode Register 2 */
2179                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2180         },
2181         {
2182                 0x32,       /* Rev 3.2 */
2183                 102000,     /* SDRAM frequency */
2184                 {
2185                         0x00000004, /* EMC_RC */
2186                         0x0000001a, /* EMC_RFC */
2187                         0x00000003, /* EMC_RAS */
2188                         0x00000001, /* EMC_RP */
2189                         0x00000002, /* EMC_R2W */
2190                         0x0000000a, /* EMC_W2R */
2191                         0x00000003, /* EMC_R2P */
2192                         0x0000000b, /* EMC_W2P */
2193                         0x00000001, /* EMC_RD_RCD */
2194                         0x00000001, /* EMC_WR_RCD */
2195                         0x00000003, /* EMC_RRD */
2196                         0x00000001, /* EMC_REXT */
2197                         0x00000000, /* EMC_WEXT */
2198                         0x00000005, /* EMC_WDV */
2199                         0x00000005, /* EMC_QUSE */
2200                         0x00000004, /* EMC_QRST */
2201                         0x00000009, /* EMC_QSAFE */
2202                         0x0000000b, /* EMC_RDV */
2203                         0x00000303, /* EMC_REFRESH */
2204                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2205                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
2206                         0x00000002, /* EMC_PDEX2WR */
2207                         0x00000002, /* EMC_PDEX2RD */
2208                         0x00000001, /* EMC_PCHG2PDEN */
2209                         0x00000000, /* EMC_ACT2PDEN */
2210                         0x00000007, /* EMC_AR2PDEN */
2211                         0x0000000f, /* EMC_RW2PDEN */
2212                         0x0000001c, /* EMC_TXSR */
2213                         0x0000001c, /* EMC_TXSRDLL */
2214                         0x00000004, /* EMC_TCKE */
2215                         0x00000004, /* EMC_TFAW */
2216                         0x00000000, /* EMC_TRPAB */
2217                         0x00000004, /* EMC_TCLKSTABLE */
2218                         0x00000005, /* EMC_TCLKSTOP */
2219                         0x0000031c, /* EMC_TREFBW */
2220                         0x00000006, /* EMC_QUSE_EXTRA */
2221                         0x00000004, /* EMC_FBIO_CFG6 */
2222                         0x00000000, /* EMC_ODT_WRITE */
2223                         0x00000000, /* EMC_ODT_READ */
2224                         0x00004288, /* EMC_FBIO_CFG5 */
2225                         0x007800a4, /* EMC_CFG_DIG_DLL */
2226                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2227                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2228                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2229                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2230                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2231                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2232                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2233                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2234                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2235                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2236                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2237                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2238                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2239                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2240                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2241                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2242                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2243                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2244                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2245                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2246                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2247                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2248                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2249                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2250                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2251                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2252                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2253                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2254                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2255                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2256                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2257                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2258                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2259                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2260                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2261                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2262                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2263                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2264                         0x00000802, /* EMC_CTT_TERM_CTRL */
2265                         0x00000000, /* EMC_ZCAL_INTERVAL */
2266                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2267                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2268                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2269                         0x00000000, /* EMC_CTT */
2270                         0x00000000, /* EMC_CTT_DURATION */
2271                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
2272                         0x00000001, /* MC_EMEM_ARB_CFG */
2273                         0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2274                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2275                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2276                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
2277                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2278                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2279                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2280                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2281                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2282                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2283                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2284                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2285                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2286                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2287                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
2288                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
2289                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2290                         0xe8000000, /* EMC_FBIO_SPARE */
2291                         0xff00ff00, /* EMC_CFG_RSV */
2292                 },
2293                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2294                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2295                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2296                 0x80001221, /* Mode Register 0 */
2297                 0x80100003, /* Mode Register 1 */
2298                 0x80200008, /* Mode Register 2 */
2299                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2300         },
2301         {
2302                 0x32,       /* Rev 3.2 */
2303                 204000,     /* SDRAM frequency */
2304                 {
2305                         0x00000009, /* EMC_RC */
2306                         0x00000035, /* EMC_RFC */
2307                         0x00000007, /* EMC_RAS */
2308                         0x00000002, /* EMC_RP */
2309                         0x00000002, /* EMC_R2W */
2310                         0x0000000a, /* EMC_W2R */
2311                         0x00000003, /* EMC_R2P */
2312                         0x0000000b, /* EMC_W2P */
2313                         0x00000002, /* EMC_RD_RCD */
2314                         0x00000002, /* EMC_WR_RCD */
2315                         0x00000003, /* EMC_RRD */
2316                         0x00000001, /* EMC_REXT */
2317                         0x00000000, /* EMC_WEXT */
2318                         0x00000005, /* EMC_WDV */
2319                         0x00000005, /* EMC_QUSE */
2320                         0x00000004, /* EMC_QRST */
2321                         0x00000009, /* EMC_QSAFE */
2322                         0x0000000b, /* EMC_RDV */
2323                         0x00000607, /* EMC_REFRESH */
2324                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2325                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
2326                         0x00000002, /* EMC_PDEX2WR */
2327                         0x00000002, /* EMC_PDEX2RD */
2328                         0x00000001, /* EMC_PCHG2PDEN */
2329                         0x00000000, /* EMC_ACT2PDEN */
2330                         0x00000007, /* EMC_AR2PDEN */
2331                         0x0000000f, /* EMC_RW2PDEN */
2332                         0x00000038, /* EMC_TXSR */
2333                         0x00000038, /* EMC_TXSRDLL */
2334                         0x00000004, /* EMC_TCKE */
2335                         0x00000007, /* EMC_TFAW */
2336                         0x00000000, /* EMC_TRPAB */
2337                         0x00000004, /* EMC_TCLKSTABLE */
2338                         0x00000005, /* EMC_TCLKSTOP */
2339                         0x00000638, /* EMC_TREFBW */
2340                         0x00000006, /* EMC_QUSE_EXTRA */
2341                         0x00000004, /* EMC_FBIO_CFG6 */
2342                         0x00000000, /* EMC_ODT_WRITE */
2343                         0x00000000, /* EMC_ODT_READ */
2344                         0x00004288, /* EMC_FBIO_CFG5 */
2345                         0x004400a4, /* EMC_CFG_DIG_DLL */
2346                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2347                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
2348                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
2349                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
2350                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
2351                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
2352                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
2353                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
2354                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
2355                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2356                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2357                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2358                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2359                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2360                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2361                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2362                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2363                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2364                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2365                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2366                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2367                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2368                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2369                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2370                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2371                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
2372                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
2373                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
2374                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
2375                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2376                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2377                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2378                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2379                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2380                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2381                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2382                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2383                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2384                         0x00000802, /* EMC_CTT_TERM_CTRL */
2385                         0x00020000, /* EMC_ZCAL_INTERVAL */
2386                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2387                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2388                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2389                         0x00000000, /* EMC_CTT */
2390                         0x00000000, /* EMC_CTT_DURATION */
2391                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
2392                         0x00000003, /* MC_EMEM_ARB_CFG */
2393                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2394                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2395                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2396                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
2397                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
2398                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
2399                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2400                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2401                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2402                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2403                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2404                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2405                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2406                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2407                         0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
2408                         0x73840a06, /* MC_EMEM_ARB_MISC0 */
2409                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2410                         0xe8000000, /* EMC_FBIO_SPARE */
2411                         0xff00ff00, /* EMC_CFG_RSV */
2412                 },
2413                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2414                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2415                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2416                 0x80001221, /* Mode Register 0 */
2417                 0x80100003, /* Mode Register 1 */
2418                 0x80200008, /* Mode Register 2 */
2419                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2420         },
2421         {
2422                 0x32,       /* Rev 3.2 */
2423                 375000,     /* SDRAM frequency */
2424                 {
2425                         0x00000011, /* EMC_RC */
2426                         0x0000006f, /* EMC_RFC */
2427                         0x0000000c, /* EMC_RAS */
2428                         0x00000004, /* EMC_RP */
2429                         0x00000003, /* EMC_R2W */
2430                         0x00000008, /* EMC_W2R */
2431                         0x00000002, /* EMC_R2P */
2432                         0x0000000a, /* EMC_W2P */
2433                         0x00000004, /* EMC_RD_RCD */
2434                         0x00000004, /* EMC_WR_RCD */
2435                         0x00000002, /* EMC_RRD */
2436                         0x00000001, /* EMC_REXT */
2437                         0x00000000, /* EMC_WEXT */
2438                         0x00000004, /* EMC_WDV */
2439                         0x00000006, /* EMC_QUSE */
2440                         0x00000004, /* EMC_QRST */
2441                         0x0000000a, /* EMC_QSAFE */
2442                         0x0000000d, /* EMC_RDV */
2443                         0x00000b2d, /* EMC_REFRESH */
2444                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2445                         0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
2446                         0x00000001, /* EMC_PDEX2WR */
2447                         0x00000008, /* EMC_PDEX2RD */
2448                         0x00000001, /* EMC_PCHG2PDEN */
2449                         0x00000000, /* EMC_ACT2PDEN */
2450                         0x00000007, /* EMC_AR2PDEN */
2451                         0x0000000f, /* EMC_RW2PDEN */
2452                         0x00000075, /* EMC_TXSR */
2453                         0x00000200, /* EMC_TXSRDLL */
2454                         0x00000004, /* EMC_TCKE */
2455                         0x0000000c, /* EMC_TFAW */
2456                         0x00000000, /* EMC_TRPAB */
2457                         0x00000004, /* EMC_TCLKSTABLE */
2458                         0x00000005, /* EMC_TCLKSTOP */
2459                         0x00000b6d, /* EMC_TREFBW */
2460                         0x00000000, /* EMC_QUSE_EXTRA */
2461                         0x00000006, /* EMC_FBIO_CFG6 */
2462                         0x00000000, /* EMC_ODT_WRITE */
2463                         0x00000000, /* EMC_ODT_READ */
2464                         0x00007088, /* EMC_FBIO_CFG5 */
2465                         0x00200084, /* EMC_CFG_DIG_DLL */
2466                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2467                         0x0003c000, /* EMC_DLL_XFORM_DQS0 */
2468                         0x0003c000, /* EMC_DLL_XFORM_DQS1 */
2469                         0x0003c000, /* EMC_DLL_XFORM_DQS2 */
2470                         0x0003c000, /* EMC_DLL_XFORM_DQS3 */
2471                         0x0003c000, /* EMC_DLL_XFORM_DQS4 */
2472                         0x0003c000, /* EMC_DLL_XFORM_DQS5 */
2473                         0x0003c000, /* EMC_DLL_XFORM_DQS6 */
2474                         0x0003c000, /* EMC_DLL_XFORM_DQS7 */
2475                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2476                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2477                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2478                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2479                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2480                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2481                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2482                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2483                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2484                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2485                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2486                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2487                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2488                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2489                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2490                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2491                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
2492                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
2493                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
2494                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
2495                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2496                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
2497                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2498                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2499                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
2500                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2501                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2502                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2503                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
2504                         0x00000802, /* EMC_CTT_TERM_CTRL */
2505                         0x00020000, /* EMC_ZCAL_INTERVAL */
2506                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2507                         0x0150000c, /* EMC_MRS_WAIT_CNT */
2508                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2509                         0x00000000, /* EMC_CTT */
2510                         0x00000000, /* EMC_CTT_DURATION */
2511                         0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
2512                         0x00000005, /* MC_EMEM_ARB_CFG */
2513                         0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2514                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2515                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
2516                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
2517                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
2518                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
2519                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2520                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2521                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2522                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2523                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2524                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
2525                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2526                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
2527                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
2528                         0x75c6110a, /* MC_EMEM_ARB_MISC0 */
2529                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2530                         0x58000000, /* EMC_FBIO_SPARE */
2531                         0xff00ff88, /* EMC_CFG_RSV */
2532                 },
2533                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2534                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2535                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
2536                 0x80000521, /* Mode Register 0 */
2537                 0x80100002, /* Mode Register 1 */
2538                 0x80200000, /* Mode Register 2 */
2539                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2540         },
2541         {
2542                 0x32,       /* Rev 3.2 */
2543                 750000,     /* SDRAM frequency */
2544                 {
2545                         0x00000023, /* EMC_RC */
2546                         0x000000df, /* EMC_RFC */
2547                         0x00000019, /* EMC_RAS */
2548                         0x00000009, /* EMC_RP */
2549                         0x00000005, /* EMC_R2W */
2550                         0x0000000d, /* EMC_W2R */
2551                         0x00000004, /* EMC_R2P */
2552                         0x00000013, /* EMC_W2P */
2553                         0x00000009, /* EMC_RD_RCD */
2554                         0x00000009, /* EMC_WR_RCD */
2555                         0x00000003, /* EMC_RRD */
2556                         0x00000001, /* EMC_REXT */
2557                         0x00000000, /* EMC_WEXT */
2558                         0x00000007, /* EMC_WDV */
2559                         0x0000000b, /* EMC_QUSE */
2560                         0x00000009, /* EMC_QRST */
2561                         0x0000000c, /* EMC_QSAFE */
2562                         0x00000011, /* EMC_RDV */
2563                         0x0000169a, /* EMC_REFRESH */
2564                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2565                         0x000005a6, /* EMC_PRE_REFRESH_REQ_CNT */
2566                         0x00000003, /* EMC_PDEX2WR */
2567                         0x00000010, /* EMC_PDEX2RD */
2568                         0x00000001, /* EMC_PCHG2PDEN */
2569                         0x00000000, /* EMC_ACT2PDEN */
2570                         0x0000000e, /* EMC_AR2PDEN */
2571                         0x00000018, /* EMC_RW2PDEN */
2572                         0x000000e9, /* EMC_TXSR */
2573                         0x00000200, /* EMC_TXSRDLL */
2574                         0x00000005, /* EMC_TCKE */
2575                         0x00000017, /* EMC_TFAW */
2576                         0x00000000, /* EMC_TRPAB */
2577                         0x00000007, /* EMC_TCLKSTABLE */
2578                         0x00000008, /* EMC_TCLKSTOP */
2579                         0x000016da, /* EMC_TREFBW */
2580                         0x0000000c, /* EMC_QUSE_EXTRA */
2581                         0x00000004, /* EMC_FBIO_CFG6 */
2582                         0x00000000, /* EMC_ODT_WRITE */
2583                         0x00000000, /* EMC_ODT_READ */
2584                         0x00005088, /* EMC_FBIO_CFG5 */
2585                         0xf0080191, /* EMC_CFG_DIG_DLL */
2586                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2587                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
2588                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
2589                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
2590                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
2591                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
2592                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
2593                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
2594                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
2595                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2596                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2597                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2598                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2599                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2600                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2601                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2602                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2603                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2604                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2605                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2606                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2607                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2608                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2609                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2610                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2611                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
2612                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
2613                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
2614                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
2615                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2616                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
2617                         0x22220000, /* EMC_XM2DQPADCTRL2 */
2618                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2619                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
2620                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
2621                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
2622                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
2623                         0x07000021, /* EMC_XM2DQSPADCTRL3 */
2624                         0x00000802, /* EMC_CTT_TERM_CTRL */
2625                         0x00020000, /* EMC_ZCAL_INTERVAL */
2626                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
2627                         0x00df000c, /* EMC_MRS_WAIT_CNT */
2628                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2629                         0x00000000, /* EMC_CTT */
2630                         0x00000000, /* EMC_CTT_DURATION */
2631                         0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
2632                         0x0000000b, /* MC_EMEM_ARB_CFG */
2633                         0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2634                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
2635                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
2636                         0x00000012, /* MC_EMEM_ARB_TIMING_RC */
2637                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
2638                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
2639                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
2640                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2641                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2642                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2643                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
2644                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
2645                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
2646                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
2647                         0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
2648                         0x73cc2213, /* MC_EMEM_ARB_MISC0 */
2649                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2650                         0xf8000000, /* EMC_FBIO_SPARE */
2651                         0xff00ff49, /* EMC_CFG_RSV */
2652                 },
2653                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2654                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2655                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2656                 0x80000d71, /* Mode Register 0 */
2657                 0x80100002, /* Mode Register 1 */
2658                 0x80200018, /* Mode Register 2 */
2659                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
2660         },
2661 };
2662
2663 static const struct tegra_emc_table cardhu_emc_tables_k4b4g0846b_hyk0[] = {
2664         {
2665                 0x32,       /* Rev 3.2 */
2666                 25500,      /* SDRAM frequency */
2667                 {
2668                         0x00000001, /* EMC_RC */
2669                         0x00000006, /* EMC_RFC */
2670                         0x00000000, /* EMC_RAS */
2671                         0x00000000, /* EMC_RP */
2672                         0x00000002, /* EMC_R2W */
2673                         0x0000000a, /* EMC_W2R */
2674                         0x00000005, /* EMC_R2P */
2675                         0x0000000b, /* EMC_W2P */
2676                         0x00000000, /* EMC_RD_RCD */
2677                         0x00000000, /* EMC_WR_RCD */
2678                         0x00000003, /* EMC_RRD */
2679                         0x00000001, /* EMC_REXT */
2680                         0x00000000, /* EMC_WEXT */
2681                         0x00000005, /* EMC_WDV */
2682                         0x00000005, /* EMC_QUSE */
2683                         0x00000004, /* EMC_QRST */
2684                         0x00000009, /* EMC_QSAFE */
2685                         0x0000000b, /* EMC_RDV */
2686                         0x000000c0, /* EMC_REFRESH */
2687                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2688                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
2689                         0x00000002, /* EMC_PDEX2WR */
2690                         0x00000002, /* EMC_PDEX2RD */
2691                         0x00000001, /* EMC_PCHG2PDEN */
2692                         0x00000000, /* EMC_ACT2PDEN */
2693                         0x00000007, /* EMC_AR2PDEN */
2694                         0x0000000f, /* EMC_RW2PDEN */
2695                         0x00000007, /* EMC_TXSR */
2696                         0x00000007, /* EMC_TXSRDLL */
2697                         0x00000004, /* EMC_TCKE */
2698                         0x00000001, /* EMC_TFAW */
2699                         0x00000000, /* EMC_TRPAB */
2700                         0x00000004, /* EMC_TCLKSTABLE */
2701                         0x00000005, /* EMC_TCLKSTOP */
2702                         0x000000c7, /* EMC_TREFBW */
2703                         0x00000006, /* EMC_QUSE_EXTRA */
2704                         0x00000004, /* EMC_FBIO_CFG6 */
2705                         0x00000000, /* EMC_ODT_WRITE */
2706                         0x00000000, /* EMC_ODT_READ */
2707                         0x00004288, /* EMC_FBIO_CFG5 */
2708                         0x007800a4, /* EMC_CFG_DIG_DLL */
2709                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2710                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2711                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2712                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2713                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2714                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2715                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2716                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2717                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2718                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2719                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2720                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2721                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2722                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2723                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2724                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2725                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2726                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2727                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2728                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2729                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2730                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2731                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2732                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2733                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2734                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2735                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2736                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2737                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2738                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2739                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2740                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2741                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2742                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2743                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2744                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2745                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2746                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2747                         0x00000802, /* EMC_CTT_TERM_CTRL */
2748                         0x00000000, /* EMC_ZCAL_INTERVAL */
2749                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2750                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2751                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2752                         0x00000000, /* EMC_CTT */
2753                         0x00000000, /* EMC_CTT_DURATION */
2754                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
2755                         0x00020001, /* MC_EMEM_ARB_CFG */
2756                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2757                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2758                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2759                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2760                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2761                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2762                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2763                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2764                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2765                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2766                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2767                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2768                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2769                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2770                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2771                         0x75830303, /* MC_EMEM_ARB_MISC0 */
2772                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2773                         0xe8000000, /* EMC_FBIO_SPARE */
2774                         0xff00ff00, /* EMC_CFG_RSV */
2775                 },
2776                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2777                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2778                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2779                 0x80001221, /* Mode Register 0 */
2780                 0x80100003, /* Mode Register 1 */
2781                 0x80200008, /* Mode Register 2 */
2782                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2783         },
2784         {
2785                 0x32,       /* Rev 3.2 */
2786                 51000,      /* SDRAM frequency */
2787                 {
2788                         0x00000002, /* EMC_RC */
2789                         0x0000000d, /* EMC_RFC */
2790                         0x00000001, /* EMC_RAS */
2791                         0x00000000, /* EMC_RP */
2792                         0x00000002, /* EMC_R2W */
2793                         0x0000000a, /* EMC_W2R */
2794                         0x00000005, /* EMC_R2P */
2795                         0x0000000b, /* EMC_W2P */
2796                         0x00000000, /* EMC_RD_RCD */
2797                         0x00000000, /* EMC_WR_RCD */
2798                         0x00000003, /* EMC_RRD */
2799                         0x00000001, /* EMC_REXT */
2800                         0x00000000, /* EMC_WEXT */
2801                         0x00000005, /* EMC_WDV */
2802                         0x00000005, /* EMC_QUSE */
2803                         0x00000004, /* EMC_QRST */
2804                         0x00000009, /* EMC_QSAFE */
2805                         0x0000000b, /* EMC_RDV */
2806                         0x00000181, /* EMC_REFRESH */
2807                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2808                         0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
2809                         0x00000002, /* EMC_PDEX2WR */
2810                         0x00000002, /* EMC_PDEX2RD */
2811                         0x00000001, /* EMC_PCHG2PDEN */
2812                         0x00000000, /* EMC_ACT2PDEN */
2813                         0x00000007, /* EMC_AR2PDEN */
2814                         0x0000000f, /* EMC_RW2PDEN */
2815                         0x0000000e, /* EMC_TXSR */
2816                         0x0000000e, /* EMC_TXSRDLL */
2817                         0x00000004, /* EMC_TCKE */
2818                         0x00000002, /* EMC_TFAW */
2819                         0x00000000, /* EMC_TRPAB */
2820                         0x00000004, /* EMC_TCLKSTABLE */
2821                         0x00000005, /* EMC_TCLKSTOP */
2822                         0x0000018e, /* EMC_TREFBW */
2823                         0x00000006, /* EMC_QUSE_EXTRA */
2824                         0x00000004, /* EMC_FBIO_CFG6 */
2825                         0x00000000, /* EMC_ODT_WRITE */
2826                         0x00000000, /* EMC_ODT_READ */
2827                         0x00004288, /* EMC_FBIO_CFG5 */
2828                         0x007800a4, /* EMC_CFG_DIG_DLL */
2829                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2830                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2831                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2832                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2833                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2834                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2835                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2836                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2837                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2838                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2839                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2840                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2841                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2842                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2843                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2844                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2845                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2846                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2847                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2848                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2849                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2850                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2851                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2852                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2853                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2854                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2855                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2856                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2857                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2858                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2859                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2860                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2861                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2862                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2863                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2864                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2865                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2866                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2867                         0x00000802, /* EMC_CTT_TERM_CTRL */
2868                         0x00000000, /* EMC_ZCAL_INTERVAL */
2869                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2870                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2871                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2872                         0x00000000, /* EMC_CTT */
2873                         0x00000000, /* EMC_CTT_DURATION */
2874                         0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
2875                         0x00010001, /* MC_EMEM_ARB_CFG */
2876                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2877                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2878                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2879                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
2880                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
2881                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
2882                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
2883                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
2884                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
2885                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
2886                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
2887                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
2888                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
2889                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
2890                         0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
2891                         0x74630303, /* MC_EMEM_ARB_MISC0 */
2892                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
2893                         0xe8000000, /* EMC_FBIO_SPARE */
2894                         0xff00ff00, /* EMC_CFG_RSV */
2895                 },
2896                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
2897                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
2898                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
2899                 0x80001221, /* Mode Register 0 */
2900                 0x80100003, /* Mode Register 1 */
2901                 0x80200008, /* Mode Register 2 */
2902                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
2903         },
2904         {
2905                 0x32,       /* Rev 3.2 */
2906                 102000,     /* SDRAM frequency */
2907                 {
2908                         0x00000004, /* EMC_RC */
2909                         0x0000001a, /* EMC_RFC */
2910                         0x00000003, /* EMC_RAS */
2911                         0x00000001, /* EMC_RP */
2912                         0x00000002, /* EMC_R2W */
2913                         0x0000000a, /* EMC_W2R */
2914                         0x00000005, /* EMC_R2P */
2915                         0x0000000b, /* EMC_W2P */
2916                         0x00000001, /* EMC_RD_RCD */
2917                         0x00000001, /* EMC_WR_RCD */
2918                         0x00000003, /* EMC_RRD */
2919                         0x00000001, /* EMC_REXT */
2920                         0x00000000, /* EMC_WEXT */
2921                         0x00000005, /* EMC_WDV */
2922                         0x00000005, /* EMC_QUSE */
2923                         0x00000004, /* EMC_QRST */
2924                         0x00000009, /* EMC_QSAFE */
2925                         0x0000000b, /* EMC_RDV */
2926                         0x00000303, /* EMC_REFRESH */
2927                         0x00000000, /* EMC_BURST_REFRESH_NUM */
2928                         0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
2929                         0x00000002, /* EMC_PDEX2WR */
2930                         0x00000002, /* EMC_PDEX2RD */
2931                         0x00000001, /* EMC_PCHG2PDEN */
2932                         0x00000000, /* EMC_ACT2PDEN */
2933                         0x00000007, /* EMC_AR2PDEN */
2934                         0x0000000f, /* EMC_RW2PDEN */
2935                         0x0000001c, /* EMC_TXSR */
2936                         0x0000001c, /* EMC_TXSRDLL */
2937                         0x00000004, /* EMC_TCKE */
2938                         0x00000004, /* EMC_TFAW */
2939                         0x00000000, /* EMC_TRPAB */
2940                         0x00000004, /* EMC_TCLKSTABLE */
2941                         0x00000005, /* EMC_TCLKSTOP */
2942                         0x0000031c, /* EMC_TREFBW */
2943                         0x00000006, /* EMC_QUSE_EXTRA */
2944                         0x00000004, /* EMC_FBIO_CFG6 */
2945                         0x00000000, /* EMC_ODT_WRITE */
2946                         0x00000000, /* EMC_ODT_READ */
2947                         0x00004288, /* EMC_FBIO_CFG5 */
2948                         0x007800a4, /* EMC_CFG_DIG_DLL */
2949                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
2950                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
2951                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
2952                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
2953                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
2954                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
2955                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
2956                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
2957                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
2958                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
2959                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
2960                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
2961                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
2962                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
2963                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
2964                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
2965                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
2966                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
2967                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
2968                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
2969                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
2970                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
2971                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
2972                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
2973                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
2974                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
2975                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
2976                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
2977                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
2978                         0x000002a0, /* EMC_XM2CMDPADCTRL */
2979                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
2980                         0x00000000, /* EMC_XM2DQPADCTRL2 */
2981                         0x77fff884, /* EMC_XM2CLKPADCTRL */
2982                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
2983                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
2984                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
2985                         0x08000168, /* EMC_XM2QUSEPADCTRL */
2986                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
2987                         0x00000802, /* EMC_CTT_TERM_CTRL */
2988                         0x00000000, /* EMC_ZCAL_INTERVAL */
2989                         0x00000040, /* EMC_ZCAL_WAIT_CNT */
2990                         0x000c000c, /* EMC_MRS_WAIT_CNT */
2991                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
2992                         0x00000000, /* EMC_CTT */
2993                         0x00000000, /* EMC_CTT_DURATION */
2994                         0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
2995                         0x00000001, /* MC_EMEM_ARB_CFG */
2996                         0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */
2997                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
2998                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
2999                         0x00000003, /* MC_EMEM_ARB_TIMING_RC */
3000                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3001                         0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
3002                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3003                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3004                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3005                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3006                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3007                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3008                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3009                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3010                         0x000a0403, /* MC_EMEM_ARB_DA_COVERS */
3011                         0x73c30504, /* MC_EMEM_ARB_MISC0 */
3012                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3013                         0xe8000000, /* EMC_FBIO_SPARE */
3014                         0xff00ff00, /* EMC_CFG_RSV */
3015                 },
3016                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3017                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3018                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3019                 0x80001221, /* Mode Register 0 */
3020                 0x80100003, /* Mode Register 1 */
3021                 0x80200008, /* Mode Register 2 */
3022                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3023         },
3024         {
3025                 0x32,       /* Rev 3.2 */
3026                 204000,     /* SDRAM frequency */
3027                 {
3028                         0x00000009, /* EMC_RC */
3029                         0x00000035, /* EMC_RFC */
3030                         0x00000007, /* EMC_RAS */
3031                         0x00000002, /* EMC_RP */
3032                         0x00000002, /* EMC_R2W */
3033                         0x0000000a, /* EMC_W2R */
3034                         0x00000005, /* EMC_R2P */
3035                         0x0000000b, /* EMC_W2P */
3036                         0x00000002, /* EMC_RD_RCD */
3037                         0x00000002, /* EMC_WR_RCD */
3038                         0x00000003, /* EMC_RRD */
3039                         0x00000001, /* EMC_REXT */
3040                         0x00000000, /* EMC_WEXT */
3041                         0x00000005, /* EMC_WDV */
3042                         0x00000005, /* EMC_QUSE */
3043                         0x00000004, /* EMC_QRST */
3044                         0x00000009, /* EMC_QSAFE */
3045                         0x0000000b, /* EMC_RDV */
3046                         0x00000607, /* EMC_REFRESH */
3047                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3048                         0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
3049                         0x00000002, /* EMC_PDEX2WR */
3050                         0x00000002, /* EMC_PDEX2RD */
3051                         0x00000001, /* EMC_PCHG2PDEN */
3052                         0x00000000, /* EMC_ACT2PDEN */
3053                         0x00000007, /* EMC_AR2PDEN */
3054                         0x0000000f, /* EMC_RW2PDEN */
3055                         0x00000038, /* EMC_TXSR */
3056                         0x00000038, /* EMC_TXSRDLL */
3057                         0x00000004, /* EMC_TCKE */
3058                         0x00000007, /* EMC_TFAW */
3059                         0x00000000, /* EMC_TRPAB */
3060                         0x00000004, /* EMC_TCLKSTABLE */
3061                         0x00000005, /* EMC_TCLKSTOP */
3062                         0x00000638, /* EMC_TREFBW */
3063                         0x00000006, /* EMC_QUSE_EXTRA */
3064                         0x00000004, /* EMC_FBIO_CFG6 */
3065                         0x00000000, /* EMC_ODT_WRITE */
3066                         0x00000000, /* EMC_ODT_READ */
3067                         0x00004288, /* EMC_FBIO_CFG5 */
3068                         0x004400a4, /* EMC_CFG_DIG_DLL */
3069                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3070                         0x00080000, /* EMC_DLL_XFORM_DQS0 */
3071                         0x00080000, /* EMC_DLL_XFORM_DQS1 */
3072                         0x00080000, /* EMC_DLL_XFORM_DQS2 */
3073                         0x00080000, /* EMC_DLL_XFORM_DQS3 */
3074                         0x00080000, /* EMC_DLL_XFORM_DQS4 */
3075                         0x00080000, /* EMC_DLL_XFORM_DQS5 */
3076                         0x00080000, /* EMC_DLL_XFORM_DQS6 */
3077                         0x00080000, /* EMC_DLL_XFORM_DQS7 */
3078                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3079                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3080                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3081                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3082                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3083                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3084                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3085                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3086                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3087                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3088                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3089                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3090                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3091                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3092                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3093                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3094                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
3095                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
3096                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
3097                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
3098                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3099                         0x0800211c, /* EMC_XM2DQSPADCTRL2 */
3100                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3101                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3102                         0x01f1f108, /* EMC_XM2COMPPADCTRL */
3103                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3104                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3105                         0x08000168, /* EMC_XM2QUSEPADCTRL */
3106                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3107                         0x00000802, /* EMC_CTT_TERM_CTRL */
3108                         0x00020000, /* EMC_ZCAL_INTERVAL */
3109                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3110                         0x000c000c, /* EMC_MRS_WAIT_CNT */
3111                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3112                         0x00000000, /* EMC_CTT */
3113                         0x00000000, /* EMC_CTT_DURATION */
3114                         0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
3115                         0x00000003, /* MC_EMEM_ARB_CFG */
3116                         0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3117                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3118                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3119                         0x00000005, /* MC_EMEM_ARB_TIMING_RC */
3120                         0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
3121                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3122                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3123                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3124                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3125                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3126                         0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
3127                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3128                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3129                         0x06020102, /* MC_EMEM_ARB_DA_TURNS */
3130                         0x000a0405, /* MC_EMEM_ARB_DA_COVERS */
3131                         0x73840a06, /* MC_EMEM_ARB_MISC0 */
3132                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3133                         0xe8000000, /* EMC_FBIO_SPARE */
3134                         0xff00ff00, /* EMC_CFG_RSV */
3135                 },
3136                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3137                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3138                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3139                 0x80001221, /* Mode Register 0 */
3140                 0x80100003, /* Mode Register 1 */
3141                 0x80200008, /* Mode Register 2 */
3142                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3143         },
3144         {
3145                 0x32,       /* Rev 3.2 */
3146                 375000,     /* SDRAM frequency */
3147                 {
3148                         0x00000011, /* EMC_RC */
3149                         0x00000060, /* EMC_RFC */
3150                         0x0000000c, /* EMC_RAS */
3151                         0x00000004, /* EMC_RP */
3152                         0x00000003, /* EMC_R2W */
3153                         0x00000008, /* EMC_W2R */
3154                         0x00000002, /* EMC_R2P */
3155                         0x0000000a, /* EMC_W2P */
3156                         0x00000004, /* EMC_RD_RCD */
3157                         0x00000004, /* EMC_WR_RCD */
3158                         0x00000002, /* EMC_RRD */
3159                         0x00000001, /* EMC_REXT */
3160                         0x00000000, /* EMC_WEXT */
3161                         0x00000004, /* EMC_WDV */
3162                         0x00000006, /* EMC_QUSE */
3163                         0x00000004, /* EMC_QRST */
3164                         0x0000000a, /* EMC_QSAFE */
3165                         0x0000000d, /* EMC_RDV */
3166                         0x00000b2d, /* EMC_REFRESH */
3167                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3168                         0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */
3169                         0x00000001, /* EMC_PDEX2WR */
3170                         0x00000008, /* EMC_PDEX2RD */
3171                         0x00000001, /* EMC_PCHG2PDEN */
3172                         0x00000000, /* EMC_ACT2PDEN */
3173                         0x00000007, /* EMC_AR2PDEN */
3174                         0x0000000f, /* EMC_RW2PDEN */
3175                         0x00000066, /* EMC_TXSR */
3176                         0x00000200, /* EMC_TXSRDLL */
3177                         0x00000004, /* EMC_TCKE */
3178                         0x0000000c, /* EMC_TFAW */
3179                         0x00000000, /* EMC_TRPAB */
3180                         0x00000004, /* EMC_TCLKSTABLE */
3181                         0x00000005, /* EMC_TCLKSTOP */
3182                         0x00000b6d, /* EMC_TREFBW */
3183                         0x00000000, /* EMC_QUSE_EXTRA */
3184                         0x00000006, /* EMC_FBIO_CFG6 */
3185                         0x00000000, /* EMC_ODT_WRITE */
3186                         0x00000000, /* EMC_ODT_READ */
3187                         0x00007088, /* EMC_FBIO_CFG5 */
3188                         0x00200084, /* EMC_CFG_DIG_DLL */
3189                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3190                         0x00014000, /* EMC_DLL_XFORM_DQS0 */
3191                         0x00014000, /* EMC_DLL_XFORM_DQS1 */
3192                         0x00014000, /* EMC_DLL_XFORM_DQS2 */
3193                         0x00014000, /* EMC_DLL_XFORM_DQS3 */
3194                         0x00014000, /* EMC_DLL_XFORM_DQS4 */
3195                         0x00014000, /* EMC_DLL_XFORM_DQS5 */
3196                         0x00014000, /* EMC_DLL_XFORM_DQS6 */
3197                         0x00014000, /* EMC_DLL_XFORM_DQS7 */
3198                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3199                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3200                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3201                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3202                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3203                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3204                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3205                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3206                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3207                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3208                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3209                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3210                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3211                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3212                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3213                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3214                         0x00020000, /* EMC_DLL_XFORM_DQ0 */
3215                         0x00020000, /* EMC_DLL_XFORM_DQ1 */
3216                         0x00020000, /* EMC_DLL_XFORM_DQ2 */
3217                         0x00020000, /* EMC_DLL_XFORM_DQ3 */
3218                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3219                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
3220                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3221                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3222                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
3223                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3224                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3225                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3226                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
3227                         0x00000802, /* EMC_CTT_TERM_CTRL */
3228                         0x00020000, /* EMC_ZCAL_INTERVAL */
3229                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3230                         0x015f000c, /* EMC_MRS_WAIT_CNT */
3231                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3232                         0x00000000, /* EMC_CTT */
3233                         0x00000000, /* EMC_CTT_DURATION */
3234                         0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */
3235                         0x00000005, /* MC_EMEM_ARB_CFG */
3236                         0x80000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3237                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3238                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3239                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3240                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3241                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3242                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3243                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3244                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3245                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3246                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3247                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3248                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3249                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
3250                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
3251                         0x7086110a, /* MC_EMEM_ARB_MISC0 */
3252                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3253                         0x58000000, /* EMC_FBIO_SPARE */
3254                         0xff00ff88, /* EMC_CFG_RSV */
3255                 },
3256                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3257                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3258                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
3259                 0x80000521, /* Mode Register 0 */
3260                 0x80100002, /* Mode Register 1 */
3261                 0x80200000, /* Mode Register 2 */
3262                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3263         },
3264         {
3265                 0x32,       /* Rev 3.2 */
3266                 400000,     /* SDRAM frequency */
3267                 {
3268                         0x00000012, /* EMC_RC */
3269                         0x00000066, /* EMC_RFC */
3270                         0x0000000c, /* EMC_RAS */
3271                         0x00000004, /* EMC_RP */
3272                         0x00000003, /* EMC_R2W */
3273                         0x00000008, /* EMC_W2R */
3274                         0x00000002, /* EMC_R2P */
3275                         0x0000000a, /* EMC_W2P */
3276                         0x00000004, /* EMC_RD_RCD */
3277                         0x00000004, /* EMC_WR_RCD */
3278                         0x00000002, /* EMC_RRD */
3279                         0x00000001, /* EMC_REXT */
3280                         0x00000000, /* EMC_WEXT */
3281                         0x00000004, /* EMC_WDV */
3282                         0x00000006, /* EMC_QUSE */
3283                         0x00000004, /* EMC_QRST */
3284                         0x0000000a, /* EMC_QSAFE */
3285                         0x0000000c, /* EMC_RDV */
3286                         0x00000bf0, /* EMC_REFRESH */
3287                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3288                         0x000002fc, /* EMC_PRE_REFRESH_REQ_CNT */
3289                         0x00000001, /* EMC_PDEX2WR */
3290                         0x00000008, /* EMC_PDEX2RD */
3291                         0x00000001, /* EMC_PCHG2PDEN */
3292                         0x00000000, /* EMC_ACT2PDEN */
3293                         0x00000008, /* EMC_AR2PDEN */
3294                         0x0000000f, /* EMC_RW2PDEN */
3295                         0x0000006c, /* EMC_TXSR */
3296                         0x00000200, /* EMC_TXSRDLL */
3297                         0x00000004, /* EMC_TCKE */
3298                         0x0000000c, /* EMC_TFAW */
3299                         0x00000000, /* EMC_TRPAB */
3300                         0x00000004, /* EMC_TCLKSTABLE */
3301                         0x00000005, /* EMC_TCLKSTOP */
3302                         0x00000c30, /* EMC_TREFBW */
3303                         0x00000000, /* EMC_QUSE_EXTRA */
3304                         0x00000006, /* EMC_FBIO_CFG6 */
3305                         0x00000000, /* EMC_ODT_WRITE */
3306                         0x00000000, /* EMC_ODT_READ */
3307                         0x00007088, /* EMC_FBIO_CFG5 */
3308                         0x001d0084, /* EMC_CFG_DIG_DLL */
3309                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3310                         0x00034000, /* EMC_DLL_XFORM_DQS0 */
3311                         0x00034000, /* EMC_DLL_XFORM_DQS1 */
3312                         0x00034000, /* EMC_DLL_XFORM_DQS2 */
3313                         0x00034000, /* EMC_DLL_XFORM_DQS3 */
3314                         0x00034000, /* EMC_DLL_XFORM_DQS4 */
3315                         0x00034000, /* EMC_DLL_XFORM_DQS5 */
3316                         0x00034000, /* EMC_DLL_XFORM_DQS6 */
3317                         0x00034000, /* EMC_DLL_XFORM_DQS7 */
3318                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3319                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3320                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3321                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3322                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3323                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3324                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3325                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3326                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3327                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3328                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3329                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3330                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3331                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3332                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3333                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3334                         0x00040000, /* EMC_DLL_XFORM_DQ0 */
3335                         0x00040000, /* EMC_DLL_XFORM_DQ1 */
3336                         0x00040000, /* EMC_DLL_XFORM_DQ2 */
3337                         0x00040000, /* EMC_DLL_XFORM_DQ3 */
3338                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3339                         0x0800013d, /* EMC_XM2DQSPADCTRL2 */
3340                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3341                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3342                         0x01f1f508, /* EMC_XM2COMPPADCTRL */
3343                         0x05057404, /* EMC_XM2VTTGENPADCTRL */
3344                         0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
3345                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3346                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
3347                         0x00000802, /* EMC_CTT_TERM_CTRL */
3348                         0x00020000, /* EMC_ZCAL_INTERVAL */
3349                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3350                         0x0158000c, /* EMC_MRS_WAIT_CNT */
3351                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3352                         0x00000000, /* EMC_CTT */
3353                         0x00000000, /* EMC_CTT_DURATION */
3354                         0x800018c8, /* EMC_DYN_SELF_REF_CONTROL */
3355                         0x00000006, /* MC_EMEM_ARB_CFG */
3356                         0x80000048, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3357                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3358                         0x00000002, /* MC_EMEM_ARB_TIMING_RP */
3359                         0x00000009, /* MC_EMEM_ARB_TIMING_RC */
3360                         0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
3361                         0x00000005, /* MC_EMEM_ARB_TIMING_FAW */
3362                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3363                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3364                         0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3365                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3366                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3367                         0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
3368                         0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
3369                         0x06030202, /* MC_EMEM_ARB_DA_TURNS */
3370                         0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
3371                         0x7566120a, /* MC_EMEM_ARB_MISC0 */
3372                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3373                         0xe8000000, /* EMC_FBIO_SPARE */
3374                         0xff00ff89, /* EMC_CFG_RSV */
3375                 },
3376                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3377                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3378                 0x00000000, /* EMC_CFG.PERIODIC_QRST */
3379                 0x80000521, /* Mode Register 0 */
3380                 0x80100002, /* Mode Register 1 */
3381                 0x80200000, /* Mode Register 2 */
3382                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3383         },
3384         {
3385                 0x32,       /* Rev 3.2 */
3386                 750000,     /* SDRAM frequency */
3387                 {
3388                         0x00000023, /* EMC_RC */
3389                         0x000000c1, /* EMC_RFC */
3390                         0x00000019, /* EMC_RAS */
3391                         0x00000009, /* EMC_RP */
3392                         0x00000005, /* EMC_R2W */
3393                         0x0000000d, /* EMC_W2R */
3394                         0x00000004, /* EMC_R2P */
3395                         0x00000013, /* EMC_W2P */
3396                         0x00000009, /* EMC_RD_RCD */
3397                         0x00000009, /* EMC_WR_RCD */
3398                         0x00000003, /* EMC_RRD */
3399                         0x00000001, /* EMC_REXT */
3400                         0x00000000, /* EMC_WEXT */
3401                         0x00000007, /* EMC_WDV */
3402                         0x0000000b, /* EMC_QUSE */
3403                         0x00000009, /* EMC_QRST */
3404                         0x0000000c, /* EMC_QSAFE */
3405                         0x00000011, /* EMC_RDV */
3406                         0x0000169a, /* EMC_REFRESH */
3407                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3408                         0x000005a6, /* EMC_PRE_REFRESH_REQ_CNT */
3409                         0x00000003, /* EMC_PDEX2WR */
3410                         0x00000010, /* EMC_PDEX2RD */
3411                         0x00000001, /* EMC_PCHG2PDEN */
3412                         0x00000000, /* EMC_ACT2PDEN */
3413                         0x0000000e, /* EMC_AR2PDEN */
3414                         0x00000018, /* EMC_RW2PDEN */
3415                         0x000000cb, /* EMC_TXSR */
3416                         0x00000200, /* EMC_TXSRDLL */
3417                         0x00000005, /* EMC_TCKE */
3418                         0x00000017, /* EMC_TFAW */
3419                         0x00000000, /* EMC_TRPAB */
3420                         0x00000007, /* EMC_TCLKSTABLE */
3421                         0x00000008, /* EMC_TCLKSTOP */
3422                         0x000016da, /* EMC_TREFBW */
3423                         0x0000000c, /* EMC_QUSE_EXTRA */
3424                         0x00000004, /* EMC_FBIO_CFG6 */
3425                         0x00000000, /* EMC_ODT_WRITE */
3426                         0x00000000, /* EMC_ODT_READ */
3427                         0x00005088, /* EMC_FBIO_CFG5 */
3428                         0xf0080191, /* EMC_CFG_DIG_DLL */
3429                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3430                         0x00000008, /* EMC_DLL_XFORM_DQS0 */
3431                         0x00000008, /* EMC_DLL_XFORM_DQS1 */
3432                         0x00000008, /* EMC_DLL_XFORM_DQS2 */
3433                         0x00000008, /* EMC_DLL_XFORM_DQS3 */
3434                         0x00000008, /* EMC_DLL_XFORM_DQS4 */
3435                         0x00000008, /* EMC_DLL_XFORM_DQS5 */
3436                         0x00000008, /* EMC_DLL_XFORM_DQS6 */
3437                         0x00000008, /* EMC_DLL_XFORM_DQS7 */
3438                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3439                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3440                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3441                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3442                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3443                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3444                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3445                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3446                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3447                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3448                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3449                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3450                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3451                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3452                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3453                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3454                         0x0000000c, /* EMC_DLL_XFORM_DQ0 */
3455                         0x0000000c, /* EMC_DLL_XFORM_DQ1 */
3456                         0x0000000c, /* EMC_DLL_XFORM_DQ2 */
3457                         0x0000000c, /* EMC_DLL_XFORM_DQ3 */
3458                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3459                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3460                         0x22220000, /* EMC_XM2DQPADCTRL2 */
3461                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3462                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
3463                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
3464                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3465                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3466                         0x08000021, /* EMC_XM2DQSPADCTRL3 */
3467                         0x00000802, /* EMC_CTT_TERM_CTRL */
3468                         0x00020000, /* EMC_ZCAL_INTERVAL */
3469                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3470                         0x00fd000c, /* EMC_MRS_WAIT_CNT */
3471                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3472                         0x00000000, /* EMC_CTT */
3473                         0x00000000, /* EMC_CTT_DURATION */
3474                         0x80002d93, /* EMC_DYN_SELF_REF_CONTROL */
3475                         0x0000000b, /* MC_EMEM_ARB_CFG */
3476                         0x80000087, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3477                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3478                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3479                         0x00000012, /* MC_EMEM_ARB_TIMING_RC */
3480                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3481                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3482                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3483                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3484                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3485                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3486                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3487                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3488                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3489                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3490                         0x00160d12, /* MC_EMEM_ARB_DA_COVERS */
3491                         0x710c2213, /* MC_EMEM_ARB_MISC0 */
3492                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3493                         0xf8000000, /* EMC_FBIO_SPARE */
3494                         0xff00ff49, /* EMC_CFG_RSV */
3495                 },
3496                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3497                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3498                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3499                 0x80000d71, /* Mode Register 0 */
3500                 0x80100002, /* Mode Register 1 */
3501                 0x80200018, /* Mode Register 2 */
3502                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3503         },
3504         {
3505                 0x32,       /* Rev 3.2 */
3506                 800000,     /* SDRAM frequency */
3507                 {
3508                         0x00000025, /* EMC_RC */
3509                         0x000000ce, /* EMC_RFC */
3510                         0x0000001a, /* EMC_RAS */
3511                         0x00000009, /* EMC_RP */
3512                         0x00000005, /* EMC_R2W */
3513                         0x0000000d, /* EMC_W2R */
3514                         0x00000004, /* EMC_R2P */
3515                         0x00000013, /* EMC_W2P */
3516                         0x00000009, /* EMC_RD_RCD */
3517                         0x00000009, /* EMC_WR_RCD */
3518                         0x00000003, /* EMC_RRD */
3519                         0x00000001, /* EMC_REXT */
3520                         0x00000000, /* EMC_WEXT */
3521                         0x00000007, /* EMC_WDV */
3522                         0x0000000b, /* EMC_QUSE */
3523                         0x00000009, /* EMC_QRST */
3524                         0x0000000b, /* EMC_QSAFE */
3525                         0x00000011, /* EMC_RDV */
3526                         0x00001820, /* EMC_REFRESH */
3527                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3528                         0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */
3529                         0x00000003, /* EMC_PDEX2WR */
3530                         0x00000012, /* EMC_PDEX2RD */
3531                         0x00000001, /* EMC_PCHG2PDEN */
3532                         0x00000000, /* EMC_ACT2PDEN */
3533                         0x0000000f, /* EMC_AR2PDEN */
3534                         0x00000018, /* EMC_RW2PDEN */
3535                         0x000000d8, /* EMC_TXSR */
3536                         0x00000200, /* EMC_TXSRDLL */
3537                         0x00000005, /* EMC_TCKE */
3538                         0x00000018, /* EMC_TFAW */
3539                         0x00000000, /* EMC_TRPAB */
3540                         0x00000007, /* EMC_TCLKSTABLE */
3541                         0x00000008, /* EMC_TCLKSTOP */
3542                         0x00001860, /* EMC_TREFBW */
3543                         0x0000000c, /* EMC_QUSE_EXTRA */
3544                         0x00000004, /* EMC_FBIO_CFG6 */
3545                         0x00000000, /* EMC_ODT_WRITE */
3546                         0x00000000, /* EMC_ODT_READ */
3547                         0x00005088, /* EMC_FBIO_CFG5 */
3548                         0xf0070191, /* EMC_CFG_DIG_DLL */
3549                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3550                         0x0000800a, /* EMC_DLL_XFORM_DQS0 */
3551                         0x0000800a, /* EMC_DLL_XFORM_DQS1 */
3552                         0x0000800a, /* EMC_DLL_XFORM_DQS2 */
3553                         0x0000800a, /* EMC_DLL_XFORM_DQS3 */
3554                         0x0000800a, /* EMC_DLL_XFORM_DQS4 */
3555                         0x0000800a, /* EMC_DLL_XFORM_DQS5 */
3556                         0x0000800a, /* EMC_DLL_XFORM_DQS6 */
3557                         0x0000800a, /* EMC_DLL_XFORM_DQS7 */
3558                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3559                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3560                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3561                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3562                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3563                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3564                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3565                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3566                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3567                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3568                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3569                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3570                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3571                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3572                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3573                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3574                         0x0000000a, /* EMC_DLL_XFORM_DQ0 */
3575                         0x0000000a, /* EMC_DLL_XFORM_DQ1 */
3576                         0x0000000a, /* EMC_DLL_XFORM_DQ2 */
3577                         0x0000000a, /* EMC_DLL_XFORM_DQ3 */
3578                         0x000002a0, /* EMC_XM2CMDPADCTRL */
3579                         0x0600013d, /* EMC_XM2DQSPADCTRL2 */
3580                         0x22220000, /* EMC_XM2DQPADCTRL2 */
3581                         0x77fff884, /* EMC_XM2CLKPADCTRL */
3582                         0x01f1f501, /* EMC_XM2COMPPADCTRL */
3583                         0x07077404, /* EMC_XM2VTTGENPADCTRL */
3584                         0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
3585                         0x080001e8, /* EMC_XM2QUSEPADCTRL */
3586                         0x09000021, /* EMC_XM2DQSPADCTRL3 */
3587                         0x00000802, /* EMC_CTT_TERM_CTRL */
3588                         0x00020000, /* EMC_ZCAL_INTERVAL */
3589                         0x00000100, /* EMC_ZCAL_WAIT_CNT */
3590                         0x00f0000c, /* EMC_MRS_WAIT_CNT */
3591                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3592                         0x00000000, /* EMC_CTT */
3593                         0x00000000, /* EMC_CTT_DURATION */
3594                         0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */
3595                         0x0000000c, /* MC_EMEM_ARB_CFG */
3596                         0x80000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3597                         0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
3598                         0x00000005, /* MC_EMEM_ARB_TIMING_RP */
3599                         0x00000013, /* MC_EMEM_ARB_TIMING_RC */
3600                         0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
3601                         0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */
3602                         0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
3603                         0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3604                         0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3605                         0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
3606                         0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
3607                         0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
3608                         0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
3609                         0x08040202, /* MC_EMEM_ARB_DA_TURNS */
3610                         0x00160d13, /* MC_EMEM_ARB_DA_COVERS */
3611                         0x734c2414, /* MC_EMEM_ARB_MISC0 */
3612                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3613                         0xf8000000, /* EMC_FBIO_SPARE */
3614                         0xff00ff49, /* EMC_CFG_RSV */
3615                 },
3616                 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
3617                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3618                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3619                 0x80000d71, /* Mode Register 0 */
3620                 0x80100002, /* Mode Register 1 */
3621                 0x80200018, /* Mode Register 2 */
3622                 0x00000000, /* EMC_CFG.DYN_SELF_REF */
3623         },
3624 };
3625
3626 static const struct tegra_emc_table cardhu_emc_tables_k4p8g304eb[] = {
3627         {
3628                 0x32,       /* Rev 3.2 */
3629                 12750,      /* SDRAM frequency */
3630                 {
3631                         0x00000000, /* EMC_RC */
3632                         0x00000001, /* EMC_RFC */
3633                         0x00000002, /* EMC_RAS */
3634                         0x00000002, /* EMC_RP */
3635                         0x00000004, /* EMC_R2W */
3636                         0x00000004, /* EMC_W2R */
3637                         0x00000001, /* EMC_R2P */
3638                         0x00000005, /* EMC_W2P */
3639                         0x00000002, /* EMC_RD_RCD */
3640                         0x00000002, /* EMC_WR_RCD */
3641                         0x00000001, /* EMC_RRD */
3642                         0x00000001, /* EMC_REXT */
3643                         0x00000000, /* EMC_WEXT */
3644                         0x00000001, /* EMC_WDV */
3645                         0x00000003, /* EMC_QUSE */
3646                         0x00000001, /* EMC_QRST */
3647                         0x00000009, /* EMC_QSAFE */
3648                         0x0000000a, /* EMC_RDV */
3649                         0x0000002f, /* EMC_REFRESH */
3650                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3651                         0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */
3652                         0x00000001, /* EMC_PDEX2WR */
3653                         0x00000001, /* EMC_PDEX2RD */
3654                         0x00000002, /* EMC_PCHG2PDEN */
3655                         0x00000000, /* EMC_ACT2PDEN */
3656                         0x00000001, /* EMC_AR2PDEN */
3657                         0x00000007, /* EMC_RW2PDEN */
3658                         0x00000002, /* EMC_TXSR */
3659                         0x00000002, /* EMC_TXSRDLL */
3660                         0x00000003, /* EMC_TCKE */
3661                         0x00000008, /* EMC_TFAW */
3662                         0x00000004, /* EMC_TRPAB */
3663                         0x00000004, /* EMC_TCLKSTABLE */
3664                         0x00000002, /* EMC_TCLKSTOP */
3665                         0x00000036, /* EMC_TREFBW */
3666                         0x00000004, /* EMC_QUSE_EXTRA */
3667                         0x00000004, /* EMC_FBIO_CFG6 */
3668                         0x00000000, /* EMC_ODT_WRITE */
3669                         0x00000000, /* EMC_ODT_READ */
3670                         0x00004282, /* EMC_FBIO_CFG5 */
3671                         0x007800a4, /* EMC_CFG_DIG_DLL */
3672                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3673                         0x000fc000, /* EMC_DLL_XFORM_DQS0 */
3674                         0x000fc000, /* EMC_DLL_XFORM_DQS1 */
3675                         0x000fc000, /* EMC_DLL_XFORM_DQS2 */
3676                         0x000fc000, /* EMC_DLL_XFORM_DQS3 */
3677                         0x000fc000, /* EMC_DLL_XFORM_DQS4 */
3678                         0x000fc000, /* EMC_DLL_XFORM_DQS5 */
3679                         0x000fc000, /* EMC_DLL_XFORM_DQS6 */
3680                         0x000fc000, /* EMC_DLL_XFORM_DQS7 */
3681                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3682                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3683                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3684                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3685                         0x00000000, /* EMC_DLL_XFORM_QUSE4 */
3686                         0x00000000, /* EMC_DLL_XFORM_QUSE5 */
3687                         0x00000000, /* EMC_DLL_XFORM_QUSE6 */
3688                         0x00000000, /* EMC_DLL_XFORM_QUSE7 */
3689                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3690                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3691                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3692                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3693                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3694                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3695                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3696                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3697                         0x000fc000, /* EMC_DLL_XFORM_DQ0 */
3698                         0x000fc000, /* EMC_DLL_XFORM_DQ1 */
3699                         0x000fc000, /* EMC_DLL_XFORM_DQ2 */
3700                         0x000fc000, /* EMC_DLL_XFORM_DQ3 */
3701                         0x00100220, /* EMC_XM2CMDPADCTRL */
3702                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
3703                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3704                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
3705                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
3706                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
3707                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
3708                         0x08000068, /* EMC_XM2QUSEPADCTRL */
3709                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3710                         0x00000802, /* EMC_CTT_TERM_CTRL */
3711                         0x00064000, /* EMC_ZCAL_INTERVAL */
3712                         0x00000009, /* EMC_ZCAL_WAIT_CNT */
3713                         0x00090009, /* EMC_MRS_WAIT_CNT */
3714                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3715                         0x00000000, /* EMC_CTT */
3716                         0x00000000, /* EMC_CTT_DURATION */
3717                         0x80000164, /* EMC_DYN_SELF_REF_CONTROL */
3718                         0x00020001, /* MC_EMEM_ARB_CFG */
3719                         0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3720                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3721                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3722                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3723                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3724                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3725                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3726                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3727                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3728                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
3729                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
3730                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3731                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
3732                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
3733                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
3734                         0x77230303, /* MC_EMEM_ARB_MISC0 */
3735                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3736                         0xd0000000, /* EMC_FBIO_SPARE */
3737                         0xff00ff00, /* EMC_CFG_RSV */
3738                 },
3739                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
3740                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3741                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3742                 0x00000000, /* Mode Register 0 */
3743                 0x00010022, /* Mode Register 1 */
3744                 0x00020001, /* Mode Register 2 */
3745                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3746         },
3747         {
3748                 0x32,       /* Rev 3.2 */
3749                 25500,      /* SDRAM frequency */
3750                 {
3751                         0x00000001, /* EMC_RC */
3752                         0x00000003, /* EMC_RFC */
3753                         0x00000002, /* EMC_RAS */
3754                         0x00000002, /* EMC_RP */
3755                         0x00000004, /* EMC_R2W */
3756                         0x00000004, /* EMC_W2R */
3757                         0x00000001, /* EMC_R2P */
3758                         0x00000005, /* EMC_W2P */
3759                         0x00000002, /* EMC_RD_RCD */
3760                         0x00000002, /* EMC_WR_RCD */
3761                         0x00000001, /* EMC_RRD */
3762                         0x00000001, /* EMC_REXT */
3763                         0x00000000, /* EMC_WEXT */
3764                         0x00000001, /* EMC_WDV */
3765                         0x00000003, /* EMC_QUSE */
3766                         0x00000001, /* EMC_QRST */
3767                         0x00000009, /* EMC_QSAFE */
3768                         0x0000000a, /* EMC_RDV */
3769                         0x0000005e, /* EMC_REFRESH */
3770                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3771                         0x00000017, /* EMC_PRE_REFRESH_REQ_CNT */
3772                         0x00000001, /* EMC_PDEX2WR */
3773                         0x00000001, /* EMC_PDEX2RD */
3774                         0x00000002, /* EMC_PCHG2PDEN */
3775                         0x00000000, /* EMC_ACT2PDEN */
3776                         0x00000001, /* EMC_AR2PDEN */
3777                         0x00000007, /* EMC_RW2PDEN */
3778                         0x00000004, /* EMC_TXSR */
3779                         0x00000004, /* EMC_TXSRDLL */
3780                         0x00000003, /* EMC_TCKE */
3781                         0x00000008, /* EMC_TFAW */
3782                         0x00000004, /* EMC_TRPAB */
3783                         0x00000004, /* EMC_TCLKSTABLE */
3784                         0x00000002, /* EMC_TCLKSTOP */
3785                         0x00000068, /* EMC_TREFBW */
3786                         0x00000004, /* EMC_QUSE_EXTRA */
3787                         0x00000004, /* EMC_FBIO_CFG6 */
3788                         0x00000000, /* EMC_ODT_WRITE */
3789                         0x00000000, /* EMC_ODT_READ */
3790                         0x00004282, /* EMC_FBIO_CFG5 */
3791                         0x007800a4, /* EMC_CFG_DIG_DLL */
3792                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3793                         0x00098000, /* EMC_DLL_XFORM_DQS0 */
3794                         0x00098000, /* EMC_DLL_XFORM_DQS1 */
3795                         0x00098000, /* EMC_DLL_XFORM_DQS2 */
3796                         0x00098000, /* EMC_DLL_XFORM_DQS3 */
3797                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
3798                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
3799                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
3800                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
3801                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3802                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3803                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3804                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3805                         0x00000008, /* EMC_DLL_XFORM_QUSE4 */
3806                         0x00000008, /* EMC_DLL_XFORM_QUSE5 */
3807                         0x00000008, /* EMC_DLL_XFORM_QUSE6 */
3808                         0x00000008, /* EMC_DLL_XFORM_QUSE7 */
3809                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3810                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3811                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3812                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3813                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3814                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3815                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3816                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3817                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
3818                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
3819                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
3820                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
3821                         0x00100220, /* EMC_XM2CMDPADCTRL */
3822                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
3823                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3824                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
3825                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
3826                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
3827                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
3828                         0x08000068, /* EMC_XM2QUSEPADCTRL */
3829                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3830                         0x00000802, /* EMC_CTT_TERM_CTRL */
3831                         0x00064000, /* EMC_ZCAL_INTERVAL */
3832                         0x0000000a, /* EMC_ZCAL_WAIT_CNT */
3833                         0x00090009, /* EMC_MRS_WAIT_CNT */
3834                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3835                         0x00000000, /* EMC_CTT */
3836                         0x00000000, /* EMC_CTT_DURATION */
3837                         0x800001c2, /* EMC_DYN_SELF_REF_CONTROL */
3838                         0x00020001, /* MC_EMEM_ARB_CFG */
3839                         0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3840                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3841                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3842                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3843                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3844                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3845                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3846                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3847                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3848                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
3849                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
3850                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3851                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
3852                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
3853                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
3854                         0x74030303, /* MC_EMEM_ARB_MISC0 */
3855                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3856                         0x50000000, /* EMC_FBIO_SPARE */
3857                         0xff00ff00, /* EMC_CFG_RSV */
3858                 },
3859                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
3860                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3861                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3862                 0x00000000, /* Mode Register 0 */
3863                 0x00010022, /* Mode Register 1 */
3864                 0x00020001, /* Mode Register 2 */
3865                 0x00000001, /* EMC_CFG.DYN_SELF_REF */
3866         },
3867         {
3868                 0x32,       /* Rev 3.2 */
3869                 51000,      /* SDRAM frequency */
3870                 {
3871                         0x00000003, /* EMC_RC */
3872                         0x00000006, /* EMC_RFC */
3873                         0x00000002, /* EMC_RAS */
3874                         0x00000002, /* EMC_RP */
3875                         0x00000004, /* EMC_R2W */
3876                         0x00000004, /* EMC_W2R */
3877                         0x00000001, /* EMC_R2P */
3878                         0x00000005, /* EMC_W2P */
3879                         0x00000002, /* EMC_RD_RCD */
3880                         0x00000002, /* EMC_WR_RCD */
3881                         0x00000001, /* EMC_RRD */
3882                         0x00000001, /* EMC_REXT */
3883                         0x00000000, /* EMC_WEXT */
3884                         0x00000001, /* EMC_WDV */
3885                         0x00000003, /* EMC_QUSE */
3886                         0x00000001, /* EMC_QRST */
3887                         0x00000009, /* EMC_QSAFE */
3888                         0x0000000a, /* EMC_RDV */
3889                         0x000000c0, /* EMC_REFRESH */
3890                         0x00000000, /* EMC_BURST_REFRESH_NUM */
3891                         0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
3892                         0x00000001, /* EMC_PDEX2WR */
3893                         0x00000001, /* EMC_PDEX2RD */
3894                         0x00000002, /* EMC_PCHG2PDEN */
3895                         0x00000000, /* EMC_ACT2PDEN */
3896                         0x00000001, /* EMC_AR2PDEN */
3897                         0x00000007, /* EMC_RW2PDEN */
3898                         0x00000008, /* EMC_TXSR */
3899                         0x00000008, /* EMC_TXSRDLL */
3900                         0x00000003, /* EMC_TCKE */
3901                         0x00000008, /* EMC_TFAW */
3902                         0x00000004, /* EMC_TRPAB */
3903                         0x00000004, /* EMC_TCLKSTABLE */
3904                         0x00000002, /* EMC_TCLKSTOP */
3905                         0x000000d5, /* EMC_TREFBW */
3906                         0x00000004, /* EMC_QUSE_EXTRA */
3907                         0x00000004, /* EMC_FBIO_CFG6 */
3908                         0x00000000, /* EMC_ODT_WRITE */
3909                         0x00000000, /* EMC_ODT_READ */
3910                         0x00004282, /* EMC_FBIO_CFG5 */
3911                         0x007800a4, /* EMC_CFG_DIG_DLL */
3912                         0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
3913                         0x000a0000, /* EMC_DLL_XFORM_DQS0 */
3914                         0x000a0000, /* EMC_DLL_XFORM_DQS1 */
3915                         0x000a0000, /* EMC_DLL_XFORM_DQS2 */
3916                         0x000a0000, /* EMC_DLL_XFORM_DQS3 */
3917                         0x00000010, /* EMC_DLL_XFORM_DQS4 */
3918                         0x00000010, /* EMC_DLL_XFORM_DQS5 */
3919                         0x00000010, /* EMC_DLL_XFORM_DQS6 */
3920                         0x00000010, /* EMC_DLL_XFORM_DQS7 */
3921                         0x00000000, /* EMC_DLL_XFORM_QUSE0 */
3922                         0x00000000, /* EMC_DLL_XFORM_QUSE1 */
3923                         0x00000000, /* EMC_DLL_XFORM_QUSE2 */
3924                         0x00000000, /* EMC_DLL_XFORM_QUSE3 */
3925                         0x00000018, /* EMC_DLL_XFORM_QUSE4 */
3926                         0x00000018, /* EMC_DLL_XFORM_QUSE5 */
3927                         0x00000018, /* EMC_DLL_XFORM_QUSE6 */
3928                         0x00000018, /* EMC_DLL_XFORM_QUSE7 */
3929                         0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
3930                         0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
3931                         0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
3932                         0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
3933                         0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
3934                         0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
3935                         0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
3936                         0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
3937                         0x00080000, /* EMC_DLL_XFORM_DQ0 */
3938                         0x00080000, /* EMC_DLL_XFORM_DQ1 */
3939                         0x00080000, /* EMC_DLL_XFORM_DQ2 */
3940                         0x00080000, /* EMC_DLL_XFORM_DQ3 */
3941                         0x00100220, /* EMC_XM2CMDPADCTRL */
3942                         0x0800201c, /* EMC_XM2DQSPADCTRL2 */
3943                         0x00000000, /* EMC_XM2DQPADCTRL2 */
3944                         0x77ffc004, /* EMC_XM2CLKPADCTRL */
3945                         0x01f1f008, /* EMC_XM2COMPPADCTRL */
3946                         0x00000000, /* EMC_XM2VTTGENPADCTRL */
3947                         0x00000007, /* EMC_XM2VTTGENPADCTRL2 */
3948                         0x08000068, /* EMC_XM2QUSEPADCTRL */
3949                         0x08000000, /* EMC_XM2DQSPADCTRL3 */
3950                         0x00000802, /* EMC_CTT_TERM_CTRL */
3951                         0x00064000, /* EMC_ZCAL_INTERVAL */
3952                         0x00000013, /* EMC_ZCAL_WAIT_CNT */
3953                         0x00090009, /* EMC_MRS_WAIT_CNT */
3954                         0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
3955                         0x00000000, /* EMC_CTT */
3956                         0x00000000, /* EMC_CTT_DURATION */
3957                         0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
3958                         0x00010001, /* MC_EMEM_ARB_CFG */
3959                         0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
3960                         0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
3961                         0x00000001, /* MC_EMEM_ARB_TIMING_RP */
3962                         0x00000002, /* MC_EMEM_ARB_TIMING_RC */
3963                         0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
3964                         0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
3965                         0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
3966                         0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
3967                         0x00000004, /* MC_EMEM_ARB_TIMING_WAP2PRE */
3968                         0x00000001, /* MC_EMEM_ARB_TIMING_R2R */
3969                         0x00000000, /* MC_EMEM_ARB_TIMING_W2W */
3970                         0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
3971                         0x00000002, /* MC_EMEM_ARB_TIMING_W2R */
3972                         0x02020001, /* MC_EMEM_ARB_DA_TURNS */
3973                         0x00060402, /* MC_EMEM_ARB_DA_COVERS */
3974                         0x72c30303, /* MC_EMEM_ARB_MISC0 */
3975                         0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
3976                         0x50000000, /* EMC_FBIO_SPARE */
3977                         0xff00ff00, /* EMC_CFG_RSV */
3978                 },
3979                 0x00000009, /* EMC_ZCAL_WAIT_CNT after clock change */
3980                 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
3981                 0x00000001, /* EMC_CFG.PERIODIC_QRST */
3982                 0x00000000, /* Mode Register 0 */
3983                 0x00010022, /* Mode Register 1 */