c27be09faa303cea721a80aade4e5ec4b7f5430f
[linux-2.6.git] / arch / arm / mach-tegra / board-aruba.c
1 /*
2  * arch/arm/mach-tegra/board-aruba.c
3  *
4  * Copyright (c) 2010-2011, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/gpio_keys.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37
38 #include <mach/clk.h>
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/pinmux.h>
42 #include <mach/iomap.h>
43 #include <mach/io.h>
44 #include <mach/i2s.h>
45 #include <mach/audio.h>
46 #include <mach/tegra_das.h>
47
48 #include <asm/hardware/gic.h>
49 #include <asm/mach-types.h>
50 #include <asm/mach/arch.h>
51 #include <mach/usb_phy.h>
52 #include <mach/nand.h>
53
54 #include "board.h"
55 #include "clock.h"
56 #include "board-aruba.h"
57 #include "devices.h"
58 #include "gpio-names.h"
59 #include "fuse.h"
60
61 #define ENABLE_OTG 0
62
63 static struct plat_serial8250_port debug_uart_platform_data[] = {
64         {
65                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
66                 .mapbase        = TEGRA_UARTA_BASE,
67                 .irq            = INT_UARTA,
68                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
69                 .type           = PORT_TEGRA,
70                 .iotype         = UPIO_MEM,
71                 .regshift       = 2,
72                 .uartclk        = 13000000,
73         }, {
74                 .flags          = 0,
75         }
76 };
77
78 static struct platform_device debug_uart = {
79         .name = "serial8250",
80         .id = PLAT8250_DEV_PLATFORM,
81         .dev = {
82                 .platform_data = debug_uart_platform_data,
83         },
84 };
85
86 /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
87 static struct tegra_utmip_config utmi_phy_config[] = {
88         [0] = {
89                         .hssync_start_delay = 0,
90                         .idle_wait_delay = 17,
91                         .elastic_limit = 16,
92                         .term_range_adj = 6,
93                         .xcvr_setup = 15,
94                         .xcvr_lsfslew = 2,
95                         .xcvr_lsrslew = 2,
96         },
97         [1] = {
98                         .hssync_start_delay = 0,
99                         .idle_wait_delay = 17,
100                         .elastic_limit = 16,
101                         .term_range_adj = 6,
102                         .xcvr_setup = 8,
103                         .xcvr_lsfslew = 2,
104                         .xcvr_lsrslew = 2,
105         },
106 };
107
108 /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
109 static struct tegra_ulpi_config ulpi_phy_config = {
110         .clk = "cdev2",
111 };
112
113 #ifdef CONFIG_BCM4329_RFKILL
114
115 static struct resource aruba_bcm4329_rfkill_resources[] = {
116         {
117                 .name   = "bcm4329_nreset_gpio",
118                 .start  = TEGRA_GPIO_PU0,
119                 .end    = TEGRA_GPIO_PU0,
120                 .flags  = IORESOURCE_IO,
121         },
122         {
123                 .name   = "bcm4329_nshutdown_gpio",
124                 .start  = TEGRA_GPIO_PK2,
125                 .end    = TEGRA_GPIO_PK2,
126                 .flags  = IORESOURCE_IO,
127         },
128 };
129
130 static struct platform_device aruba_bcm4329_rfkill_device = {
131         .name = "bcm4329_rfkill",
132         .id             = -1,
133         .num_resources  = ARRAY_SIZE(aruba_bcm4329_rfkill_resources),
134         .resource       = aruba_bcm4329_rfkill_resources,
135 };
136
137 static noinline void __init aruba_bt_rfkill(void)
138 {
139         /*Add Clock Resource*/
140         clk_add_alias("bcm4329_32k_clk", aruba_bcm4329_rfkill_device.name, \
141                                 "blink", NULL);
142
143         platform_device_register(&aruba_bcm4329_rfkill_device);
144
145         return;
146 }
147 #else
148 static inline void aruba_bt_rfkill(void) { }
149 #endif
150
151 static __initdata struct tegra_clk_init_table aruba_clk_init_table[] = {
152         /* name         parent          rate            enabled */
153         { "uarta",      "clk_m",        13000000,       true},
154         { "uartb",      "clk_m",        13000000,       true},
155         { "uartc",      "clk_m",        13000000,       true},
156         { "uartd",      "clk_m",        13000000,       true},
157         { "uarte",      "clk_m",        13000000,       true},
158         { "pll_m",      NULL,           0,              true},
159         { "blink",      "clk_32k",      32768,          false},
160         { "pll_p_out4", "pll_p",        24000000,       true },
161         { "pwm",        "clk_32k",      32768,          false},
162         { "blink",      "clk_32k",      32768,          false},
163         { "pll_a",      NULL,           56448000,       true},
164         { "pll_a_out0", NULL,           11289600,       true},
165         { "i2s1",       "pll_a_out0",   11289600,       true},
166         { "i2s2",       "pll_a_out0",   11289600,       true},
167         { "d_audio",    "pll_a_out0",   11289600,       false},
168         { "audio_2x",   "audio",        22579200,       true},
169         { NULL,         NULL,           0,              0},
170 };
171
172 struct tegra_das_platform_data tegra_das_pdata = {
173         .tegra_dap_port_info_table = {
174                 /* I2S0 <--> NULL */
175                 [0] = {
176                         .dac_port = tegra_das_port_none,
177                         .codec_type = tegra_audio_codec_type_none,
178                         .device_property = {
179                                 .num_channels = 0,
180                                 .bits_per_sample = 0,
181                                 .rate = 0,
182                                 .master = 0,
183                                 .lrck_high_left = false,
184                                 .dac_dap_data_comm_format = 0,
185                         },
186                 },
187                 /* I2S1 <--> Hifi Codec */
188                 [1] = {
189                         .dac_port = tegra_das_port_i2s1,
190                         .codec_type = tegra_audio_codec_type_hifi,
191                         .device_property = {
192                                 .num_channels = 2,
193                                 .bits_per_sample = 16,
194                                 .rate = 48000,
195                                 .master = 0,
196                                 .lrck_high_left = false,
197                                 .dac_dap_data_comm_format =
198                                                 dac_dap_data_format_i2s,
199                         },
200                 },
201                 /* I2s2 <--> BB */
202                 [2] = {
203                         .dac_port = tegra_das_port_i2s2,
204                         .codec_type = tegra_audio_codec_type_baseband,
205                         .device_property = {
206                                 .num_channels = 1,
207                                 .bits_per_sample = 16,
208                                 .rate = 16000,
209                                 .master = 0,
210                                 .lrck_high_left = true,
211                                 .dac_dap_data_comm_format =
212                                         dac_dap_data_format_dsp,
213                         },
214                 },
215                 /* I2s3 <--> BT */
216                 [3] = {
217                         .dac_port = tegra_das_port_i2s3,
218                         .codec_type = tegra_audio_codec_type_bluetooth,
219                         .device_property = {
220                                 .num_channels = 1,
221                                 .bits_per_sample = 16,
222                                 .rate = 8000,
223                                 .master = 0,
224                                 .lrck_high_left = false,
225                                 .dac_dap_data_comm_format =
226                                         dac_dap_data_format_dsp,
227                         },
228                 },
229                 [4] = {
230                         .dac_port = tegra_das_port_none,
231                         .codec_type = tegra_audio_codec_type_none,
232                         .device_property = {
233                                 .num_channels = 0,
234                                 .bits_per_sample = 0,
235                                 .rate = 0,
236                                 .master = 0,
237                                 .lrck_high_left = false,
238                                 .dac_dap_data_comm_format = 0,
239                         },
240                 },
241         },
242 };
243
244 static struct i2c_board_info __initdata aruba_i2c_bus1_board_info[] = {
245         {
246                 I2C_BOARD_INFO("wm8903", 0x1a),
247         },
248 };
249
250 static struct tegra_i2c_platform_data aruba_i2c1_platform_data = {
251         .adapter_nr     = 0,
252         .bus_count      = 1,
253         .bus_clk_rate   = { 100000, 0 },
254 };
255
256 #if 0   /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
257 static const struct tegra_pingroup_config i2c2_ddc = {
258         .pingroup       = TEGRA_PINGROUP_DDC,
259         .func           = TEGRA_MUX_I2C2,
260 };
261
262 static const struct tegra_pingroup_config i2c2_gen2 = {
263         .pingroup       = TEGRA_PINGROUP_PTA,
264         .func           = TEGRA_MUX_I2C2,
265 };
266 #endif
267
268 static struct tegra_i2c_platform_data aruba_i2c2_platform_data = {
269         .adapter_nr     = 1,
270         .bus_count      = 2,
271         .bus_clk_rate   = { 100000, 100000 },
272 #if 0   /* !!!FIXME!!!! TESE ARE VENTANA SETTINGS */
273         .bus_mux        = { &i2c2_ddc, &i2c2_gen2 },
274         .bus_mux_len    = { 1, 1 },
275 #endif
276 };
277
278 static struct tegra_i2c_platform_data aruba_i2c3_platform_data = {
279         .adapter_nr     = 3,
280         .bus_count      = 1,
281         .bus_clk_rate   = { 100000, 0 },
282 };
283
284 static struct tegra_i2c_platform_data aruba_i2c4_platform_data = {
285         .adapter_nr     = 4,
286         .bus_count      = 1,
287         .bus_clk_rate   = { 100000, 0 },
288 };
289
290 static struct tegra_i2c_platform_data aruba_i2c5_platform_data = {
291         .adapter_nr     = 5,
292         .bus_count      = 1,
293         .bus_clk_rate   = { 100000, 0 },
294 };
295
296 static void aruba_i2c_init(void)
297 {
298         tegra_i2c_device1.dev.platform_data = &aruba_i2c1_platform_data;
299         tegra_i2c_device2.dev.platform_data = &aruba_i2c2_platform_data;
300         tegra_i2c_device3.dev.platform_data = &aruba_i2c3_platform_data;
301         tegra_i2c_device4.dev.platform_data = &aruba_i2c4_platform_data;
302         tegra_i2c_device5.dev.platform_data = &aruba_i2c5_platform_data;
303
304         i2c_register_board_info(0, aruba_i2c_bus1_board_info, 1);
305
306         platform_device_register(&tegra_i2c_device5);
307         platform_device_register(&tegra_i2c_device4);
308         platform_device_register(&tegra_i2c_device3);
309         platform_device_register(&tegra_i2c_device2);
310         platform_device_register(&tegra_i2c_device1);
311 }
312
313 #define GPIO_KEY(_id, _gpio, _iswake)           \
314         {                                       \
315                 .code = _id,                    \
316                 .gpio = TEGRA_GPIO_##_gpio,     \
317                 .active_low = 1,                \
318                 .desc = #_id,                   \
319                 .type = EV_KEY,                 \
320                 .wakeup = _iswake,              \
321                 .debounce_interval = 10,        \
322         }
323
324 // !!!FIXME!!! THESE ARE VENTANA DEFINITIONS
325 static struct gpio_keys_button aruba_keys[] = {
326         [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
327         [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
328         [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
329         [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
330         [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
331         [5] = GPIO_KEY(KEY_POWER, PV2, 1),
332 };
333
334 static struct gpio_keys_platform_data aruba_keys_platform_data = {
335         .buttons        = aruba_keys,
336         .nbuttons       = ARRAY_SIZE(aruba_keys),
337 };
338
339 static struct platform_device aruba_keys_device = {
340         .name   = "gpio-keys",
341         .id     = 0,
342         .dev    = {
343                 .platform_data  = &aruba_keys_platform_data,
344         },
345 };
346
347 static struct resource tegra_rtc_resources[] = {
348         [0] = {
349                 .start = TEGRA_RTC_BASE,
350                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
351                 .flags = IORESOURCE_MEM,
352         },
353         [1] = {
354                 .start = INT_RTC,
355                 .end = INT_RTC,
356                 .flags = IORESOURCE_IRQ,
357         },
358 };
359
360 static struct platform_device tegra_rtc_device = {
361         .name = "tegra_rtc",
362         .id   = -1,
363         .resource = tegra_rtc_resources,
364         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
365 };
366
367 #if defined(CONFIG_MTD_NAND_TEGRA)
368 static struct resource nand_resources[] = {
369         [0] = {
370                 .start = INT_NANDFLASH,
371                 .end   = INT_NANDFLASH,
372                 .flags = IORESOURCE_IRQ
373         },
374         [1] = {
375                 .start = TEGRA_NAND_BASE,
376                 .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
377                 .flags = IORESOURCE_MEM
378         }
379 };
380
381 static struct tegra_nand_chip_parms nand_chip_parms[] = {
382         /* Samsung K5E2G1GACM */
383         [0] = {
384                 .vendor_id   = 0xEC,
385                 .device_id   = 0xAA,
386                 .capacity    = 256,
387                 .timing      = {
388                         .trp            = 21,
389                         .trh            = 15,
390                         .twp            = 21,
391                         .twh            = 15,
392                         .tcs            = 31,
393                         .twhr           = 60,
394                         .tcr_tar_trr    = 20,
395                         .twb            = 100,
396                         .trp_resp       = 30,
397                         .tadl           = 100,
398                 },
399         },
400         /* Hynix H5PS1GB3EFR */
401         [1] = {
402                 .vendor_id   = 0xAD,
403                 .device_id   = 0xDC,
404                 .capacity    = 512,
405                 .timing      = {
406                         .trp            = 12,
407                         .trh            = 10,
408                         .twp            = 12,
409                         .twh            = 10,
410                         .tcs            = 20,
411                         .twhr           = 80,
412                         .tcr_tar_trr    = 20,
413                         .twb            = 100,
414                         .trp_resp       = 20,
415                         .tadl           = 70,
416                 },
417         },
418 };
419
420 struct tegra_nand_platform nand_data = {
421         .max_chips      = 8,
422         .chip_parms     = nand_chip_parms,
423         .nr_chip_parms  = ARRAY_SIZE(nand_chip_parms),
424 };
425
426 struct platform_device tegra_nand_device = {
427         .name          = "tegra_nand",
428         .id            = -1,
429         .resource      = nand_resources,
430         .num_resources = ARRAY_SIZE(nand_resources),
431         .dev            = {
432                 .platform_data = &nand_data,
433         },
434 };
435 #endif
436
437 static struct platform_device *aruba_devices[] __initdata = {
438 #if ENABLE_OTG
439         &tegra_otg_device,
440 #endif
441         &debug_uart,
442         &tegra_uartb_device,
443         &tegra_uartc_device,
444         &tegra_uartd_device,
445         &tegra_uarte_device,
446         &tegra_pmu_device,
447         &tegra_rtc_device,
448         &tegra_udc_device,
449 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
450         &tegra_smmu_device,
451 #endif
452         &aruba_keys_device,
453         &tegra_wdt_device,
454 #if defined(CONFIG_SND_HDA_TEGRA)
455         &tegra_hda_device,
456 #endif
457         &tegra_avp_device,
458 #if defined(CONFIG_MTD_NAND_TEGRA)
459         &tegra_nand_device,
460 #endif
461 };
462
463 static void aruba_keys_init(void)
464 {
465         int i;
466
467         for (i = 0; i < ARRAY_SIZE(aruba_keys); i++)
468                 tegra_gpio_enable(aruba_keys[i].gpio);
469 }
470
471 static int __init aruba_touch_init(void)
472 {
473         return 0;
474 }
475
476
477 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
478         [0] = {
479                         .phy_config = &utmi_phy_config[0],
480                         .operating_mode = TEGRA_USB_HOST,
481                         .power_down_on_bus_suspend = 0,
482         },
483         [1] = {
484                         .phy_config = &ulpi_phy_config,
485                         .operating_mode = TEGRA_USB_HOST,
486                         .power_down_on_bus_suspend = 1,
487         },
488         [2] = {
489                         .phy_config = &utmi_phy_config[1],
490                         .operating_mode = TEGRA_USB_HOST,
491                         .power_down_on_bus_suspend = 0,
492         },
493 };
494
495
496 static void aruba_usb_init(void)
497 {
498         tegra_ehci2_device.dev.platform_data=&tegra_ehci_pdata[1];
499         platform_device_register(&tegra_ehci2_device);
500 }
501
502 #ifdef CONFIG_SATA_AHCI_TEGRA
503 static void aruba_sata_init(void)
504 {
505         platform_device_register(&tegra_sata_device);
506 }
507 #else
508 static void aruba_sata_init(void) { }
509 #endif
510
511 static void __init tegra_aruba_init(void)
512 {
513         tegra_clk_init_from_table(aruba_clk_init_table);
514         tegra_enable_pinmux();
515         aruba_pinmux_init();
516
517         platform_add_devices(aruba_devices, ARRAY_SIZE(aruba_devices));
518
519         aruba_sdhci_init();
520         aruba_i2c_init();
521         aruba_regulator_init();
522         aruba_touch_init();
523         aruba_keys_init();
524         aruba_usb_init();
525         aruba_panel_init();
526         aruba_sensors_init();
527         aruba_bt_rfkill();
528         aruba_sata_init();
529         tegra_release_bootloader_fb();
530 }
531
532 static void __init tegra_aruba_reserve(void)
533 {
534 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
535         tegra_reserve(0, SZ_4M, 0);
536 #else
537         tegra_reserve(SZ_32M, SZ_4M, 0);
538 #endif
539 }
540
541 MACHINE_START(ARUBA, "aruba")
542         .boot_params    = 0x80000100,
543         .map_io         = tegra_map_common_io,
544         .reserve        = tegra_aruba_reserve,
545         .init_early     = tegra_init_early,
546         .init_irq       = tegra_init_irq,
547         .handle_irq     = gic_handle_irq,
548         .timer          = &tegra_timer,
549         .init_machine   = tegra_aruba_init,
550 MACHINE_END