4cb9572afa90386c56d7f141f2204ff74b947717
[linux-2.6.git] / arch / arm / mach-tegra / board-aruba.c
1 /*
2  * arch/arm/mach-tegra/board-aruba.c
3  *
4  * Copyright (c) 2010-2012, NVIDIA Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, write to the Free Software Foundation, Inc.,
18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
19  */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/slab.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/serial_8250.h>
28 #include <linux/i2c.h>
29 #include <linux/i2c/panjit_ts.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/i2c-tegra.h>
33 #include <linux/gpio.h>
34 #include <linux/gpio_keys.h>
35 #include <linux/input.h>
36 #include <linux/platform_data/tegra_usb.h>
37
38 #include <mach/clk.h>
39 #include <mach/iomap.h>
40 #include <mach/irqs.h>
41 #include <mach/pinmux.h>
42 #include <mach/iomap.h>
43 #include <mach/io.h>
44 #include <mach/i2s.h>
45 #include <mach/audio.h>
46 #include <mach/tegra_das.h>
47
48 #include <asm/hardware/gic.h>
49 #include <asm/mach-types.h>
50 #include <asm/mach/arch.h>
51 #include <mach/usb_phy.h>
52 #include <mach/nand.h>
53 #include <mach/tegra_fiq_debugger.h>
54
55 #include "board.h"
56 #include "clock.h"
57 #include "board-aruba.h"
58 #include "devices.h"
59 #include "gpio-names.h"
60 #include "fuse.h"
61
62 #define ENABLE_OTG 0
63
64 static struct plat_serial8250_port debug_uart_platform_data[] = {
65         {
66                 .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
67                 .mapbase        = TEGRA_UARTA_BASE,
68                 .irq            = INT_UARTA,
69                 .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
70                 .type           = PORT_TEGRA,
71                 .iotype         = UPIO_MEM,
72                 .regshift       = 2,
73                 .uartclk        = 13000000,
74         }, {
75                 .flags          = 0,
76         }
77 };
78
79 static struct platform_device debug_uart = {
80         .name = "serial8250",
81         .id = PLAT8250_DEV_PLATFORM,
82         .dev = {
83                 .platform_data = debug_uart_platform_data,
84         },
85 };
86
87 /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
88 static struct tegra_utmip_config utmi_phy_config[] = {
89         [0] = {
90                         .hssync_start_delay = 0,
91                         .idle_wait_delay = 17,
92                         .elastic_limit = 16,
93                         .term_range_adj = 6,
94                         .xcvr_setup = 15,
95                         .xcvr_lsfslew = 2,
96                         .xcvr_lsrslew = 2,
97         },
98         [1] = {
99                         .hssync_start_delay = 0,
100                         .idle_wait_delay = 17,
101                         .elastic_limit = 16,
102                         .term_range_adj = 6,
103                         .xcvr_setup = 8,
104                         .xcvr_lsfslew = 2,
105                         .xcvr_lsrslew = 2,
106         },
107 };
108
109 /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
110 static struct tegra_ulpi_config ulpi_phy_config = {
111         .clk = "cdev2",
112 };
113
114 #ifdef CONFIG_BCM4329_RFKILL
115
116 static struct resource aruba_bcm4329_rfkill_resources[] = {
117         {
118                 .name   = "bcm4329_nreset_gpio",
119                 .start  = TEGRA_GPIO_PU0,
120                 .end    = TEGRA_GPIO_PU0,
121                 .flags  = IORESOURCE_IO,
122         },
123         {
124                 .name   = "bcm4329_nshutdown_gpio",
125                 .start  = TEGRA_GPIO_PK2,
126                 .end    = TEGRA_GPIO_PK2,
127                 .flags  = IORESOURCE_IO,
128         },
129 };
130
131 static struct platform_device aruba_bcm4329_rfkill_device = {
132         .name = "bcm4329_rfkill",
133         .id             = -1,
134         .num_resources  = ARRAY_SIZE(aruba_bcm4329_rfkill_resources),
135         .resource       = aruba_bcm4329_rfkill_resources,
136 };
137
138 static noinline void __init aruba_bt_rfkill(void)
139 {
140         /*Add Clock Resource*/
141         clk_add_alias("bcm4329_32k_clk", aruba_bcm4329_rfkill_device.name, \
142                                 "blink", NULL);
143
144         platform_device_register(&aruba_bcm4329_rfkill_device);
145
146         return;
147 }
148 #else
149 static inline void aruba_bt_rfkill(void) { }
150 #endif
151
152 static __initdata struct tegra_clk_init_table aruba_clk_init_table[] = {
153         /* name         parent          rate            enabled */
154         { "uarta",      "clk_m",        13000000,       true},
155         { "uartb",      "clk_m",        13000000,       true},
156         { "uartc",      "clk_m",        13000000,       true},
157         { "uartd",      "clk_m",        13000000,       true},
158         { "uarte",      "clk_m",        13000000,       true},
159         { "pll_m",      NULL,           0,              true},
160         { "blink",      "clk_32k",      32768,          false},
161         { "pll_p_out4", "pll_p",        24000000,       true },
162         { "pwm",        "clk_32k",      32768,          false},
163         { "blink",      "clk_32k",      32768,          false},
164         { "pll_a",      NULL,           56448000,       true},
165         { "pll_a_out0", NULL,           11289600,       true},
166         { "i2s1",       "pll_a_out0",   11289600,       true},
167         { "i2s2",       "pll_a_out0",   11289600,       true},
168         { "d_audio",    "pll_a_out0",   11289600,       false},
169         { "audio_2x",   "audio",        22579200,       true},
170         { NULL,         NULL,           0,              0},
171 };
172
173 struct tegra_das_platform_data tegra_das_pdata = {
174         .tegra_dap_port_info_table = {
175                 /* I2S0 <--> NULL */
176                 [0] = {
177                         .dac_port = tegra_das_port_none,
178                         .codec_type = tegra_audio_codec_type_none,
179                         .device_property = {
180                                 .num_channels = 0,
181                                 .bits_per_sample = 0,
182                                 .rate = 0,
183                                 .master = 0,
184                                 .lrck_high_left = false,
185                                 .dac_dap_data_comm_format = 0,
186                         },
187                 },
188                 /* I2S1 <--> Hifi Codec */
189                 [1] = {
190                         .dac_port = tegra_das_port_i2s1,
191                         .codec_type = tegra_audio_codec_type_hifi,
192                         .device_property = {
193                                 .num_channels = 2,
194                                 .bits_per_sample = 16,
195                                 .rate = 48000,
196                                 .master = 0,
197                                 .lrck_high_left = false,
198                                 .dac_dap_data_comm_format =
199                                                 dac_dap_data_format_i2s,
200                         },
201                 },
202                 /* I2s2 <--> BB */
203                 [2] = {
204                         .dac_port = tegra_das_port_i2s2,
205                         .codec_type = tegra_audio_codec_type_baseband,
206                         .device_property = {
207                                 .num_channels = 1,
208                                 .bits_per_sample = 16,
209                                 .rate = 16000,
210                                 .master = 0,
211                                 .lrck_high_left = true,
212                                 .dac_dap_data_comm_format =
213                                         dac_dap_data_format_dsp,
214                         },
215                 },
216                 /* I2s3 <--> BT */
217                 [3] = {
218                         .dac_port = tegra_das_port_i2s3,
219                         .codec_type = tegra_audio_codec_type_bluetooth,
220                         .device_property = {
221                                 .num_channels = 1,
222                                 .bits_per_sample = 16,
223                                 .rate = 8000,
224                                 .master = 0,
225                                 .lrck_high_left = false,
226                                 .dac_dap_data_comm_format =
227                                         dac_dap_data_format_dsp,
228                         },
229                 },
230                 [4] = {
231                         .dac_port = tegra_das_port_none,
232                         .codec_type = tegra_audio_codec_type_none,
233                         .device_property = {
234                                 .num_channels = 0,
235                                 .bits_per_sample = 0,
236                                 .rate = 0,
237                                 .master = 0,
238                                 .lrck_high_left = false,
239                                 .dac_dap_data_comm_format = 0,
240                         },
241                 },
242         },
243 };
244
245 static struct i2c_board_info __initdata aruba_i2c_bus1_board_info[] = {
246         {
247                 I2C_BOARD_INFO("wm8903", 0x1a),
248         },
249 };
250
251 static struct tegra_i2c_platform_data aruba_i2c1_platform_data = {
252         .adapter_nr     = 0,
253         .bus_count      = 1,
254         .bus_clk_rate   = { 100000, 0 },
255 };
256
257 #if 0   /* !!!FIXME!!! THESE ARE VENTANA SETTINGS */
258 static const struct tegra_pingroup_config i2c2_ddc = {
259         .pingroup       = TEGRA_PINGROUP_DDC,
260         .func           = TEGRA_MUX_I2C2,
261 };
262
263 static const struct tegra_pingroup_config i2c2_gen2 = {
264         .pingroup       = TEGRA_PINGROUP_PTA,
265         .func           = TEGRA_MUX_I2C2,
266 };
267 #endif
268
269 static struct tegra_i2c_platform_data aruba_i2c2_platform_data = {
270         .adapter_nr     = 1,
271         .bus_count      = 2,
272         .bus_clk_rate   = { 100000, 100000 },
273 #if 0   /* !!!FIXME!!!! TESE ARE VENTANA SETTINGS */
274         .bus_mux        = { &i2c2_ddc, &i2c2_gen2 },
275         .bus_mux_len    = { 1, 1 },
276 #endif
277 };
278
279 static struct tegra_i2c_platform_data aruba_i2c3_platform_data = {
280         .adapter_nr     = 3,
281         .bus_count      = 1,
282         .bus_clk_rate   = { 100000, 0 },
283 };
284
285 static struct tegra_i2c_platform_data aruba_i2c4_platform_data = {
286         .adapter_nr     = 4,
287         .bus_count      = 1,
288         .bus_clk_rate   = { 100000, 0 },
289 };
290
291 static struct tegra_i2c_platform_data aruba_i2c5_platform_data = {
292         .adapter_nr     = 5,
293         .bus_count      = 1,
294         .bus_clk_rate   = { 100000, 0 },
295 };
296
297 static void aruba_i2c_init(void)
298 {
299         tegra_i2c_device1.dev.platform_data = &aruba_i2c1_platform_data;
300         tegra_i2c_device2.dev.platform_data = &aruba_i2c2_platform_data;
301         tegra_i2c_device3.dev.platform_data = &aruba_i2c3_platform_data;
302         tegra_i2c_device4.dev.platform_data = &aruba_i2c4_platform_data;
303         tegra_i2c_device5.dev.platform_data = &aruba_i2c5_platform_data;
304
305         i2c_register_board_info(0, aruba_i2c_bus1_board_info, 1);
306
307         platform_device_register(&tegra_i2c_device5);
308         platform_device_register(&tegra_i2c_device4);
309         platform_device_register(&tegra_i2c_device3);
310         platform_device_register(&tegra_i2c_device2);
311         platform_device_register(&tegra_i2c_device1);
312 }
313
314 #define GPIO_KEY(_id, _gpio, _iswake)           \
315         {                                       \
316                 .code = _id,                    \
317                 .gpio = TEGRA_GPIO_##_gpio,     \
318                 .active_low = 1,                \
319                 .desc = #_id,                   \
320                 .type = EV_KEY,                 \
321                 .wakeup = _iswake,              \
322                 .debounce_interval = 10,        \
323         }
324
325 // !!!FIXME!!! THESE ARE VENTANA DEFINITIONS
326 static struct gpio_keys_button aruba_keys[] = {
327         [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
328         [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
329         [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
330         [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
331         [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
332         [5] = GPIO_KEY(KEY_POWER, PV2, 1),
333 };
334
335 static struct gpio_keys_platform_data aruba_keys_platform_data = {
336         .buttons        = aruba_keys,
337         .nbuttons       = ARRAY_SIZE(aruba_keys),
338 };
339
340 static struct platform_device aruba_keys_device = {
341         .name   = "gpio-keys",
342         .id     = 0,
343         .dev    = {
344                 .platform_data  = &aruba_keys_platform_data,
345         },
346 };
347
348 static struct resource tegra_rtc_resources[] = {
349         [0] = {
350                 .start = TEGRA_RTC_BASE,
351                 .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
352                 .flags = IORESOURCE_MEM,
353         },
354         [1] = {
355                 .start = INT_RTC,
356                 .end = INT_RTC,
357                 .flags = IORESOURCE_IRQ,
358         },
359 };
360
361 static struct platform_device tegra_rtc_device = {
362         .name = "tegra_rtc",
363         .id   = -1,
364         .resource = tegra_rtc_resources,
365         .num_resources = ARRAY_SIZE(tegra_rtc_resources),
366 };
367
368 #if defined(CONFIG_MTD_NAND_TEGRA)
369 static struct resource nand_resources[] = {
370         [0] = {
371                 .start = INT_NANDFLASH,
372                 .end   = INT_NANDFLASH,
373                 .flags = IORESOURCE_IRQ
374         },
375         [1] = {
376                 .start = TEGRA_NAND_BASE,
377                 .end = TEGRA_NAND_BASE + TEGRA_NAND_SIZE - 1,
378                 .flags = IORESOURCE_MEM
379         }
380 };
381
382 static struct tegra_nand_chip_parms nand_chip_parms[] = {
383         /* Samsung K5E2G1GACM */
384         [0] = {
385                 .vendor_id   = 0xEC,
386                 .device_id   = 0xAA,
387                 .capacity    = 256,
388                 .timing      = {
389                         .trp            = 21,
390                         .trh            = 15,
391                         .twp            = 21,
392                         .twh            = 15,
393                         .tcs            = 31,
394                         .twhr           = 60,
395                         .tcr_tar_trr    = 20,
396                         .twb            = 100,
397                         .trp_resp       = 30,
398                         .tadl           = 100,
399                 },
400         },
401         /* Hynix H5PS1GB3EFR */
402         [1] = {
403                 .vendor_id   = 0xAD,
404                 .device_id   = 0xDC,
405                 .capacity    = 512,
406                 .timing      = {
407                         .trp            = 12,
408                         .trh            = 10,
409                         .twp            = 12,
410                         .twh            = 10,
411                         .tcs            = 20,
412                         .twhr           = 80,
413                         .tcr_tar_trr    = 20,
414                         .twb            = 100,
415                         .trp_resp       = 20,
416                         .tadl           = 70,
417                 },
418         },
419 };
420
421 struct tegra_nand_platform nand_data = {
422         .max_chips      = 8,
423         .chip_parms     = nand_chip_parms,
424         .nr_chip_parms  = ARRAY_SIZE(nand_chip_parms),
425 };
426
427 struct platform_device tegra_nand_device = {
428         .name          = "tegra_nand",
429         .id            = -1,
430         .resource      = nand_resources,
431         .num_resources = ARRAY_SIZE(nand_resources),
432         .dev            = {
433                 .platform_data = &nand_data,
434         },
435 };
436 #endif
437
438 static struct platform_device *aruba_devices[] __initdata = {
439 #if ENABLE_OTG
440         &tegra_otg_device,
441 #endif
442         &debug_uart,
443         &tegra_uartb_device,
444         &tegra_uartc_device,
445         &tegra_uartd_device,
446         &tegra_uarte_device,
447         &tegra_pmu_device,
448         &tegra_rtc_device,
449         &tegra_udc_device,
450 #if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU)
451         &tegra_smmu_device,
452 #endif
453         &aruba_keys_device,
454         &tegra_wdt0_device,
455         &tegra_wdt1_device,
456         &tegra_wdt2_device,
457 #if defined(CONFIG_SND_HDA_TEGRA)
458         &tegra_hda_device,
459 #endif
460         &tegra_avp_device,
461 #if defined(CONFIG_MTD_NAND_TEGRA)
462         &tegra_nand_device,
463 #endif
464 };
465
466 static void aruba_keys_init(void)
467 {
468         int i;
469
470         for (i = 0; i < ARRAY_SIZE(aruba_keys); i++)
471                 tegra_gpio_enable(aruba_keys[i].gpio);
472 }
473
474 static int __init aruba_touch_init(void)
475 {
476         return 0;
477 }
478
479
480 static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
481         [0] = {
482                         .phy_config = &utmi_phy_config[0],
483                         .operating_mode = TEGRA_USB_HOST,
484                         .power_down_on_bus_suspend = 0,
485         },
486         [1] = {
487                         .phy_config = &ulpi_phy_config,
488                         .operating_mode = TEGRA_USB_HOST,
489                         .power_down_on_bus_suspend = 1,
490         },
491         [2] = {
492                         .phy_config = &utmi_phy_config[1],
493                         .operating_mode = TEGRA_USB_HOST,
494                         .power_down_on_bus_suspend = 0,
495         },
496 };
497
498
499 static void aruba_usb_init(void)
500 {
501         tegra_ehci2_device.dev.platform_data=&tegra_ehci_pdata[1];
502         platform_device_register(&tegra_ehci2_device);
503 }
504
505 #ifdef CONFIG_SATA_AHCI_TEGRA
506 static void aruba_sata_init(void)
507 {
508         platform_device_register(&tegra_sata_device);
509 }
510 #else
511 static void aruba_sata_init(void) { }
512 #endif
513
514 static void __init tegra_aruba_init(void)
515 {
516         tegra_clk_init_from_table(aruba_clk_init_table);
517         tegra_enable_pinmux();
518         aruba_pinmux_init();
519
520         platform_add_devices(aruba_devices, ARRAY_SIZE(aruba_devices));
521
522         aruba_sdhci_init();
523         aruba_i2c_init();
524         aruba_regulator_init();
525         aruba_touch_init();
526         aruba_keys_init();
527         aruba_usb_init();
528         aruba_panel_init();
529         aruba_sensors_init();
530         aruba_bt_rfkill();
531         aruba_sata_init();
532         tegra_release_bootloader_fb();
533         tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1);
534 }
535
536 static void __init tegra_aruba_reserve(void)
537 {
538 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
539         tegra_reserve(0, SZ_4M, 0);
540 #else
541         tegra_reserve(SZ_32M, SZ_4M, 0);
542 #endif
543 }
544
545 MACHINE_START(ARUBA, "aruba")
546         .boot_params    = 0x80000100,
547         .map_io         = tegra_map_common_io,
548         .reserve        = tegra_aruba_reserve,
549         .init_early     = tegra_init_early,
550         .init_irq       = tegra_init_irq,
551         .handle_irq     = gic_handle_irq,
552         .timer          = &tegra_timer,
553         .init_machine   = tegra_aruba_init,
554 MACHINE_END