Merge branch 'next/soc-exynos5250-arch' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / arm / mach-sa1100 / jornada720.c
1 /*
2  * linux/arch/arm/mach-sa1100/jornada720.c
3  *
4  * HP Jornada720 init code
5  *
6  * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
7  * Copyright (C) 2006 Filip Zyzniewski <filip.zyzniewski@tefnet.pl>
8  *  Copyright (C) 2005 Michael Gernoth <michael@gernoth.net>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14  */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/tty.h>
19 #include <linux/delay.h>
20 #include <linux/platform_device.h>
21 #include <linux/ioport.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <video/s1d13xxxfb.h>
25
26 #include <mach/hardware.h>
27 #include <asm/hardware/sa1111.h>
28 #include <asm/irq.h>
29 #include <asm/page.h>
30 #include <asm/mach-types.h>
31 #include <asm/setup.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/flash.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/serial_sa1100.h>
36
37 #include "generic.h"
38
39 /*
40  * HP Documentation referred in this file:
41  * http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt
42  */
43
44 /* line 110 of HP's doc */
45 #define TUCR_VAL        0x20000400
46
47 /* memory space (line 52 of HP's doc) */
48 #define SA1111REGSTART  0x40000000
49 #define SA1111REGLEN    0x00001fff
50 #define EPSONREGSTART   0x48000000
51 #define EPSONREGLEN     0x00100000
52 #define EPSONFBSTART    0x48200000
53 /* 512kB framebuffer */
54 #define EPSONFBLEN      512*1024
55
56 static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
57         /* line 344 of HP's doc */
58         {0x0001,0x00},  // Miscellaneous Register
59         {0x01FC,0x00},  // Display Mode Register
60         {0x0004,0x00},  // General IO Pins Configuration Register 0
61         {0x0005,0x00},  // General IO Pins Configuration Register 1
62         {0x0008,0x00},  // General IO Pins Control Register 0
63         {0x0009,0x00},  // General IO Pins Control Register 1
64         {0x0010,0x01},  // Memory Clock Configuration Register
65         {0x0014,0x11},  // LCD Pixel Clock Configuration Register
66         {0x0018,0x01},  // CRT/TV Pixel Clock Configuration Register
67         {0x001C,0x01},  // MediaPlug Clock Configuration Register
68         {0x001E,0x01},  // CPU To Memory Wait State Select Register
69         {0x0020,0x00},  // Memory Configuration Register
70         {0x0021,0x45},  // DRAM Refresh Rate Register
71         {0x002A,0x01},  // DRAM Timings Control Register 0
72         {0x002B,0x03},  // DRAM Timings Control Register 1
73         {0x0030,0x1c},  // Panel Type Register
74         {0x0031,0x00},  // MOD Rate Register
75         {0x0032,0x4F},  // LCD Horizontal Display Width Register
76         {0x0034,0x07},  // LCD Horizontal Non-Display Period Register
77         {0x0035,0x01},  // TFT FPLINE Start Position Register
78         {0x0036,0x0B},  // TFT FPLINE Pulse Width Register
79         {0x0038,0xEF},  // LCD Vertical Display Height Register 0
80         {0x0039,0x00},  // LCD Vertical Display Height Register 1
81         {0x003A,0x13},  // LCD Vertical Non-Display Period Register
82         {0x003B,0x0B},  // TFT FPFRAME Start Position Register
83         {0x003C,0x01},  // TFT FPFRAME Pulse Width Register
84         {0x0040,0x05},  // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
85         {0x0041,0x00},  // LCD Miscellaneous Register
86         {0x0042,0x00},  // LCD Display Start Address Register 0
87         {0x0043,0x00},  // LCD Display Start Address Register 1
88         {0x0044,0x00},  // LCD Display Start Address Register 2
89         {0x0046,0x80},  // LCD Memory Address Offset Register 0
90         {0x0047,0x02},  // LCD Memory Address Offset Register 1
91         {0x0048,0x00},  // LCD Pixel Panning Register
92         {0x004A,0x00},  // LCD Display FIFO High Threshold Control Register
93         {0x004B,0x00},  // LCD Display FIFO Low Threshold Control Register
94         {0x0050,0x4F},  // CRT/TV Horizontal Display Width Register
95         {0x0052,0x13},  // CRT/TV Horizontal Non-Display Period Register
96         {0x0053,0x01},  // CRT/TV HRTC Start Position Register
97         {0x0054,0x0B},  // CRT/TV HRTC Pulse Width Register
98         {0x0056,0xDF},  // CRT/TV Vertical Display Height Register 0
99         {0x0057,0x01},  // CRT/TV Vertical Display Height Register 1
100         {0x0058,0x2B},  // CRT/TV Vertical Non-Display Period Register
101         {0x0059,0x09},  // CRT/TV VRTC Start Position Register
102         {0x005A,0x01},  // CRT/TV VRTC Pulse Width Register
103         {0x005B,0x10},  // TV Output Control Register
104         {0x0060,0x03},  // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
105         {0x0062,0x00},  // CRT/TV Display Start Address Register 0
106         {0x0063,0x00},  // CRT/TV Display Start Address Register 1
107         {0x0064,0x00},  // CRT/TV Display Start Address Register 2
108         {0x0066,0x40},  // CRT/TV Memory Address Offset Register 0
109         {0x0067,0x01},  // CRT/TV Memory Address Offset Register 1
110         {0x0068,0x00},  // CRT/TV Pixel Panning Register
111         {0x006A,0x00},  // CRT/TV Display FIFO High Threshold Control Register
112         {0x006B,0x00},  // CRT/TV Display FIFO Low Threshold Control Register
113         {0x0070,0x00},  // LCD Ink/Cursor Control Register
114         {0x0071,0x01},  // LCD Ink/Cursor Start Address Register
115         {0x0072,0x00},  // LCD Cursor X Position Register 0
116         {0x0073,0x00},  // LCD Cursor X Position Register 1
117         {0x0074,0x00},  // LCD Cursor Y Position Register 0
118         {0x0075,0x00},  // LCD Cursor Y Position Register 1
119         {0x0076,0x00},  // LCD Ink/Cursor Blue Color 0 Register
120         {0x0077,0x00},  // LCD Ink/Cursor Green Color 0 Register
121         {0x0078,0x00},  // LCD Ink/Cursor Red Color 0 Register
122         {0x007A,0x1F},  // LCD Ink/Cursor Blue Color 1 Register
123         {0x007B,0x3F},  // LCD Ink/Cursor Green Color 1 Register
124         {0x007C,0x1F},  // LCD Ink/Cursor Red Color 1 Register
125         {0x007E,0x00},  // LCD Ink/Cursor FIFO Threshold Register
126         {0x0080,0x00},  // CRT/TV Ink/Cursor Control Register
127         {0x0081,0x01},  // CRT/TV Ink/Cursor Start Address Register
128         {0x0082,0x00},  // CRT/TV Cursor X Position Register 0
129         {0x0083,0x00},  // CRT/TV Cursor X Position Register 1
130         {0x0084,0x00},  // CRT/TV Cursor Y Position Register 0
131         {0x0085,0x00},  // CRT/TV Cursor Y Position Register 1
132         {0x0086,0x00},  // CRT/TV Ink/Cursor Blue Color 0 Register
133         {0x0087,0x00},  // CRT/TV Ink/Cursor Green Color 0 Register
134         {0x0088,0x00},  // CRT/TV Ink/Cursor Red Color 0 Register
135         {0x008A,0x1F},  // CRT/TV Ink/Cursor Blue Color 1 Register
136         {0x008B,0x3F},  // CRT/TV Ink/Cursor Green Color 1 Register
137         {0x008C,0x1F},  // CRT/TV Ink/Cursor Red Color 1 Register
138         {0x008E,0x00},  // CRT/TV Ink/Cursor FIFO Threshold Register
139         {0x0100,0x00},  // BitBlt Control Register 0
140         {0x0101,0x00},  // BitBlt Control Register 1
141         {0x0102,0x00},  // BitBlt ROP Code/Color Expansion Register
142         {0x0103,0x00},  // BitBlt Operation Register
143         {0x0104,0x00},  // BitBlt Source Start Address Register 0
144         {0x0105,0x00},  // BitBlt Source Start Address Register 1
145         {0x0106,0x00},  // BitBlt Source Start Address Register 2
146         {0x0108,0x00},  // BitBlt Destination Start Address Register 0
147         {0x0109,0x00},  // BitBlt Destination Start Address Register 1
148         {0x010A,0x00},  // BitBlt Destination Start Address Register 2
149         {0x010C,0x00},  // BitBlt Memory Address Offset Register 0
150         {0x010D,0x00},  // BitBlt Memory Address Offset Register 1
151         {0x0110,0x00},  // BitBlt Width Register 0
152         {0x0111,0x00},  // BitBlt Width Register 1
153         {0x0112,0x00},  // BitBlt Height Register 0
154         {0x0113,0x00},  // BitBlt Height Register 1
155         {0x0114,0x00},  // BitBlt Background Color Register 0
156         {0x0115,0x00},  // BitBlt Background Color Register 1
157         {0x0118,0x00},  // BitBlt Foreground Color Register 0
158         {0x0119,0x00},  // BitBlt Foreground Color Register 1
159         {0x01E0,0x00},  // Look-Up Table Mode Register
160         {0x01E2,0x00},  // Look-Up Table Address Register
161         /* not sure, wouldn't like to mess with the driver */
162         {0x01E4,0x00},  // Look-Up Table Data Register
163         /* jornada doc says 0x00, but I trust the driver */
164         {0x01F0,0x10},  // Power Save Configuration Register
165         {0x01F1,0x00},  // Power Save Status Register
166         {0x01F4,0x00},  // CPU-to-Memory Access Watchdog Timer Register
167         {0x01FC,0x01},  // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT)
168 };
169
170 static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
171         .initregs               = s1d13xxxfb_initregs,
172         .initregssize           = ARRAY_SIZE(s1d13xxxfb_initregs),
173         .platform_init_video    = NULL
174 };
175
176 static struct resource s1d13xxxfb_resources[] = {
177         [0] = {
178                 .start  = EPSONFBSTART,
179                 .end    = EPSONFBSTART + EPSONFBLEN,
180                 .flags  = IORESOURCE_MEM,
181         },
182         [1] = {
183                 .start  = EPSONREGSTART,
184                 .end    = EPSONREGSTART + EPSONREGLEN,
185                 .flags  = IORESOURCE_MEM,
186         }
187 };
188
189 static struct platform_device s1d13xxxfb_device = {
190         .name           = S1D_DEVICENAME,
191         .id             = 0,
192         .dev            = {
193                 .platform_data  = &s1d13xxxfb_data,
194         },
195         .num_resources  = ARRAY_SIZE(s1d13xxxfb_resources),
196         .resource       = s1d13xxxfb_resources,
197 };
198
199 static struct resource sa1111_resources[] = {
200         [0] = {
201                 .start          = SA1111REGSTART,
202                 .end            = SA1111REGSTART + SA1111REGLEN,
203                 .flags          = IORESOURCE_MEM,
204         },
205         [1] = {
206                 .start          = IRQ_GPIO1,
207                 .end            = IRQ_GPIO1,
208                 .flags          = IORESOURCE_IRQ,
209         },
210 };
211
212 static struct sa1111_platform_data sa1111_info = {
213         .irq_base       = IRQ_BOARD_END,
214 };
215
216 static u64 sa1111_dmamask = 0xffffffffUL;
217
218 static struct platform_device sa1111_device = {
219         .name           = "sa1111",
220         .id             = 0,
221         .dev            = {
222                 .dma_mask = &sa1111_dmamask,
223                 .coherent_dma_mask = 0xffffffff,
224                 .platform_data = &sa1111_info,
225         },
226         .num_resources  = ARRAY_SIZE(sa1111_resources),
227         .resource       = sa1111_resources,
228 };
229
230 static struct platform_device jornada_ssp_device = {
231         .name           = "jornada_ssp",
232         .id             = -1,
233 };
234
235 static struct platform_device jornada_kbd_device = {
236         .name           = "jornada720_kbd",
237         .id             = -1,
238 };
239
240 static struct platform_device jornada_ts_device = {
241         .name           = "jornada_ts",
242         .id             = -1,
243 };
244
245 static struct platform_device *devices[] __initdata = {
246         &sa1111_device,
247         &jornada_ssp_device,
248         &s1d13xxxfb_device,
249         &jornada_kbd_device,
250         &jornada_ts_device,
251 };
252
253 static int __init jornada720_init(void)
254 {
255         int ret = -ENODEV;
256
257         if (machine_is_jornada720()) {
258                 /* we want to use gpio20 as input to drive the clock of our uart 3 */
259                 GPDR |= GPIO_GPIO20;    /* Clear gpio20 pin as input */
260                 TUCR = TUCR_VAL;
261                 GPSR = GPIO_GPIO20;     /* start gpio20 pin */
262                 udelay(1);
263                 GPCR = GPIO_GPIO20;     /* stop gpio20 */
264                 udelay(1);
265                 GPSR = GPIO_GPIO20;     /* restart gpio20 */
266                 udelay(20);             /* give it some time to restart */
267
268                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
269         }
270
271         return ret;
272 }
273
274 arch_initcall(jornada720_init);
275
276 static struct map_desc jornada720_io_desc[] __initdata = {
277         {       /* Epson registers */
278                 .virtual        = 0xf0000000,
279                 .pfn            = __phys_to_pfn(EPSONREGSTART),
280                 .length         = EPSONREGLEN,
281                 .type           = MT_DEVICE
282         }, {    /* Epson frame buffer */
283                 .virtual        = 0xf1000000,
284                 .pfn            = __phys_to_pfn(EPSONFBSTART),
285                 .length         = EPSONFBLEN,
286                 .type           = MT_DEVICE
287         }, {    /* SA-1111 */
288                 .virtual        = 0xf4000000,
289                 .pfn            = __phys_to_pfn(SA1111REGSTART),
290                 .length         = SA1111REGLEN,
291                 .type           = MT_DEVICE
292         }
293 };
294
295 static void __init jornada720_map_io(void)
296 {
297         sa1100_map_io();
298         iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc));
299
300         sa1100_register_uart(0, 3);
301         sa1100_register_uart(1, 1);
302 }
303
304 static struct mtd_partition jornada720_partitions[] = {
305         {
306                 .name           = "JORNADA720 boot firmware",
307                 .size           = 0x00040000,
308                 .offset         = 0,
309                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
310         }, {
311                 .name           = "JORNADA720 kernel",
312                 .size           = 0x000c0000,
313                 .offset         = 0x00040000,
314         }, {
315                 .name           = "JORNADA720 params",
316                 .size           = 0x00040000,
317                 .offset         = 0x00100000,
318         }, {
319                 .name           = "JORNADA720 initrd",
320                 .size           = 0x00100000,
321                 .offset         = 0x00140000,
322         }, {
323                 .name           = "JORNADA720 root cramfs",
324                 .size           = 0x00300000,
325                 .offset         = 0x00240000,
326         }, {
327                 .name           = "JORNADA720 usr cramfs",
328                 .size           = 0x00800000,
329                 .offset         = 0x00540000,
330         }, {
331                 .name           = "JORNADA720 usr local",
332                 .size           = 0, /* will expand to the end of the flash */
333                 .offset         = 0x00d00000,
334         }
335 };
336
337 static void jornada720_set_vpp(int vpp)
338 {
339         if (vpp)
340                 /* enabling flash write (line 470 of HP's doc) */
341                 PPSR |= PPC_LDD7;
342         else
343                 /* disabling flash write (line 470 of HP's doc) */
344                 PPSR &= ~PPC_LDD7;
345         PPDR |= PPC_LDD7;
346 }
347
348 static struct flash_platform_data jornada720_flash_data = {
349         .map_name       = "cfi_probe",
350         .set_vpp        = jornada720_set_vpp,
351         .parts          = jornada720_partitions,
352         .nr_parts       = ARRAY_SIZE(jornada720_partitions),
353 };
354
355 static struct resource jornada720_flash_resource = {
356         .start          = SA1100_CS0_PHYS,
357         .end            = SA1100_CS0_PHYS + SZ_32M - 1,
358         .flags          = IORESOURCE_MEM,
359 };
360
361 static void __init jornada720_mach_init(void)
362 {
363         sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1);
364 }
365
366 MACHINE_START(JORNADA720, "HP Jornada 720")
367         /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
368         .atag_offset    = 0x100,
369         .map_io         = jornada720_map_io,
370         .init_irq       = sa1100_init_irq,
371         .timer          = &sa1100_timer,
372         .init_machine   = jornada720_mach_init,
373 #ifdef CONFIG_SA1111
374         .dma_zone_size  = SZ_1M,
375 #endif
376         .restart        = sa11x0_restart,
377 MACHINE_END