Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / arch / arm / mach-s5pc100 / include / mach / map.h
1 /* linux/arch/arm/mach-s5pc100/include/mach/map.h
2  *
3  * Copyright 2009 Samsung Electronics Co.
4  *      Byungho Min <bhmin@samsung.com>
5  *
6  * S5PC100 - Memory map definitions
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #ifndef __ASM_ARCH_MAP_H
14 #define __ASM_ARCH_MAP_H __FILE__
15
16 #include <plat/map-base.h>
17 #include <plat/map-s5p.h>
18
19 /*
20  * map-base.h has already defined virtual memory address
21  * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
22  * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
23  * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
24  * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
25  * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
26  * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
27  *
28  * S5PC100 specific virtual memory address can be defined here
29  * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
30  *
31  */
32
33 #define S5PC100_PA_ONENAND_BUF  (0xB0000000)
34 #define S5PC100_SZ_ONENAND_BUF  (SZ_256M - SZ_32M)
35
36 /* Chip ID */
37
38 #define S5PC100_PA_CHIPID       (0xE0000000)
39 #define S5P_PA_CHIPID           S5PC100_PA_CHIPID
40
41 #define S5PC100_PA_SYSCON       (0xE0100000)
42 #define S5P_PA_SYSCON           S5PC100_PA_SYSCON
43
44 #define S5PC100_PA_OTHERS       (0xE0200000)
45 #define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
46
47 #define S5PC100_PA_GPIO         (0xE0300000)
48 #define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
49
50 /* Interrupt */
51 #define S5PC100_PA_VIC0         (0xE4000000)
52 #define S5PC100_PA_VIC1         (0xE4100000)
53 #define S5PC100_PA_VIC2         (0xE4200000)
54 #define S5PC100_VA_VIC          S3C_VA_IRQ
55 #define S5PC100_VA_VIC_OFFSET   0x10000
56 #define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57
58 #define S5PC100_PA_SROMC        (0xE7000000)
59 #define S5P_PA_SROMC            S5PC100_PA_SROMC
60
61 #define S5PC100_PA_ONENAND      (0xE7100000)
62
63 #define S5PC100_PA_CFCON        (0xE7800000)
64
65 /* DMA */
66 #define S5PC100_PA_MDMA         (0xE8100000)
67 #define S5PC100_PA_PDMA0        (0xE9000000)
68 #define S5PC100_PA_PDMA1        (0xE9200000)
69
70 /* Timer */
71 #define S5PC100_PA_TIMER        (0xEA000000)
72 #define S5P_PA_TIMER            S5PC100_PA_TIMER
73
74 #define S5PC100_PA_SYSTIMER     (0xEA100000)
75
76 #define S5PC100_PA_WATCHDOG     (0xEA200000)
77 #define S5PC100_PA_RTC          (0xEA300000)
78
79 #define S5PC100_PA_UART         (0xEC000000)
80
81 #define S5P_PA_UART0            (S5PC100_PA_UART + 0x0)
82 #define S5P_PA_UART1            (S5PC100_PA_UART + 0x400)
83 #define S5P_PA_UART2            (S5PC100_PA_UART + 0x800)
84 #define S5P_PA_UART3            (S5PC100_PA_UART + 0xC00)
85 #define S5P_SZ_UART             SZ_256
86
87 #define S5PC100_PA_IIC0         (0xEC100000)
88 #define S5PC100_PA_IIC1         (0xEC200000)
89
90 /* SPI */
91 #define S5PC100_PA_SPI0         0xEC300000
92 #define S5PC100_PA_SPI1         0xEC400000
93 #define S5PC100_PA_SPI2         0xEC500000
94
95 /* USB HS OTG */
96 #define S5PC100_PA_USB_HSOTG    (0xED200000)
97 #define S5PC100_PA_USB_HSPHY    (0xED300000)
98
99 #define S5PC100_PA_FB           (0xEE000000)
100
101 #define S5PC100_PA_FIMC0        (0xEE200000)
102 #define S5PC100_PA_FIMC1        (0xEE300000)
103 #define S5PC100_PA_FIMC2        (0xEE400000)
104
105 #define S5PC100_PA_I2S0         (0xF2000000)
106 #define S5PC100_PA_I2S1         (0xF2100000)
107 #define S5PC100_PA_I2S2         (0xF2200000)
108
109 #define S5PC100_PA_AC97         0xF2300000
110
111 /* PCM */
112 #define S5PC100_PA_PCM0         0xF2400000
113 #define S5PC100_PA_PCM1         0xF2500000
114
115 #define S5PC100_PA_SPDIF        0xF2600000
116
117 #define S5PC100_PA_TSADC        (0xF3000000)
118
119 /* KEYPAD */
120 #define S5PC100_PA_KEYPAD       (0xF3100000)
121
122 #define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
123
124 #define S5PC100_PA_SDRAM        (0x20000000)
125 #define S5P_PA_SDRAM            S5PC100_PA_SDRAM
126
127 /* compatibiltiy defines. */
128 #define S3C_PA_UART             S5PC100_PA_UART
129 #define S3C_PA_IIC              S5PC100_PA_IIC0
130 #define S3C_PA_IIC1             S5PC100_PA_IIC1
131 #define S3C_PA_FB               S5PC100_PA_FB
132 #define S3C_PA_G2D              S5PC100_PA_G2D
133 #define S3C_PA_G3D              S5PC100_PA_G3D
134 #define S3C_PA_JPEG             S5PC100_PA_JPEG
135 #define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
136 #define S5P_VA_VIC0             S5PC1XX_VA_VIC(0)
137 #define S5P_VA_VIC1             S5PC1XX_VA_VIC(1)
138 #define S5P_VA_VIC2             S5PC1XX_VA_VIC(2)
139 #define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
140 #define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
141 #define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
142 #define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
143 #define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)
144 #define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
145 #define S3C_PA_WDT              S5PC100_PA_WATCHDOG
146 #define S3C_PA_TSADC            S5PC100_PA_TSADC
147 #define S3C_PA_ONENAND          S5PC100_PA_ONENAND
148 #define S3C_PA_ONENAND_BUF      S5PC100_PA_ONENAND_BUF
149 #define S3C_SZ_ONENAND_BUF      S5PC100_SZ_ONENAND_BUF
150 #define S3C_PA_RTC              S5PC100_PA_RTC
151
152 #define SAMSUNG_PA_ADC          S5PC100_PA_TSADC
153 #define SAMSUNG_PA_CFCON        S5PC100_PA_CFCON
154 #define SAMSUNG_PA_KEYPAD       S5PC100_PA_KEYPAD
155
156 #define S5P_PA_FIMC0            S5PC100_PA_FIMC0
157 #define S5P_PA_FIMC1            S5PC100_PA_FIMC1
158 #define S5P_PA_FIMC2            S5PC100_PA_FIMC2
159
160 #endif /* __ASM_ARCH_C100_MAP_H */