arch/arm/mach-s5p64x0/common.c

   1 /*
   2  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for S5P64X0 machines
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/device.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/gpio.h>
  26 #include <linux/irq.h>
  27
  28 #include <asm/irq.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/system_misc.h>
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/map.h>
  33 #include <asm/mach/irq.h>
  34
  35 #include <mach/map.h>
  36 #include <mach/hardware.h>
  37 #include <mach/regs-clock.h>
  38 #include <mach/regs-gpio.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/clock.h>
  42 #include <plat/devs.h>
  43 #include <plat/pm.h>
  44 #include <plat/sdhci.h>
  45 #include <plat/adc-core.h>
  46 #include <plat/fb-core.h>
  47 #include <plat/spi-core.h>
  48 #include <plat/gpio-cfg.h>
  49 #include <plat/regs-irqtype.h>
  50 #include <plat/regs-serial.h>
  51 #include <plat/watchdog-reset.h>
  52
  53 #include "common.h"
  54
  55 static const char name_s5p6440[] = "S5P6440";
  56 static const char name_s5p6450[] = "S5P6450";
  57
  58 static struct cpu_table cpu_ids[] __initdata = {
  59         {
  60                 .idcode         = S5P6440_CPU_ID,
  61                 .idmask         = S5P64XX_CPU_MASK,
  62                 .map_io         = s5p6440_map_io,
  63                 .init_clocks    = s5p6440_init_clocks,
  64                 .init_uarts     = s5p6440_init_uarts,
  65                 .init           = s5p64x0_init,
  66                 .name           = name_s5p6440,
  67         }, {
  68                 .idcode         = S5P6450_CPU_ID,
  69                 .idmask         = S5P64XX_CPU_MASK,
  70                 .map_io         = s5p6450_map_io,
  71                 .init_clocks    = s5p6450_init_clocks,
  72                 .init_uarts     = s5p6450_init_uarts,
  73                 .init           = s5p64x0_init,
  74                 .name           = name_s5p6450,
  75         },
  76 };
  77
  78 /* Initial IO mappings */
  79
  80 static struct map_desc s5p64x0_iodesc[] __initdata = {
  81         {
  82                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  83                 .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
  84                 .length         = SZ_4K,
  85                 .type           = MT_DEVICE,
  86         }, {
  87                 .virtual        = (unsigned long)S3C_VA_SYS,
  88                 .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
  89                 .length         = SZ_64K,
  90                 .type           = MT_DEVICE,
  91         }, {
  92                 .virtual        = (unsigned long)S3C_VA_TIMER,
  93                 .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
  94                 .length         = SZ_16K,
  95                 .type           = MT_DEVICE,
  96         }, {
  97                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  98                 .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
  99                 .length         = SZ_4K,
 100                 .type           = MT_DEVICE,
 101         }, {
 102                 .virtual        = (unsigned long)S5P_VA_SROMC,
 103                 .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
 104                 .length         = SZ_4K,
 105                 .type           = MT_DEVICE,
 106         }, {
 107                 .virtual        = (unsigned long)S5P_VA_GPIO,
 108                 .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
 109                 .length         = SZ_4K,
 110                 .type           = MT_DEVICE,
 111         }, {
 112                 .virtual        = (unsigned long)VA_VIC0,
 113                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
 114                 .length         = SZ_16K,
 115                 .type           = MT_DEVICE,
 116         }, {
 117                 .virtual        = (unsigned long)VA_VIC1,
 118                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
 119                 .length         = SZ_16K,
 120                 .type           = MT_DEVICE,
 121         },
 122 };
 123
 124 static struct map_desc s5p6440_iodesc[] __initdata = {
 125         {
 126                 .virtual        = (unsigned long)S3C_VA_UART,
 127                 .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE,
 130         },
 131 };
 132
 133 static struct map_desc s5p6450_iodesc[] __initdata = {
 134         {
 135                 .virtual        = (unsigned long)S3C_VA_UART,
 136                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
 137                 .length         = SZ_512K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
 141                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
 142                 .length         = SZ_4K,
 143                 .type           = MT_DEVICE,
 144         },
 145 };
 146
 147 static void s5p64x0_idle(void)
 148 {
 149         unsigned long val;
 150
 151         val = __raw_readl(S5P64X0_PWR_CFG);
 152         val &= ~(0x3 << 5);
 153         val |= (0x1 << 5);
 154         __raw_writel(val, S5P64X0_PWR_CFG);
 155
 156         cpu_do_idle();
 157 }
 158
 159 /*
 160  * s5p64x0_map_io
 161  *
 162  * register the standard CPU IO areas
 163  */
 164
 165 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
 166 {
 167         /* initialize the io descriptors we need for initialization */
 168         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
 169         if (mach_desc)
 170                 iotable_init(mach_desc, size);
 171
 172         /* detect cpu id and rev. */
 173         s5p_init_cpu(S5P64X0_SYS_ID);
 174
 175         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 176 }
 177
 178 void __init s5p6440_map_io(void)
 179 {
 180         /* initialize any device information early */
 181         s3c_adc_setname("s3c64xx-adc");
 182         s3c_fb_setname("s5p64x0-fb");
 183         s3c64xx_spi_setname("s5p64x0-spi");
 184
 185         s5p64x0_default_sdhci0();
 186         s5p64x0_default_sdhci1();
 187         s5p6440_default_sdhci2();
 188
 189         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 190         init_consistent_dma_size(SZ_8M);
 191 }
 192
 193 void __init s5p6450_map_io(void)
 194 {
 195         /* initialize any device information early */
 196         s3c_adc_setname("s3c64xx-adc");
 197         s3c_fb_setname("s5p64x0-fb");
 198         s3c64xx_spi_setname("s5p64x0-spi");
 199
 200         s5p64x0_default_sdhci0();
 201         s5p64x0_default_sdhci1();
 202         s5p6450_default_sdhci2();
 203
 204         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 205         init_consistent_dma_size(SZ_8M);
 206 }
 207
 208 /*
 209  * s5p64x0_init_clocks
 210  *
 211  * register and setup the CPU clocks
 212  */
 213
 214 void __init s5p6440_init_clocks(int xtal)
 215 {
 216         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 217
 218         s3c24xx_register_baseclocks(xtal);
 219         s5p_register_clocks(xtal);
 220         s5p6440_register_clocks();
 221         s5p6440_setup_clocks();
 222 }
 223
 224 void __init s5p6450_init_clocks(int xtal)
 225 {
 226         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 227
 228         s3c24xx_register_baseclocks(xtal);
 229         s5p_register_clocks(xtal);
 230         s5p6450_register_clocks();
 231         s5p6450_setup_clocks();
 232 }
 233
 234 /*
 235  * s5p64x0_init_irq
 236  *
 237  * register the CPU interrupts
 238  */
 239
 240 void __init s5p6440_init_irq(void)
 241 {
 242         /* S5P6440 supports 2 VIC */
 243         u32 vic[2];
 244
 245         /*
 246          * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
 247          * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
 248          */
 249         vic[0] = 0xff800ae7;
 250         vic[1] = 0xffbf23e5;
 251
 252         s5p_init_irq(vic, ARRAY_SIZE(vic));
 253 }
 254
 255 void __init s5p6450_init_irq(void)
 256 {
 257         /* S5P6450 supports only 2 VIC */
 258         u32 vic[2];
 259
 260         /*
 261          * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
 262          * VIC1 is missing IRQ VIC1[12, 14, 23]
 263          */
 264         vic[0] = 0xff9f1fff;
 265         vic[1] = 0xff7fafff;
 266
 267         s5p_init_irq(vic, ARRAY_SIZE(vic));
 268 }
 269
 270 struct bus_type s5p64x0_subsys = {
 271         .name           = "s5p64x0-core",
 272         .dev_name       = "s5p64x0-core",
 273 };
 274
 275 static struct device s5p64x0_dev = {
 276         .bus    = &s5p64x0_subsys,
 277 };
 278
 279 static int __init s5p64x0_core_init(void)
 280 {
 281         return subsys_system_register(&s5p64x0_subsys, NULL);
 282 }
 283 core_initcall(s5p64x0_core_init);
 284
 285 int __init s5p64x0_init(void)
 286 {
 287         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 288
 289         /* set idle function */
 290         arm_pm_idle = s5p64x0_idle;
 291
 292         return device_register(&s5p64x0_dev);
 293 }
 294
 295 /* uart registration process */
 296 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 297 {
 298         int uart;
 299
 300         for (uart = 0; uart < no; uart++) {
 301                 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
 302                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
 303         }
 304
 305         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 306 }
 307
 308 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 309 {
 310         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 311 }
 312
 313 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 314
 315 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
 316 {
 317         int offs = eint_offset(data->irq);
 318         int shift;
 319         u32 ctrl, mask;
 320         u32 newvalue = 0;
 321
 322         if (offs > 15)
 323                 return -EINVAL;
 324
 325         switch (type) {
 326         case IRQ_TYPE_NONE:
 327                 printk(KERN_WARNING "No edge setting!\n");
 328                 break;
 329         case IRQ_TYPE_EDGE_RISING:
 330                 newvalue = S3C2410_EXTINT_RISEEDGE;
 331                 break;
 332         case IRQ_TYPE_EDGE_FALLING:
 333                 newvalue = S3C2410_EXTINT_FALLEDGE;
 334                 break;
 335         case IRQ_TYPE_EDGE_BOTH:
 336                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 337                 break;
 338         case IRQ_TYPE_LEVEL_LOW:
 339                 newvalue = S3C2410_EXTINT_LOWLEV;
 340                 break;
 341         case IRQ_TYPE_LEVEL_HIGH:
 342                 newvalue = S3C2410_EXTINT_HILEV;
 343                 break;
 344         default:
 345                 printk(KERN_ERR "No such irq type %d", type);
 346                 return -EINVAL;
 347         }
 348
 349         shift = (offs / 2) * 4;
 350         mask = 0x7 << shift;
 351
 352         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
 353         ctrl |= newvalue << shift;
 354         __raw_writel(ctrl, S5P64X0_EINT0CON0);
 355
 356         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
 357         if (soc_is_s5p6450())
 358                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
 359         else
 360                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
 361
 362         return 0;
 363 }
 364
 365 /*
 366  * s5p64x0_irq_demux_eint
 367  *
 368  * This function demuxes the IRQ from the group0 external interrupts,
 369  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
 370  * the specific handlers s5p64x0_irq_demux_eintX_Y.
 371  */
 372 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
 373 {
 374         u32 status = __raw_readl(S5P64X0_EINT0PEND);
 375         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
 376         unsigned int irq;
 377
 378         status &= ~mask;
 379         status >>= start;
 380         status &= (1 << (end - start + 1)) - 1;
 381
 382         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 383                 if (status & 1)
 384                         generic_handle_irq(irq);
 385                 status >>= 1;
 386         }
 387 }
 388
 389 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 390 {
 391         s5p64x0_irq_demux_eint(0, 3);
 392 }
 393
 394 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 395 {
 396         s5p64x0_irq_demux_eint(4, 11);
 397 }
 398
 399 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 400                                         struct irq_desc *desc)
 401 {
 402         s5p64x0_irq_demux_eint(12, 15);
 403 }
 404
 405 static int s5p64x0_alloc_gc(void)
 406 {
 407         struct irq_chip_generic *gc;
 408         struct irq_chip_type *ct;
 409
 410         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 411                                     S5P_VA_GPIO, handle_level_irq);
 412         if (!gc) {
 413                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 414                         "external interrupts failed\n", __func__);
 415                 return -EINVAL;
 416         }
 417
 418         ct = gc->chip_types;
 419         ct->chip.irq_ack = irq_gc_ack_set_bit;
 420         ct->chip.irq_mask = irq_gc_mask_set_bit;
 421         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 422         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 423         ct->chip.irq_set_wake = s3c_irqext_wake;
 424         ct->regs.ack = EINT0PEND_OFFSET;
 425         ct->regs.mask = EINT0MASK_OFFSET;
 426         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 427                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 428         return 0;
 429 }
 430
 431 static int __init s5p64x0_init_irq_eint(void)
 432 {
 433         int ret = s5p64x0_alloc_gc();
 434         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 435         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 436         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 437
 438         return ret;
 439 }
 440 arch_initcall(s5p64x0_init_irq_eint);
 441
 442 void s5p64x0_restart(char mode, const char *cmd)
 443 {
 444         if (mode != 's')
 445                 arch_wdt_reset();
 446
 447         soft_restart(0);
 448 }