Merge branch 'samsung/cleanup' into next/boards
[linux-2.6.git] / arch / arm / mach-s3c64xx / pm.c
1 /* linux/arch/arm/plat-s3c64xx/pm.c
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *      Ben Dooks <ben@simtec.co.uk>
6  *      http://armlinux.simtec.co.uk/
7  *
8  * S3C64XX CPU PM support.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/suspend.h>
17 #include <linux/serial_core.h>
18 #include <linux/io.h>
19 #include <linux/gpio.h>
20
21 #include <mach/map.h>
22 #include <mach/irqs.h>
23
24 #include <plat/pm.h>
25 #include <plat/wakeup-mask.h>
26
27 #include <mach/regs-sys.h>
28 #include <mach/regs-gpio.h>
29 #include <mach/regs-clock.h>
30 #include <mach/regs-syscon-power.h>
31 #include <mach/regs-gpio-memport.h>
32 #include <mach/regs-modem.h>
33
34 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
35 void s3c_pm_debug_smdkled(u32 set, u32 clear)
36 {
37         unsigned long flags;
38         int i;
39
40         local_irq_save(flags);
41         for (i = 0; i < 4; i++) {
42                 if (clear & (1 << i))
43                         gpio_set_value(S3C64XX_GPN(12 + i), 0);
44                 if (set & (1 << i))
45                         gpio_set_value(S3C64XX_GPN(12 + i), 1);
46         }
47         local_irq_restore(flags);
48 }
49 #endif
50
51 static struct sleep_save core_save[] = {
52         SAVE_ITEM(S3C_APLL_LOCK),
53         SAVE_ITEM(S3C_MPLL_LOCK),
54         SAVE_ITEM(S3C_EPLL_LOCK),
55         SAVE_ITEM(S3C_CLK_SRC),
56         SAVE_ITEM(S3C_CLK_DIV0),
57         SAVE_ITEM(S3C_CLK_DIV1),
58         SAVE_ITEM(S3C_CLK_DIV2),
59         SAVE_ITEM(S3C_CLK_OUT),
60         SAVE_ITEM(S3C_HCLK_GATE),
61         SAVE_ITEM(S3C_PCLK_GATE),
62         SAVE_ITEM(S3C_SCLK_GATE),
63         SAVE_ITEM(S3C_MEM0_GATE),
64
65         SAVE_ITEM(S3C_EPLL_CON1),
66         SAVE_ITEM(S3C_EPLL_CON0),
67
68         SAVE_ITEM(S3C64XX_MEM0DRVCON),
69         SAVE_ITEM(S3C64XX_MEM1DRVCON),
70
71 #ifndef CONFIG_CPU_FREQ
72         SAVE_ITEM(S3C_APLL_CON),
73         SAVE_ITEM(S3C_MPLL_CON),
74 #endif
75 };
76
77 static struct sleep_save misc_save[] = {
78         SAVE_ITEM(S3C64XX_AHB_CON0),
79         SAVE_ITEM(S3C64XX_AHB_CON1),
80         SAVE_ITEM(S3C64XX_AHB_CON2),
81         
82         SAVE_ITEM(S3C64XX_SPCON),
83
84         SAVE_ITEM(S3C64XX_MEM0CONSTOP),
85         SAVE_ITEM(S3C64XX_MEM1CONSTOP),
86         SAVE_ITEM(S3C64XX_MEM0CONSLP0),
87         SAVE_ITEM(S3C64XX_MEM0CONSLP1),
88         SAVE_ITEM(S3C64XX_MEM1CONSLP),
89
90         SAVE_ITEM(S3C64XX_SDMA_SEL),
91         SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
92
93         SAVE_ITEM(S3C64XX_NORMAL_CFG),
94 };
95
96 void s3c_pm_configure_extint(void)
97 {
98         __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
99 }
100
101 void s3c_pm_restore_core(void)
102 {
103         __raw_writel(0, S3C64XX_EINT_MASK);
104
105         s3c_pm_debug_smdkled(1 << 2, 0);
106
107         s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
108         s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
109 }
110
111 void s3c_pm_save_core(void)
112 {
113         s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
114         s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
115 }
116
117 /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
118  * put the per-cpu code in here until any new cpu comes along and changes
119  * this.
120  */
121
122 static int s3c64xx_cpu_suspend(unsigned long arg)
123 {
124         unsigned long tmp;
125
126         /* set our standby method to sleep */
127
128         tmp = __raw_readl(S3C64XX_PWR_CFG);
129         tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
130         tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
131         __raw_writel(tmp, S3C64XX_PWR_CFG);
132
133         /* clear any old wakeup */
134
135         __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
136                      S3C64XX_WAKEUP_STAT);
137
138         /* set the LED state to 0110 over sleep */
139         s3c_pm_debug_smdkled(3 << 1, 0xf);
140
141         /* issue the standby signal into the pm unit. Note, we
142          * issue a write-buffer drain just in case */
143
144         tmp = 0;
145
146         asm("b 1f\n\t"
147             ".align 5\n\t"
148             "1:\n\t"
149             "mcr p15, 0, %0, c7, c10, 5\n\t"
150             "mcr p15, 0, %0, c7, c10, 4\n\t"
151             "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
152
153         /* we should never get past here */
154
155         panic("sleep resumed to originator?");
156 }
157
158 /* mapping of interrupts to parts of the wakeup mask */
159 static struct samsung_wakeup_mask wake_irqs[] = {
160         { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
161         { .irq = IRQ_RTC_TIC,   .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
162         { .irq = IRQ_PENDN,     .bit = S3C64XX_PWRCFG_TS_DISABLE, },
163         { .irq = IRQ_HSMMC0,    .bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
164         { .irq = IRQ_HSMMC1,    .bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
165         { .irq = IRQ_HSMMC2,    .bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
166         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE},
167         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
168         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE },
169         { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE },
170 };
171
172 static void s3c64xx_pm_prepare(void)
173 {
174         samsung_sync_wakemask(S3C64XX_PWR_CFG,
175                               wake_irqs, ARRAY_SIZE(wake_irqs));
176
177         /* store address of resume. */
178         __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0);
179
180         /* ensure previous wakeup state is cleared before sleeping */
181         __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
182 }
183
184 static int s3c64xx_pm_init(void)
185 {
186         u32 val;
187
188         pm_cpu_prep = s3c64xx_pm_prepare;
189         pm_cpu_sleep = s3c64xx_cpu_suspend;
190         pm_uart_udivslot = 1;
191
192         /*
193          * Unconditionally disable power domains that contain only
194          * blocks which have no mainline driver support.
195          */
196         val = __raw_readl(S3C64XX_NORMAL_CFG);
197         val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
198                  S3C64XX_NORMALCFG_DOMAIN_V_ON |
199                  S3C64XX_NORMALCFG_DOMAIN_I_ON |
200                  S3C64XX_NORMALCFG_DOMAIN_P_ON);
201         __raw_writel(val, S3C64XX_NORMAL_CFG);
202
203 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
204         gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
205         gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
206         gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
207         gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
208         gpio_direction_output(S3C64XX_GPN(12), 0);
209         gpio_direction_output(S3C64XX_GPN(13), 0);
210         gpio_direction_output(S3C64XX_GPN(14), 0);
211         gpio_direction_output(S3C64XX_GPN(15), 0);
212 #endif
213
214         return 0;
215 }
216
217 arch_initcall(s3c64xx_pm_init);