Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx
[linux-2.6.git] / arch / arm / mach-s3c64xx / mach-anw6410.c
1 /* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *      Ben Dooks <ben@simtec.co.uk>
6  *      http://armlinux.simtec.co.uk/
7  * Copyright 2009 Kwangwoo Lee
8  *      Kwangwoo Lee <kwangwoo.lee@gmail.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/timer.h>
21 #include <linux/init.h>
22 #include <linux/serial_core.h>
23 #include <linux/platform_device.h>
24 #include <linux/io.h>
25 #include <linux/i2c.h>
26 #include <linux/fb.h>
27 #include <linux/gpio.h>
28 #include <linux/delay.h>
29 #include <linux/dm9000.h>
30
31 #include <video/platform_lcd.h>
32
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/irq.h>
36
37 #include <mach/hardware.h>
38 #include <mach/regs-fb.h>
39 #include <mach/map.h>
40
41 #include <asm/irq.h>
42 #include <asm/mach-types.h>
43
44 #include <plat/regs-serial.h>
45 #include <plat/iic.h>
46 #include <plat/fb.h>
47
48 #include <mach/s3c6410.h>
49 #include <plat/clock.h>
50 #include <plat/devs.h>
51 #include <plat/cpu.h>
52 #include <mach/regs-gpio.h>
53 #include <mach/regs-modem.h>
54
55 /* DM9000 */
56 #define ANW6410_PA_DM9000       (0x18000000)
57
58 /* A hardware buffer to control external devices is mapped at 0x30000000.
59  * It can not be read. So current status must be kept in anw6410_extdev_status.
60  */
61 #define ANW6410_VA_EXTDEV       S3C_ADDR(0x02000000)
62 #define ANW6410_PA_EXTDEV       (0x30000000)
63
64 #define ANW6410_EN_DM9000       (1<<11)
65 #define ANW6410_EN_LCD          (1<<14)
66
67 static __u32 anw6410_extdev_status;
68
69 static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
70         [0] = {
71                 .hwport      = 0,
72                 .flags       = 0,
73                 .ucon        = 0x3c5,
74                 .ulcon       = 0x03,
75                 .ufcon       = 0x51,
76         },
77         [1] = {
78                 .hwport      = 1,
79                 .flags       = 0,
80                 .ucon        = 0x3c5,
81                 .ulcon       = 0x03,
82                 .ufcon       = 0x51,
83         },
84 };
85
86 /* framebuffer and LCD setup. */
87 static void __init anw6410_lcd_mode_set(void)
88 {
89         u32 tmp;
90
91         /* set the LCD type */
92         tmp = __raw_readl(S3C64XX_SPCON);
93         tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
94         tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
95         __raw_writel(tmp, S3C64XX_SPCON);
96
97         /* remove the LCD bypass */
98         tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
99         tmp &= ~MIFPCON_LCD_BYPASS;
100         __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
101 }
102
103 /* GPF1 = LCD panel power
104  * GPF4 = LCD backlight control
105  */
106 static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
107                                    unsigned int power)
108 {
109         if (power) {
110                 anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
111                 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
112
113                 gpio_direction_output(S3C64XX_GPF(1), 1);
114                 gpio_direction_output(S3C64XX_GPF(4), 1);
115         } else {
116                 anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
117                 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
118
119                 gpio_direction_output(S3C64XX_GPF(1), 0);
120                 gpio_direction_output(S3C64XX_GPF(4), 0);
121         }
122 }
123
124 static struct plat_lcd_data anw6410_lcd_power_data = {
125         .set_power      = anw6410_lcd_power_set,
126 };
127
128 static struct platform_device anw6410_lcd_powerdev = {
129         .name                   = "platform-lcd",
130         .dev.parent             = &s3c_device_fb.dev,
131         .dev.platform_data      = &anw6410_lcd_power_data,
132 };
133
134 static struct s3c_fb_pd_win anw6410_fb_win0 = {
135         /* this is to ensure we use win0 */
136         .win_mode       = {
137                 .left_margin    = 8,
138                 .right_margin   = 13,
139                 .upper_margin   = 7,
140                 .lower_margin   = 5,
141                 .hsync_len      = 3,
142                 .vsync_len      = 1,
143                 .xres           = 800,
144                 .yres           = 480,
145         },
146         .max_bpp        = 32,
147         .default_bpp    = 16,
148 };
149
150 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
151 static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
152         .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
153         .win[0]         = &anw6410_fb_win0,
154         .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
155         .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
156 };
157
158 /* DM9000AEP 10/100 ethernet controller */
159 static void __init anw6410_dm9000_enable(void)
160 {
161         anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
162         __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
163 }
164
165 static struct resource anw6410_dm9000_resource[] = {
166         [0] = {
167                 .start = ANW6410_PA_DM9000,
168                 .end   = ANW6410_PA_DM9000 + 3,
169                 .flags = IORESOURCE_MEM,
170         },
171         [1] = {
172                 .start = ANW6410_PA_DM9000 + 4,
173                 .end   = ANW6410_PA_DM9000 + 4 + 500,
174                 .flags = IORESOURCE_MEM,
175         },
176         [2] = {
177                 .start = IRQ_EINT(15),
178                 .end   = IRQ_EINT(15),
179                 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
180         },
181 };
182
183 static struct dm9000_plat_data anw6410_dm9000_pdata = {
184         .flags    = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
185         /* dev_addr can be set to provide hwaddr. */
186 };
187
188 static struct platform_device anw6410_device_eth = {
189         .name   = "dm9000",
190         .id     = -1,
191         .num_resources  = ARRAY_SIZE(anw6410_dm9000_resource),
192         .resource       = anw6410_dm9000_resource,
193         .dev    = {
194                 .platform_data  = &anw6410_dm9000_pdata,
195         },
196 };
197
198 static struct map_desc anw6410_iodesc[] __initdata = {
199         {
200                 .virtual        = (unsigned long)ANW6410_VA_EXTDEV,
201                 .pfn            = __phys_to_pfn(ANW6410_PA_EXTDEV),
202                 .length         = SZ_64K,
203                 .type           = MT_DEVICE,
204         },
205 };
206
207 static struct platform_device *anw6410_devices[] __initdata = {
208         &s3c_device_fb,
209         &anw6410_lcd_powerdev,
210         &anw6410_device_eth,
211 };
212
213 static void __init anw6410_map_io(void)
214 {
215         s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
216         s3c24xx_init_clocks(12000000);
217         s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
218
219         anw6410_lcd_mode_set();
220 }
221
222 static void __init anw6410_machine_init(void)
223 {
224         s3c_fb_set_platdata(&anw6410_lcd_pdata);
225
226         gpio_request(S3C64XX_GPF(1), "panel power");
227         gpio_request(S3C64XX_GPF(4), "LCD backlight");
228
229         anw6410_dm9000_enable();
230
231         platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
232 }
233
234 MACHINE_START(ANW6410, "A&W6410")
235         /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
236         .boot_params    = S3C64XX_PA_SDRAM + 0x100,
237
238         .init_irq       = s3c6410_init_irq,
239         .map_io         = anw6410_map_io,
240         .init_machine   = anw6410_machine_init,
241         .timer          = &s3c24xx_timer,
242 MACHINE_END