2a58a4d5aa5ae44e196c59acb8838e851defe4a3
[linux-2.6.git] / arch / arm / mach-s3c2443 / dma.c
1 /* linux/arch/arm/mach-s3c2443/dma.c
2  *
3  * Copyright (c) 2007 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C2443 DMA selection
7  *
8  * http://armlinux.simtec.co.uk/
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/sysdev.h>
18 #include <linux/serial_core.h>
19 #include <linux/io.h>
20
21 #include <mach/dma.h>
22
23 #include <plat/dma.h>
24 #include <plat/cpu.h>
25
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <mach/regs-mem.h>
30 #include <mach/regs-lcd.h>
31 #include <mach/regs-sdi.h>
32 #include <asm/plat-s3c24xx/regs-iis.h>
33 #include <plat/regs-spi.h>
34
35 #define MAP(x) { \
36                 [0]     = (x) | DMA_CH_VALID,   \
37                 [1]     = (x) | DMA_CH_VALID,   \
38                 [2]     = (x) | DMA_CH_VALID,   \
39                 [3]     = (x) | DMA_CH_VALID,   \
40                 [4]     = (x) | DMA_CH_VALID,   \
41                 [5]     = (x) | DMA_CH_VALID,   \
42         }
43
44 static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
45         [DMACH_XD0] = {
46                 .name           = "xdreq0",
47                 .channels       = MAP(S3C2443_DMAREQSEL_XDREQ0),
48         },
49         [DMACH_XD1] = {
50                 .name           = "xdreq1",
51                 .channels       = MAP(S3C2443_DMAREQSEL_XDREQ1),
52         },
53         [DMACH_SDI] = {
54                 .name           = "sdi",
55                 .channels       = MAP(S3C2443_DMAREQSEL_SDI),
56                 .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
57                 .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
58         },
59         [DMACH_SPI0] = {
60                 .name           = "spi0",
61                 .channels       = MAP(S3C2443_DMAREQSEL_SPI0TX),
62                 .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
63                 .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
64         },
65         [DMACH_SPI1] = {
66                 .name           = "spi1",
67                 .channels       = MAP(S3C2443_DMAREQSEL_SPI1TX),
68                 .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
69                 .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
70         },
71         [DMACH_UART0] = {
72                 .name           = "uart0",
73                 .channels       = MAP(S3C2443_DMAREQSEL_UART0_0),
74                 .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
75                 .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
76         },
77         [DMACH_UART1] = {
78                 .name           = "uart1",
79                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_0),
80                 .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
81                 .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
82         },
83         [DMACH_UART2] = {
84                 .name           = "uart2",
85                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_0),
86                 .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
87                 .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
88         },
89         [DMACH_UART3] = {
90                 .name           = "uart3",
91                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_0),
92                 .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
93                 .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
94         },
95         [DMACH_UART0_SRC2] = {
96                 .name           = "uart0",
97                 .channels       = MAP(S3C2443_DMAREQSEL_UART0_1),
98                 .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
99                 .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
100         },
101         [DMACH_UART1_SRC2] = {
102                 .name           = "uart1",
103                 .channels       = MAP(S3C2443_DMAREQSEL_UART1_1),
104                 .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
105                 .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
106         },
107         [DMACH_UART2_SRC2] = {
108                 .name           = "uart2",
109                 .channels       = MAP(S3C2443_DMAREQSEL_UART2_1),
110                 .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
111                 .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
112         },
113         [DMACH_UART3_SRC2] = {
114                 .name           = "uart3",
115                 .channels       = MAP(S3C2443_DMAREQSEL_UART3_1),
116                 .hw_addr.to     = S3C2443_PA_UART3 + S3C2410_UTXH,
117                 .hw_addr.from   = S3C2443_PA_UART3 + S3C2410_URXH,
118         },
119         [DMACH_TIMER] = {
120                 .name           = "timer",
121                 .channels       = MAP(S3C2443_DMAREQSEL_TIMER),
122         },
123         [DMACH_I2S_IN] = {
124                 .name           = "i2s-sdi",
125                 .channels       = MAP(S3C2443_DMAREQSEL_I2SRX),
126                 .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
127         },
128         [DMACH_I2S_OUT] = {
129                 .name           = "i2s-sdo",
130                 .channels       = MAP(S3C2443_DMAREQSEL_I2STX),
131                 .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
132         },
133         [DMACH_PCM_IN] = {
134                 .name           = "pcm-in",
135                 .channels       = MAP(S3C2443_DMAREQSEL_PCMIN),
136                 .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
137         },
138         [DMACH_PCM_OUT] = {
139                 .name           = "pcm-out",
140                 .channels       = MAP(S3C2443_DMAREQSEL_PCMOUT),
141                 .hw_addr.to     = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
142         },
143         [DMACH_MIC_IN] = {
144                 .name           = "mic-in",
145                 .channels       = MAP(S3C2443_DMAREQSEL_MICIN),
146                 .hw_addr.from   = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
147         },
148 };
149
150 static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
151                                struct s3c24xx_dma_map *map)
152 {
153         writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
154                chan->regs + S3C2443_DMA_DMAREQSEL);
155 }
156
157 static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
158         .select         = s3c2443_dma_select,
159         .dcon_mask      = 0,
160         .map            = s3c2443_dma_mappings,
161         .map_size       = ARRAY_SIZE(s3c2443_dma_mappings),
162 };
163
164 static int __init s3c2443_dma_add(struct sys_device *sysdev)
165 {
166         s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
167         return s3c24xx_dma_init_map(&s3c2443_dma_sel);
168 }
169
170 static struct sysdev_driver s3c2443_dma_driver = {
171         .add    = s3c2443_dma_add,
172 };
173
174 static int __init s3c2443_dma_init(void)
175 {
176         return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver);
177 }
178
179 arch_initcall(s3c2443_dma_init);