[ARM] 4325/1: S3C24XX: remove s3c24xx_board
[linux-2.6.git] / arch / arm / mach-s3c2440 / mach-rx3715.c
1 /* linux/arch/arm/mach-s3c2440/mach-rx3715.c
2  *
3  * Copyright (c) 2003,2004 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * http://www.handhelds.org/projects/rx3715.html
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/interrupt.h>
17 #include <linux/list.h>
18 #include <linux/timer.h>
19 #include <linux/init.h>
20 #include <linux/tty.h>
21 #include <linux/console.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial_core.h>
24 #include <linux/serial.h>
25
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/mtd/partitions.h>
30
31 #include <asm/mach/arch.h>
32 #include <asm/mach/map.h>
33 #include <asm/mach/irq.h>
34
35 #include <asm/hardware.h>
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 #include <asm/mach-types.h>
39
40 #include <asm/arch/regs-serial.h>
41 #include <asm/arch/regs-gpio.h>
42 #include <asm/arch/regs-lcd.h>
43
44 #include <asm/arch/h1940.h>
45 #include <asm/arch/nand.h>
46 #include <asm/arch/fb.h>
47
48 #include <asm/plat-s3c24xx/clock.h>
49 #include <asm/plat-s3c24xx/devs.h>
50 #include <asm/plat-s3c24xx/cpu.h>
51 #include <asm/plat-s3c24xx/pm.h>
52
53 static struct map_desc rx3715_iodesc[] __initdata = {
54         /* dump ISA space somewhere unused */
55
56         {
57                 .virtual        = (u32)S3C24XX_VA_ISA_WORD,
58                 .pfn            = __phys_to_pfn(S3C2410_CS3),
59                 .length         = SZ_1M,
60                 .type           = MT_DEVICE,
61         }, {
62                 .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
63                 .pfn            = __phys_to_pfn(S3C2410_CS3),
64                 .length         = SZ_1M,
65                 .type           = MT_DEVICE,
66         },
67 };
68
69
70 static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
71         [0] = {
72                 .name           = "fclk",
73                 .divisor        = 0,
74                 .min_baud       = 0,
75                 .max_baud       = 0,
76         }
77 };
78
79 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
80         [0] = {
81                 .hwport      = 0,
82                 .flags       = 0,
83                 .ucon        = 0x3c5,
84                 .ulcon       = 0x03,
85                 .ufcon       = 0x51,
86                 .clocks      = rx3715_serial_clocks,
87                 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
88         },
89         [1] = {
90                 .hwport      = 1,
91                 .flags       = 0,
92                 .ucon        = 0x3c5,
93                 .ulcon       = 0x03,
94                 .ufcon       = 0x00,
95                 .clocks      = rx3715_serial_clocks,
96                 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
97         },
98         /* IR port */
99         [2] = {
100                 .hwport      = 2,
101                 .uart_flags  = UPF_CONS_FLOW,
102                 .ucon        = 0x3c5,
103                 .ulcon       = 0x43,
104                 .ufcon       = 0x51,
105                 .clocks      = rx3715_serial_clocks,
106                 .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
107         }
108 };
109
110 /* framebuffer lcd controller information */
111
112 static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = {
113         .regs   = {
114                 .lcdcon1 =      S3C2410_LCDCON1_TFT16BPP | \
115                                 S3C2410_LCDCON1_TFT | \
116                                 S3C2410_LCDCON1_CLKVAL(0x0C),
117
118                 .lcdcon2 =      S3C2410_LCDCON2_VBPD(5) | \
119                                 S3C2410_LCDCON2_LINEVAL(319) | \
120                                 S3C2410_LCDCON2_VFPD(6) | \
121                                 S3C2410_LCDCON2_VSPW(2),
122
123                 .lcdcon3 =      S3C2410_LCDCON3_HBPD(35) | \
124                                 S3C2410_LCDCON3_HOZVAL(239) | \
125                                 S3C2410_LCDCON3_HFPD(35),
126
127                 .lcdcon4 =      S3C2410_LCDCON4_MVAL(0) | \
128                                 S3C2410_LCDCON4_HSPW(7),
129
130                 .lcdcon5 =      S3C2410_LCDCON5_INVVLINE |
131                                 S3C2410_LCDCON5_FRM565 |
132                                 S3C2410_LCDCON5_HWSWP,
133         },
134
135         .lpcsel =       0xf82,
136
137         .gpccon =       0xaa955699,
138         .gpccon_mask =  0xffc003cc,
139         .gpcup =        0x0000ffff,
140         .gpcup_mask =   0xffffffff,
141
142         .gpdcon =       0xaa95aaa1,
143         .gpdcon_mask =  0xffc0fff0,
144         .gpdup =        0x0000faff,
145         .gpdup_mask =   0xffffffff,
146
147         .fixed_syncs =  1,
148         .width  =       240,
149         .height =       320,
150
151         .xres   = {
152                 .min =          240,
153                 .max =          240,
154                 .defval =       240,
155         },
156
157         .yres   = {
158                 .max =          320,
159                 .min =          320,
160                 .defval =       320,
161         },
162
163         .bpp    = {
164                 .min =          16,
165                 .max =          16,
166                 .defval =       16,
167         },
168 };
169
170 static struct mtd_partition rx3715_nand_part[] = {
171         [0] = {
172                 .name           = "Whole Flash",
173                 .offset         = 0,
174                 .size           = MTDPART_SIZ_FULL,
175                 .mask_flags     = MTD_WRITEABLE,
176         }
177 };
178
179 static struct s3c2410_nand_set rx3715_nand_sets[] = {
180         [0] = {
181                 .name           = "Internal",
182                 .nr_chips       = 1,
183                 .nr_partitions  = ARRAY_SIZE(rx3715_nand_part),
184                 .partitions     = rx3715_nand_part,
185         },
186 };
187
188 static struct s3c2410_platform_nand rx3715_nand_info = {
189         .tacls          = 25,
190         .twrph0         = 50,
191         .twrph1         = 15,
192         .nr_sets        = ARRAY_SIZE(rx3715_nand_sets),
193         .sets           = rx3715_nand_sets,
194 };
195
196 static struct platform_device *rx3715_devices[] __initdata = {
197         &s3c_device_usb,
198         &s3c_device_lcd,
199         &s3c_device_wdt,
200         &s3c_device_i2c,
201         &s3c_device_iis,
202         &s3c_device_nand,
203 };
204
205 static void __init rx3715_map_io(void)
206 {
207         s3c_device_nand.dev.platform_data = &rx3715_nand_info;
208
209         s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
210         s3c24xx_init_clocks(16934000);
211         s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
212 }
213
214 static void __init rx3715_init_irq(void)
215 {
216         s3c24xx_init_irq();
217 }
218
219 static void __init rx3715_init_machine(void)
220 {
221 #ifdef CONFIG_PM_H1940
222         memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024);
223 #endif
224         s3c2410_pm_init();
225
226         s3c24xx_fb_set_platdata(&rx3715_lcdcfg);
227         platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices));
228 }
229
230 MACHINE_START(RX3715, "IPAQ-RX3715")
231         /* Maintainer: Ben Dooks <ben@fluff.org> */
232         .phys_io        = S3C2410_PA_UART,
233         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
234         .boot_params    = S3C2410_SDRAM_PA + 0x100,
235         .map_io         = rx3715_map_io,
236         .init_irq       = rx3715_init_irq,
237         .init_machine   = rx3715_init_machine,
238         .timer          = &s3c24xx_timer,
239 MACHINE_END