[ARM] S3C: Move nand headers to arch/arm/plat-s3c/include/plat
[linux-2.6.git] / arch / arm / mach-s3c2410 / mach-bast.c
1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2  *
3  * Copyright (c) 2003-2005,2008 Simtec Electronics
4  *   Ben Dooks <ben@simtec.co.uk>
5  *
6  * http://www.simtec.co.uk/products/EB2410ITX/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/sysdev.h>
20 #include <linux/serial_core.h>
21 #include <linux/platform_device.h>
22 #include <linux/dm9000.h>
23 #include <linux/ata_platform.h>
24 #include <linux/i2c.h>
25 #include <linux/io.h>
26
27 #include <net/ax88796.h>
28
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 #include <asm/mach/irq.h>
32
33 #include <mach/bast-map.h>
34 #include <mach/bast-irq.h>
35 #include <mach/bast-cpld.h>
36
37 #include <mach/hardware.h>
38 #include <asm/irq.h>
39 #include <asm/mach-types.h>
40
41 //#include <asm/debug-ll.h>
42 #include <plat/regs-serial.h>
43 #include <mach/regs-gpio.h>
44 #include <mach/regs-mem.h>
45 #include <mach/regs-lcd.h>
46
47 #include <plat/nand.h>
48 #include <plat/iic.h>
49 #include <mach/fb.h>
50
51 #include <linux/mtd/mtd.h>
52 #include <linux/mtd/nand.h>
53 #include <linux/mtd/nand_ecc.h>
54 #include <linux/mtd/partitions.h>
55
56 #include <linux/serial_8250.h>
57
58 #include <plat/clock.h>
59 #include <plat/devs.h>
60 #include <plat/cpu.h>
61
62 #include "usb-simtec.h"
63 #include "nor-simtec.h"
64
65 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
66
67 /* macros for virtual address mods for the io space entries */
68 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
69 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
70 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
71 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
72
73 /* macros to modify the physical addresses for io space */
74
75 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
76 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
77 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
78 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
79
80 static struct map_desc bast_iodesc[] __initdata = {
81   /* ISA IO areas */
82   {
83           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
84           .pfn          = PA_CS2(BAST_PA_ISAIO),
85           .length       = SZ_16M,
86           .type         = MT_DEVICE,
87   }, {
88           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
89           .pfn          = PA_CS3(BAST_PA_ISAIO),
90           .length       = SZ_16M,
91           .type         = MT_DEVICE,
92   },
93   /* bast CPLD control registers, and external interrupt controls */
94   {
95           .virtual      = (u32)BAST_VA_CTRL1,
96           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
97           .length       = SZ_1M,
98           .type         = MT_DEVICE,
99   }, {
100           .virtual      = (u32)BAST_VA_CTRL2,
101           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
102           .length       = SZ_1M,
103           .type         = MT_DEVICE,
104   }, {
105           .virtual      = (u32)BAST_VA_CTRL3,
106           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
107           .length       = SZ_1M,
108           .type         = MT_DEVICE,
109   }, {
110           .virtual      = (u32)BAST_VA_CTRL4,
111           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
112           .length       = SZ_1M,
113           .type         = MT_DEVICE,
114   },
115   /* PC104 IRQ mux */
116   {
117           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
118           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
119           .length       = SZ_1M,
120           .type         = MT_DEVICE,
121   }, {
122           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
123           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
124           .length       = SZ_1M,
125           .type         = MT_DEVICE,
126   }, {
127           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
128           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
129           .length       = SZ_1M,
130           .type         = MT_DEVICE,
131   },
132
133   /* peripheral space... one for each of fast/slow/byte/16bit */
134   /* note, ide is only decoded in word space, even though some registers
135    * are only 8bit */
136
137   /* slow, byte */
138   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
139   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
140   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
141
142   /* slow, word */
143   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
144   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
145   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
146
147   /* fast, byte */
148   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
149   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
150   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
151
152   /* fast, word */
153   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
154   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
155   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
156 };
157
158 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
159 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
160 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
161
162 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
163         [0] = {
164                 .name           = "uclk",
165                 .divisor        = 1,
166                 .min_baud       = 0,
167                 .max_baud       = 0,
168         },
169         [1] = {
170                 .name           = "pclk",
171                 .divisor        = 1,
172                 .min_baud       = 0,
173                 .max_baud       = 0,
174         }
175 };
176
177
178 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
179         [0] = {
180                 .hwport      = 0,
181                 .flags       = 0,
182                 .ucon        = UCON,
183                 .ulcon       = ULCON,
184                 .ufcon       = UFCON,
185                 .clocks      = bast_serial_clocks,
186                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
187         },
188         [1] = {
189                 .hwport      = 1,
190                 .flags       = 0,
191                 .ucon        = UCON,
192                 .ulcon       = ULCON,
193                 .ufcon       = UFCON,
194                 .clocks      = bast_serial_clocks,
195                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
196         },
197         /* port 2 is not actually used */
198         [2] = {
199                 .hwport      = 2,
200                 .flags       = 0,
201                 .ucon        = UCON,
202                 .ulcon       = ULCON,
203                 .ufcon       = UFCON,
204                 .clocks      = bast_serial_clocks,
205                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
206         }
207 };
208
209 /* NAND Flash on BAST board */
210
211 #ifdef CONFIG_PM
212 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
213 {
214         /* ensure that an nRESET is not generated on resume. */
215         s3c2410_gpio_setpin(S3C2410_GPA21, 1);
216         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
217
218         return 0;
219 }
220
221 static int bast_pm_resume(struct sys_device *sd)
222 {
223         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
224         return 0;
225 }
226
227 #else
228 #define bast_pm_suspend NULL
229 #define bast_pm_resume NULL
230 #endif
231
232 static struct sysdev_class bast_pm_sysclass = {
233         .name           = "mach-bast",
234         .suspend        = bast_pm_suspend,
235         .resume         = bast_pm_resume,
236 };
237
238 static struct sys_device bast_pm_sysdev = {
239         .cls            = &bast_pm_sysclass,
240 };
241
242 static int smartmedia_map[] = { 0 };
243 static int chip0_map[] = { 1 };
244 static int chip1_map[] = { 2 };
245 static int chip2_map[] = { 3 };
246
247 static struct mtd_partition bast_default_nand_part[] = {
248         [0] = {
249                 .name   = "Boot Agent",
250                 .size   = SZ_16K,
251                 .offset = 0,
252         },
253         [1] = {
254                 .name   = "/boot",
255                 .size   = SZ_4M - SZ_16K,
256                 .offset = SZ_16K,
257         },
258         [2] = {
259                 .name   = "user",
260                 .offset = SZ_4M,
261                 .size   = MTDPART_SIZ_FULL,
262         }
263 };
264
265 /* the bast has 4 selectable slots for nand-flash, the three
266  * on-board chip areas, as well as the external SmartMedia
267  * slot.
268  *
269  * Note, there is no current hot-plug support for the SmartMedia
270  * socket.
271 */
272
273 static struct s3c2410_nand_set bast_nand_sets[] = {
274         [0] = {
275                 .name           = "SmartMedia",
276                 .nr_chips       = 1,
277                 .nr_map         = smartmedia_map,
278                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
279                 .partitions     = bast_default_nand_part,
280         },
281         [1] = {
282                 .name           = "chip0",
283                 .nr_chips       = 1,
284                 .nr_map         = chip0_map,
285                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
286                 .partitions     = bast_default_nand_part,
287         },
288         [2] = {
289                 .name           = "chip1",
290                 .nr_chips       = 1,
291                 .nr_map         = chip1_map,
292                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
293                 .partitions     = bast_default_nand_part,
294         },
295         [3] = {
296                 .name           = "chip2",
297                 .nr_chips       = 1,
298                 .nr_map         = chip2_map,
299                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
300                 .partitions     = bast_default_nand_part,
301         }
302 };
303
304 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
305 {
306         unsigned int tmp;
307
308         slot = set->nr_map[slot] & 3;
309
310         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
311                  slot, set, set->nr_map);
312
313         tmp = __raw_readb(BAST_VA_CTRL2);
314         tmp &= BAST_CPLD_CTLR2_IDERST;
315         tmp |= slot;
316         tmp |= BAST_CPLD_CTRL2_WNAND;
317
318         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
319
320         __raw_writeb(tmp, BAST_VA_CTRL2);
321 }
322
323 static struct s3c2410_platform_nand bast_nand_info = {
324         .tacls          = 30,
325         .twrph0         = 60,
326         .twrph1         = 60,
327         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
328         .sets           = bast_nand_sets,
329         .select_chip    = bast_nand_select,
330 };
331
332 /* DM9000 */
333
334 static struct resource bast_dm9k_resource[] = {
335         [0] = {
336                 .start = S3C2410_CS5 + BAST_PA_DM9000,
337                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
338                 .flags = IORESOURCE_MEM,
339         },
340         [1] = {
341                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
342                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
343                 .flags = IORESOURCE_MEM,
344         },
345         [2] = {
346                 .start = IRQ_DM9000,
347                 .end   = IRQ_DM9000,
348                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
349         }
350
351 };
352
353 /* for the moment we limit ourselves to 16bit IO until some
354  * better IO routines can be written and tested
355 */
356
357 static struct dm9000_plat_data bast_dm9k_platdata = {
358         .flags          = DM9000_PLATF_16BITONLY,
359 };
360
361 static struct platform_device bast_device_dm9k = {
362         .name           = "dm9000",
363         .id             = 0,
364         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
365         .resource       = bast_dm9k_resource,
366         .dev            = {
367                 .platform_data = &bast_dm9k_platdata,
368         }
369 };
370
371 /* serial devices */
372
373 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
374 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
375 #define SERIAL_CLK   (1843200)
376
377 static struct plat_serial8250_port bast_sio_data[] = {
378         [0] = {
379                 .mapbase        = SERIAL_BASE + 0x2f8,
380                 .irq            = IRQ_PCSERIAL1,
381                 .flags          = SERIAL_FLAGS,
382                 .iotype         = UPIO_MEM,
383                 .regshift       = 0,
384                 .uartclk        = SERIAL_CLK,
385         },
386         [1] = {
387                 .mapbase        = SERIAL_BASE + 0x3f8,
388                 .irq            = IRQ_PCSERIAL2,
389                 .flags          = SERIAL_FLAGS,
390                 .iotype         = UPIO_MEM,
391                 .regshift       = 0,
392                 .uartclk        = SERIAL_CLK,
393         },
394         { }
395 };
396
397 static struct platform_device bast_sio = {
398         .name                   = "serial8250",
399         .id                     = PLAT8250_DEV_PLATFORM,
400         .dev                    = {
401                 .platform_data  = &bast_sio_data,
402         },
403 };
404
405 /* we have devices on the bus which cannot work much over the
406  * standard 100KHz i2c bus frequency
407 */
408
409 static struct s3c2410_platform_i2c bast_i2c_info = {
410         .flags          = 0,
411         .slave_addr     = 0x10,
412         .bus_freq       = 100*1000,
413         .max_freq       = 130*1000,
414 };
415
416 /* Asix AX88796 10/100 ethernet controller */
417
418 static struct ax_plat_data bast_asix_platdata = {
419         .flags          = AXFLG_MAC_FROMDEV,
420         .wordlength     = 2,
421         .dcr_val        = 0x48,
422         .rcr_val        = 0x40,
423 };
424
425 static struct resource bast_asix_resource[] = {
426         [0] = {
427                 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
428                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
429                 .flags = IORESOURCE_MEM,
430         },
431         [1] = {
432                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
433                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
434                 .flags = IORESOURCE_MEM,
435         },
436         [2] = {
437                 .start = IRQ_ASIX,
438                 .end   = IRQ_ASIX,
439                 .flags = IORESOURCE_IRQ
440         }
441 };
442
443 static struct platform_device bast_device_asix = {
444         .name           = "ax88796",
445         .id             = 0,
446         .num_resources  = ARRAY_SIZE(bast_asix_resource),
447         .resource       = bast_asix_resource,
448         .dev            = {
449                 .platform_data = &bast_asix_platdata
450         }
451 };
452
453 /* Asix AX88796 10/100 ethernet controller parallel port */
454
455 static struct resource bast_asixpp_resource[] = {
456         [0] = {
457                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
458                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
459                 .flags = IORESOURCE_MEM,
460         }
461 };
462
463 static struct platform_device bast_device_axpp = {
464         .name           = "ax88796-pp",
465         .id             = 0,
466         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
467         .resource       = bast_asixpp_resource,
468 };
469
470 /* LCD/VGA controller */
471
472 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
473         {
474                 .type           = S3C2410_LCDCON1_TFT,
475                 .width          = 640,
476                 .height         = 480,
477
478                 .pixclock       = 33333,
479                 .xres           = 640,
480                 .yres           = 480,
481                 .bpp            = 4,
482                 .left_margin    = 40,
483                 .right_margin   = 20,
484                 .hsync_len      = 88,
485                 .upper_margin   = 30,
486                 .lower_margin   = 32,
487                 .vsync_len      = 3,
488
489                 .lcdcon5        = 0x00014b02,
490         },
491         {
492                 .type           = S3C2410_LCDCON1_TFT,
493                 .width          = 640,
494                 .height         = 480,
495
496                 .pixclock       = 33333,
497                 .xres           = 640,
498                 .yres           = 480,
499                 .bpp            = 8,
500                 .left_margin    = 40,
501                 .right_margin   = 20,
502                 .hsync_len      = 88,
503                 .upper_margin   = 30,
504                 .lower_margin   = 32,
505                 .vsync_len      = 3,
506
507                 .lcdcon5        = 0x00014b02,
508         },
509         {
510                 .type           = S3C2410_LCDCON1_TFT,
511                 .width          = 640,
512                 .height         = 480,
513
514                 .pixclock       = 33333,
515                 .xres           = 640,
516                 .yres           = 480,
517                 .bpp            = 16,
518                 .left_margin    = 40,
519                 .right_margin   = 20,
520                 .hsync_len      = 88,
521                 .upper_margin   = 30,
522                 .lower_margin   = 32,
523                 .vsync_len      = 3,
524
525                 .lcdcon5        = 0x00014b02,
526         },
527 };
528
529 /* LCD/VGA controller */
530
531 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
532
533         .displays = bast_lcd_info,
534         .num_displays = ARRAY_SIZE(bast_lcd_info),
535         .default_display = 1,
536 };
537
538 /* I2C devices fitted. */
539
540 static struct i2c_board_info bast_i2c_devs[] __initdata = {
541         {
542                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
543         }, {
544                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
545         }, {
546                 I2C_BOARD_INFO("ch7013", 0x75),
547         },
548 };
549
550 /* Standard BAST devices */
551
552 static struct platform_device *bast_devices[] __initdata = {
553         &s3c_device_usb,
554         &s3c_device_lcd,
555         &s3c_device_wdt,
556         &s3c_device_i2c,
557         &s3c_device_rtc,
558         &s3c_device_nand,
559         &bast_device_dm9k,
560         &bast_device_asix,
561         &bast_device_axpp,
562         &bast_sio,
563 };
564
565 static struct clk *bast_clocks[] __initdata = {
566         &s3c24xx_dclk0,
567         &s3c24xx_dclk1,
568         &s3c24xx_clkout0,
569         &s3c24xx_clkout1,
570         &s3c24xx_uclk,
571 };
572
573 static void __init bast_map_io(void)
574 {
575         /* initialise the clocks */
576
577         s3c24xx_dclk0.parent = &clk_upll;
578         s3c24xx_dclk0.rate   = 12*1000*1000;
579
580         s3c24xx_dclk1.parent = &clk_upll;
581         s3c24xx_dclk1.rate   = 24*1000*1000;
582
583         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
584         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
585
586         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
587
588         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
589
590         s3c_device_nand.dev.platform_data = &bast_nand_info;
591         s3c_device_i2c.dev.platform_data = &bast_i2c_info;
592
593         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
594         s3c24xx_init_clocks(0);
595         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
596
597         usb_simtec_init();
598 }
599
600 static void __init bast_init(void)
601 {
602         sysdev_class_register(&bast_pm_sysclass);
603         sysdev_register(&bast_pm_sysdev);
604
605         s3c24xx_fb_set_platdata(&bast_fb_info);
606         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
607
608         i2c_register_board_info(0, bast_i2c_devs,
609                                 ARRAY_SIZE(bast_i2c_devs));
610
611         nor_simtec_init();
612 }
613
614 MACHINE_START(BAST, "Simtec-BAST")
615         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
616         .phys_io        = S3C2410_PA_UART,
617         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
618         .boot_params    = S3C2410_SDRAM_PA + 0x100,
619         .map_io         = bast_map_io,
620         .init_irq       = s3c24xx_init_irq,
621         .init_machine   = bast_init,
622         .timer          = &s3c24xx_timer,
623 MACHINE_END