sh: Convert sh to use read/update_persistent_clock
[linux-2.6.git] / arch / arm / mach-s3c2410 / mach-bast.c
1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2  *
3  * Copyright 2003-2008 Simtec Electronics
4  *   Ben Dooks <ben@simtec.co.uk>
5  *
6  * http://www.simtec.co.uk/products/EB2410ITX/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/gpio.h>
20 #include <linux/sysdev.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/dm9000.h>
24 #include <linux/ata_platform.h>
25 #include <linux/i2c.h>
26 #include <linux/io.h>
27
28 #include <net/ax88796.h>
29
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
33
34 #include <mach/bast-map.h>
35 #include <mach/bast-irq.h>
36 #include <mach/bast-cpld.h>
37
38 #include <mach/hardware.h>
39 #include <asm/irq.h>
40 #include <asm/mach-types.h>
41
42 //#include <asm/debug-ll.h>
43 #include <plat/regs-serial.h>
44 #include <mach/regs-gpio.h>
45 #include <mach/regs-mem.h>
46 #include <mach/regs-lcd.h>
47
48 #include <plat/hwmon.h>
49 #include <plat/nand.h>
50 #include <plat/iic.h>
51 #include <mach/fb.h>
52
53 #include <linux/mtd/mtd.h>
54 #include <linux/mtd/nand.h>
55 #include <linux/mtd/nand_ecc.h>
56 #include <linux/mtd/partitions.h>
57
58 #include <linux/serial_8250.h>
59
60 #include <plat/clock.h>
61 #include <plat/devs.h>
62 #include <plat/cpu.h>
63 #include <plat/cpu-freq.h>
64 #include <plat/audio-simtec.h>
65
66 #include "usb-simtec.h"
67 #include "nor-simtec.h"
68
69 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
70
71 /* macros for virtual address mods for the io space entries */
72 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
73 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
74 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
75 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
76
77 /* macros to modify the physical addresses for io space */
78
79 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
80 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
81 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
82 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
83
84 static struct map_desc bast_iodesc[] __initdata = {
85   /* ISA IO areas */
86   {
87           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
88           .pfn          = PA_CS2(BAST_PA_ISAIO),
89           .length       = SZ_16M,
90           .type         = MT_DEVICE,
91   }, {
92           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
93           .pfn          = PA_CS3(BAST_PA_ISAIO),
94           .length       = SZ_16M,
95           .type         = MT_DEVICE,
96   },
97   /* bast CPLD control registers, and external interrupt controls */
98   {
99           .virtual      = (u32)BAST_VA_CTRL1,
100           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
101           .length       = SZ_1M,
102           .type         = MT_DEVICE,
103   }, {
104           .virtual      = (u32)BAST_VA_CTRL2,
105           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
106           .length       = SZ_1M,
107           .type         = MT_DEVICE,
108   }, {
109           .virtual      = (u32)BAST_VA_CTRL3,
110           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
111           .length       = SZ_1M,
112           .type         = MT_DEVICE,
113   }, {
114           .virtual      = (u32)BAST_VA_CTRL4,
115           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
116           .length       = SZ_1M,
117           .type         = MT_DEVICE,
118   },
119   /* PC104 IRQ mux */
120   {
121           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
122           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
123           .length       = SZ_1M,
124           .type         = MT_DEVICE,
125   }, {
126           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
127           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
128           .length       = SZ_1M,
129           .type         = MT_DEVICE,
130   }, {
131           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
132           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
133           .length       = SZ_1M,
134           .type         = MT_DEVICE,
135   },
136
137   /* peripheral space... one for each of fast/slow/byte/16bit */
138   /* note, ide is only decoded in word space, even though some registers
139    * are only 8bit */
140
141   /* slow, byte */
142   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
143   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
144   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
145
146   /* slow, word */
147   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
148   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
149   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
150
151   /* fast, byte */
152   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
153   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
154   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
155
156   /* fast, word */
157   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
158   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
159   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
160 };
161
162 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
163 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
164 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
165
166 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
167         [0] = {
168                 .name           = "uclk",
169                 .divisor        = 1,
170                 .min_baud       = 0,
171                 .max_baud       = 0,
172         },
173         [1] = {
174                 .name           = "pclk",
175                 .divisor        = 1,
176                 .min_baud       = 0,
177                 .max_baud       = 0,
178         }
179 };
180
181
182 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
183         [0] = {
184                 .hwport      = 0,
185                 .flags       = 0,
186                 .ucon        = UCON,
187                 .ulcon       = ULCON,
188                 .ufcon       = UFCON,
189                 .clocks      = bast_serial_clocks,
190                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
191         },
192         [1] = {
193                 .hwport      = 1,
194                 .flags       = 0,
195                 .ucon        = UCON,
196                 .ulcon       = ULCON,
197                 .ufcon       = UFCON,
198                 .clocks      = bast_serial_clocks,
199                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
200         },
201         /* port 2 is not actually used */
202         [2] = {
203                 .hwport      = 2,
204                 .flags       = 0,
205                 .ucon        = UCON,
206                 .ulcon       = ULCON,
207                 .ufcon       = UFCON,
208                 .clocks      = bast_serial_clocks,
209                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
210         }
211 };
212
213 /* NAND Flash on BAST board */
214
215 #ifdef CONFIG_PM
216 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
217 {
218         /* ensure that an nRESET is not generated on resume. */
219         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
220         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
221
222         return 0;
223 }
224
225 static int bast_pm_resume(struct sys_device *sd)
226 {
227         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
228         return 0;
229 }
230
231 #else
232 #define bast_pm_suspend NULL
233 #define bast_pm_resume NULL
234 #endif
235
236 static struct sysdev_class bast_pm_sysclass = {
237         .name           = "mach-bast",
238         .suspend        = bast_pm_suspend,
239         .resume         = bast_pm_resume,
240 };
241
242 static struct sys_device bast_pm_sysdev = {
243         .cls            = &bast_pm_sysclass,
244 };
245
246 static int smartmedia_map[] = { 0 };
247 static int chip0_map[] = { 1 };
248 static int chip1_map[] = { 2 };
249 static int chip2_map[] = { 3 };
250
251 static struct mtd_partition __initdata bast_default_nand_part[] = {
252         [0] = {
253                 .name   = "Boot Agent",
254                 .size   = SZ_16K,
255                 .offset = 0,
256         },
257         [1] = {
258                 .name   = "/boot",
259                 .size   = SZ_4M - SZ_16K,
260                 .offset = SZ_16K,
261         },
262         [2] = {
263                 .name   = "user",
264                 .offset = SZ_4M,
265                 .size   = MTDPART_SIZ_FULL,
266         }
267 };
268
269 /* the bast has 4 selectable slots for nand-flash, the three
270  * on-board chip areas, as well as the external SmartMedia
271  * slot.
272  *
273  * Note, there is no current hot-plug support for the SmartMedia
274  * socket.
275 */
276
277 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
278         [0] = {
279                 .name           = "SmartMedia",
280                 .nr_chips       = 1,
281                 .nr_map         = smartmedia_map,
282                 .options        = NAND_SCAN_SILENT_NODEV,
283                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
284                 .partitions     = bast_default_nand_part,
285         },
286         [1] = {
287                 .name           = "chip0",
288                 .nr_chips       = 1,
289                 .nr_map         = chip0_map,
290                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
291                 .partitions     = bast_default_nand_part,
292         },
293         [2] = {
294                 .name           = "chip1",
295                 .nr_chips       = 1,
296                 .nr_map         = chip1_map,
297                 .options        = NAND_SCAN_SILENT_NODEV,
298                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
299                 .partitions     = bast_default_nand_part,
300         },
301         [3] = {
302                 .name           = "chip2",
303                 .nr_chips       = 1,
304                 .nr_map         = chip2_map,
305                 .options        = NAND_SCAN_SILENT_NODEV,
306                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
307                 .partitions     = bast_default_nand_part,
308         }
309 };
310
311 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
312 {
313         unsigned int tmp;
314
315         slot = set->nr_map[slot] & 3;
316
317         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
318                  slot, set, set->nr_map);
319
320         tmp = __raw_readb(BAST_VA_CTRL2);
321         tmp &= BAST_CPLD_CTLR2_IDERST;
322         tmp |= slot;
323         tmp |= BAST_CPLD_CTRL2_WNAND;
324
325         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
326
327         __raw_writeb(tmp, BAST_VA_CTRL2);
328 }
329
330 static struct s3c2410_platform_nand __initdata bast_nand_info = {
331         .tacls          = 30,
332         .twrph0         = 60,
333         .twrph1         = 60,
334         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
335         .sets           = bast_nand_sets,
336         .select_chip    = bast_nand_select,
337 };
338
339 /* DM9000 */
340
341 static struct resource bast_dm9k_resource[] = {
342         [0] = {
343                 .start = S3C2410_CS5 + BAST_PA_DM9000,
344                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
345                 .flags = IORESOURCE_MEM,
346         },
347         [1] = {
348                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
349                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
350                 .flags = IORESOURCE_MEM,
351         },
352         [2] = {
353                 .start = IRQ_DM9000,
354                 .end   = IRQ_DM9000,
355                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
356         }
357
358 };
359
360 /* for the moment we limit ourselves to 16bit IO until some
361  * better IO routines can be written and tested
362 */
363
364 static struct dm9000_plat_data bast_dm9k_platdata = {
365         .flags          = DM9000_PLATF_16BITONLY,
366 };
367
368 static struct platform_device bast_device_dm9k = {
369         .name           = "dm9000",
370         .id             = 0,
371         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
372         .resource       = bast_dm9k_resource,
373         .dev            = {
374                 .platform_data = &bast_dm9k_platdata,
375         }
376 };
377
378 /* serial devices */
379
380 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
381 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
382 #define SERIAL_CLK   (1843200)
383
384 static struct plat_serial8250_port bast_sio_data[] = {
385         [0] = {
386                 .mapbase        = SERIAL_BASE + 0x2f8,
387                 .irq            = IRQ_PCSERIAL1,
388                 .flags          = SERIAL_FLAGS,
389                 .iotype         = UPIO_MEM,
390                 .regshift       = 0,
391                 .uartclk        = SERIAL_CLK,
392         },
393         [1] = {
394                 .mapbase        = SERIAL_BASE + 0x3f8,
395                 .irq            = IRQ_PCSERIAL2,
396                 .flags          = SERIAL_FLAGS,
397                 .iotype         = UPIO_MEM,
398                 .regshift       = 0,
399                 .uartclk        = SERIAL_CLK,
400         },
401         { }
402 };
403
404 static struct platform_device bast_sio = {
405         .name                   = "serial8250",
406         .id                     = PLAT8250_DEV_PLATFORM,
407         .dev                    = {
408                 .platform_data  = &bast_sio_data,
409         },
410 };
411
412 /* we have devices on the bus which cannot work much over the
413  * standard 100KHz i2c bus frequency
414 */
415
416 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
417         .flags          = 0,
418         .slave_addr     = 0x10,
419         .frequency      = 100*1000,
420 };
421
422 /* Asix AX88796 10/100 ethernet controller */
423
424 static struct ax_plat_data bast_asix_platdata = {
425         .flags          = AXFLG_MAC_FROMDEV,
426         .wordlength     = 2,
427         .dcr_val        = 0x48,
428         .rcr_val        = 0x40,
429 };
430
431 static struct resource bast_asix_resource[] = {
432         [0] = {
433                 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
434                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
435                 .flags = IORESOURCE_MEM,
436         },
437         [1] = {
438                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
439                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
440                 .flags = IORESOURCE_MEM,
441         },
442         [2] = {
443                 .start = IRQ_ASIX,
444                 .end   = IRQ_ASIX,
445                 .flags = IORESOURCE_IRQ
446         }
447 };
448
449 static struct platform_device bast_device_asix = {
450         .name           = "ax88796",
451         .id             = 0,
452         .num_resources  = ARRAY_SIZE(bast_asix_resource),
453         .resource       = bast_asix_resource,
454         .dev            = {
455                 .platform_data = &bast_asix_platdata
456         }
457 };
458
459 /* Asix AX88796 10/100 ethernet controller parallel port */
460
461 static struct resource bast_asixpp_resource[] = {
462         [0] = {
463                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
464                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
465                 .flags = IORESOURCE_MEM,
466         }
467 };
468
469 static struct platform_device bast_device_axpp = {
470         .name           = "ax88796-pp",
471         .id             = 0,
472         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
473         .resource       = bast_asixpp_resource,
474 };
475
476 /* LCD/VGA controller */
477
478 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
479         {
480                 .type           = S3C2410_LCDCON1_TFT,
481                 .width          = 640,
482                 .height         = 480,
483
484                 .pixclock       = 33333,
485                 .xres           = 640,
486                 .yres           = 480,
487                 .bpp            = 4,
488                 .left_margin    = 40,
489                 .right_margin   = 20,
490                 .hsync_len      = 88,
491                 .upper_margin   = 30,
492                 .lower_margin   = 32,
493                 .vsync_len      = 3,
494
495                 .lcdcon5        = 0x00014b02,
496         },
497         {
498                 .type           = S3C2410_LCDCON1_TFT,
499                 .width          = 640,
500                 .height         = 480,
501
502                 .pixclock       = 33333,
503                 .xres           = 640,
504                 .yres           = 480,
505                 .bpp            = 8,
506                 .left_margin    = 40,
507                 .right_margin   = 20,
508                 .hsync_len      = 88,
509                 .upper_margin   = 30,
510                 .lower_margin   = 32,
511                 .vsync_len      = 3,
512
513                 .lcdcon5        = 0x00014b02,
514         },
515         {
516                 .type           = S3C2410_LCDCON1_TFT,
517                 .width          = 640,
518                 .height         = 480,
519
520                 .pixclock       = 33333,
521                 .xres           = 640,
522                 .yres           = 480,
523                 .bpp            = 16,
524                 .left_margin    = 40,
525                 .right_margin   = 20,
526                 .hsync_len      = 88,
527                 .upper_margin   = 30,
528                 .lower_margin   = 32,
529                 .vsync_len      = 3,
530
531                 .lcdcon5        = 0x00014b02,
532         },
533 };
534
535 /* LCD/VGA controller */
536
537 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
538
539         .displays = bast_lcd_info,
540         .num_displays = ARRAY_SIZE(bast_lcd_info),
541         .default_display = 1,
542 };
543
544 /* I2C devices fitted. */
545
546 static struct i2c_board_info bast_i2c_devs[] __initdata = {
547         {
548                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
549         }, {
550                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
551         }, {
552                 I2C_BOARD_INFO("ch7013", 0x75),
553         },
554 };
555
556 static struct s3c_hwmon_pdata bast_hwmon_info = {
557         /* LCD contrast (0-6.6V) */
558         .in[0] = &(struct s3c_hwmon_chcfg) {
559                 .name           = "lcd-contrast",
560                 .mult           = 3300,
561                 .div            = 512,
562         },
563         /* LED current feedback */
564         .in[1] = &(struct s3c_hwmon_chcfg) {
565                 .name           = "led-feedback",
566                 .mult           = 3300,
567                 .div            = 1024,
568         },
569         /* LCD feedback (0-6.6V) */
570         .in[2] = &(struct s3c_hwmon_chcfg) {
571                 .name           = "lcd-feedback",
572                 .mult           = 3300,
573                 .div            = 512,
574         },
575         /* Vcore (1.8-2.0V), Vref 3.3V  */
576         .in[3] = &(struct s3c_hwmon_chcfg) {
577                 .name           = "vcore",
578                 .mult           = 3300,
579                 .div            = 1024,
580         },
581 };
582
583 /* Standard BAST devices */
584 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
585
586 static struct platform_device *bast_devices[] __initdata = {
587         &s3c_device_usb,
588         &s3c_device_lcd,
589         &s3c_device_wdt,
590         &s3c_device_i2c0,
591         &s3c_device_rtc,
592         &s3c_device_nand,
593         &s3c_device_adc,
594         &s3c_device_hwmon,
595         &bast_device_dm9k,
596         &bast_device_asix,
597         &bast_device_axpp,
598         &bast_sio,
599 };
600
601 static struct clk *bast_clocks[] __initdata = {
602         &s3c24xx_dclk0,
603         &s3c24xx_dclk1,
604         &s3c24xx_clkout0,
605         &s3c24xx_clkout1,
606         &s3c24xx_uclk,
607 };
608
609 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
610         .refresh        = 7800, /* 7.8usec */
611         .auto_io        = 1,
612         .need_io        = 1,
613 };
614
615 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
616         .have_mic       = 1,
617         .have_lout      = 1,
618 };
619
620 static void __init bast_map_io(void)
621 {
622         /* initialise the clocks */
623
624         s3c24xx_dclk0.parent = &clk_upll;
625         s3c24xx_dclk0.rate   = 12*1000*1000;
626
627         s3c24xx_dclk1.parent = &clk_upll;
628         s3c24xx_dclk1.rate   = 24*1000*1000;
629
630         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
631         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
632
633         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
634
635         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
636
637         s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
638
639         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
640         s3c24xx_init_clocks(0);
641         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
642 }
643
644 static void __init bast_init(void)
645 {
646         sysdev_class_register(&bast_pm_sysclass);
647         sysdev_register(&bast_pm_sysdev);
648
649         s3c_i2c0_set_platdata(&bast_i2c_info);
650         s3c_nand_set_platdata(&bast_nand_info);
651         s3c24xx_fb_set_platdata(&bast_fb_info);
652         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
653
654         i2c_register_board_info(0, bast_i2c_devs,
655                                 ARRAY_SIZE(bast_i2c_devs));
656
657         usb_simtec_init();
658         nor_simtec_init();
659         simtec_audio_add(NULL, true, &bast_audio);
660
661         s3c_cpufreq_setboard(&bast_cpufreq);
662 }
663
664 MACHINE_START(BAST, "Simtec-BAST")
665         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
666         .phys_io        = S3C2410_PA_UART,
667         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
668         .boot_params    = S3C2410_SDRAM_PA + 0x100,
669         .map_io         = bast_map_io,
670         .init_irq       = s3c24xx_init_irq,
671         .init_machine   = bast_init,
672         .timer          = &s3c24xx_timer,
673 MACHINE_END