Merge branch 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/linville...
[linux-2.6.git] / arch / arm / mach-s3c2410 / mach-bast.c
1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
2  *
3  * Copyright (c) 2003-2005 Simtec Electronics
4  *   Ben Dooks <ben@simtec.co.uk>
5  *
6  * http://www.simtec.co.uk/products/EB2410ITX/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/list.h>
17 #include <linux/timer.h>
18 #include <linux/init.h>
19 #include <linux/platform_device.h>
20 #include <linux/dm9000.h>
21
22 #include <asm/mach/arch.h>
23 #include <asm/mach/map.h>
24 #include <asm/mach/irq.h>
25
26 #include <asm/arch/bast-map.h>
27 #include <asm/arch/bast-irq.h>
28 #include <asm/arch/bast-cpld.h>
29
30 #include <asm/hardware.h>
31 #include <asm/io.h>
32 #include <asm/irq.h>
33 #include <asm/mach-types.h>
34
35 //#include <asm/debug-ll.h>
36 #include <asm/arch/regs-serial.h>
37 #include <asm/arch/regs-gpio.h>
38 #include <asm/arch/regs-mem.h>
39 #include <asm/arch/regs-lcd.h>
40
41 #include <asm/arch/nand.h>
42 #include <asm/arch/iic.h>
43 #include <asm/arch/fb.h>
44
45 #include <linux/mtd/mtd.h>
46 #include <linux/mtd/nand.h>
47 #include <linux/mtd/nand_ecc.h>
48 #include <linux/mtd/partitions.h>
49
50 #include <linux/serial_8250.h>
51
52 #include "clock.h"
53 #include "devs.h"
54 #include "cpu.h"
55 #include "usb-simtec.h"
56
57 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
58
59 /* macros for virtual address mods for the io space entries */
60 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
61 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
62 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
63 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
64
65 /* macros to modify the physical addresses for io space */
66
67 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
68 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
69 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
70 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
71
72 static struct map_desc bast_iodesc[] __initdata = {
73   /* ISA IO areas */
74   {
75           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
76           .pfn          = PA_CS2(BAST_PA_ISAIO),
77           .length       = SZ_16M,
78           .type         = MT_DEVICE,
79   }, {
80           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
81           .pfn          = PA_CS3(BAST_PA_ISAIO),
82           .length       = SZ_16M,
83           .type         = MT_DEVICE,
84   },
85   /* bast CPLD control registers, and external interrupt controls */
86   {
87           .virtual      = (u32)BAST_VA_CTRL1,
88           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
89           .length       = SZ_1M,
90           .type         = MT_DEVICE,
91   }, {
92           .virtual      = (u32)BAST_VA_CTRL2,
93           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
94           .length       = SZ_1M,
95           .type         = MT_DEVICE,
96   }, {
97           .virtual      = (u32)BAST_VA_CTRL3,
98           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
99           .length       = SZ_1M,
100           .type         = MT_DEVICE,
101   }, {
102           .virtual      = (u32)BAST_VA_CTRL4,
103           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
104           .length       = SZ_1M,
105           .type         = MT_DEVICE,
106   },
107   /* PC104 IRQ mux */
108   {
109           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
110           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
111           .length       = SZ_1M,
112           .type         = MT_DEVICE,
113   }, {
114           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
115           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
116           .length       = SZ_1M,
117           .type         = MT_DEVICE,
118   }, {
119           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
120           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
121           .length       = SZ_1M,
122           .type         = MT_DEVICE,
123   },
124
125   /* peripheral space... one for each of fast/slow/byte/16bit */
126   /* note, ide is only decoded in word space, even though some registers
127    * are only 8bit */
128
129   /* slow, byte */
130   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
131   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
132   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
133   { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
134   { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
135   { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
136   { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
137
138   /* slow, word */
139   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
140   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
141   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
142   { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
143   { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
144   { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
145   { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
146
147   /* fast, byte */
148   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
149   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
150   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
151   { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
152   { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
153   { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
154   { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
155
156   /* fast, word */
157   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
158   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
159   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
160   { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
161   { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
162   { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
163   { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
164 };
165
166 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
167 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
168 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
169
170 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
171         [0] = {
172                 .name           = "uclk",
173                 .divisor        = 1,
174                 .min_baud       = 0,
175                 .max_baud       = 0,
176         },
177         [1] = {
178                 .name           = "pclk",
179                 .divisor        = 1,
180                 .min_baud       = 0,
181                 .max_baud       = 0,
182         }
183 };
184
185
186 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
187         [0] = {
188                 .hwport      = 0,
189                 .flags       = 0,
190                 .ucon        = UCON,
191                 .ulcon       = ULCON,
192                 .ufcon       = UFCON,
193                 .clocks      = bast_serial_clocks,
194                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
195         },
196         [1] = {
197                 .hwport      = 1,
198                 .flags       = 0,
199                 .ucon        = UCON,
200                 .ulcon       = ULCON,
201                 .ufcon       = UFCON,
202                 .clocks      = bast_serial_clocks,
203                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
204         },
205         /* port 2 is not actually used */
206         [2] = {
207                 .hwport      = 2,
208                 .flags       = 0,
209                 .ucon        = UCON,
210                 .ulcon       = ULCON,
211                 .ufcon       = UFCON,
212                 .clocks      = bast_serial_clocks,
213                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
214         }
215 };
216
217 /* NOR Flash on BAST board */
218
219 static struct resource bast_nor_resource[] = {
220         [0] = {
221                 .start = S3C2410_CS1 + 0x4000000,
222                 .end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
223                 .flags = IORESOURCE_MEM,
224         }
225 };
226
227 static struct platform_device bast_device_nor = {
228         .name           = "bast-nor",
229         .id             = -1,
230         .num_resources  = ARRAY_SIZE(bast_nor_resource),
231         .resource       = bast_nor_resource,
232 };
233
234 /* NAND Flash on BAST board */
235
236
237 static int smartmedia_map[] = { 0 };
238 static int chip0_map[] = { 1 };
239 static int chip1_map[] = { 2 };
240 static int chip2_map[] = { 3 };
241
242 static struct mtd_partition bast_default_nand_part[] = {
243         [0] = {
244                 .name   = "Boot Agent",
245                 .size   = SZ_16K,
246                 .offset = 0,
247         },
248         [1] = {
249                 .name   = "/boot",
250                 .size   = SZ_4M - SZ_16K,
251                 .offset = SZ_16K,
252         },
253         [2] = {
254                 .name   = "user",
255                 .offset = SZ_4M,
256                 .size   = MTDPART_SIZ_FULL,
257         }
258 };
259
260 /* the bast has 4 selectable slots for nand-flash, the three
261  * on-board chip areas, as well as the external SmartMedia
262  * slot.
263  *
264  * Note, there is no current hot-plug support for the SmartMedia
265  * socket.
266 */
267
268 static struct s3c2410_nand_set bast_nand_sets[] = {
269         [0] = {
270                 .name           = "SmartMedia",
271                 .nr_chips       = 1,
272                 .nr_map         = smartmedia_map,
273                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
274                 .partitions     = bast_default_nand_part,
275         },
276         [1] = {
277                 .name           = "chip0",
278                 .nr_chips       = 1,
279                 .nr_map         = chip0_map,
280                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
281                 .partitions     = bast_default_nand_part,
282         },
283         [2] = {
284                 .name           = "chip1",
285                 .nr_chips       = 1,
286                 .nr_map         = chip1_map,
287                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
288                 .partitions     = bast_default_nand_part,
289         },
290         [3] = {
291                 .name           = "chip2",
292                 .nr_chips       = 1,
293                 .nr_map         = chip2_map,
294                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
295                 .partitions     = bast_default_nand_part,
296         }
297 };
298
299 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
300 {
301         unsigned int tmp;
302
303         slot = set->nr_map[slot] & 3;
304
305         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
306                  slot, set, set->nr_map);
307
308         tmp = __raw_readb(BAST_VA_CTRL2);
309         tmp &= BAST_CPLD_CTLR2_IDERST;
310         tmp |= slot;
311         tmp |= BAST_CPLD_CTRL2_WNAND;
312
313         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
314
315         __raw_writeb(tmp, BAST_VA_CTRL2);
316 }
317
318 static struct s3c2410_platform_nand bast_nand_info = {
319         .tacls          = 30,
320         .twrph0         = 60,
321         .twrph1         = 60,
322         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
323         .sets           = bast_nand_sets,
324         .select_chip    = bast_nand_select,
325 };
326
327 /* DM9000 */
328
329 static struct resource bast_dm9k_resource[] = {
330         [0] = {
331                 .start = S3C2410_CS5 + BAST_PA_DM9000,
332                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
333                 .flags = IORESOURCE_MEM,
334         },
335         [1] = {
336                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
337                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
338                 .flags = IORESOURCE_MEM,
339         },
340         [2] = {
341                 .start = IRQ_DM9000,
342                 .end   = IRQ_DM9000,
343                 .flags = IORESOURCE_IRQ,
344         }
345
346 };
347
348 /* for the moment we limit ourselves to 16bit IO until some
349  * better IO routines can be written and tested
350 */
351
352 static struct dm9000_plat_data bast_dm9k_platdata = {
353         .flags          = DM9000_PLATF_16BITONLY,
354 };
355
356 static struct platform_device bast_device_dm9k = {
357         .name           = "dm9000",
358         .id             = 0,
359         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
360         .resource       = bast_dm9k_resource,
361         .dev            = {
362                 .platform_data = &bast_dm9k_platdata,
363         }
364 };
365
366 /* serial devices */
367
368 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
369 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
370 #define SERIAL_CLK   (1843200)
371
372 static struct plat_serial8250_port bast_sio_data[] = {
373         [0] = {
374                 .mapbase        = SERIAL_BASE + 0x2f8,
375                 .irq            = IRQ_PCSERIAL1,
376                 .flags          = SERIAL_FLAGS,
377                 .iotype         = UPIO_MEM,
378                 .regshift       = 0,
379                 .uartclk        = SERIAL_CLK,
380         },
381         [1] = {
382                 .mapbase        = SERIAL_BASE + 0x3f8,
383                 .irq            = IRQ_PCSERIAL2,
384                 .flags          = SERIAL_FLAGS,
385                 .iotype         = UPIO_MEM,
386                 .regshift       = 0,
387                 .uartclk        = SERIAL_CLK,
388         },
389         { }
390 };
391
392 static struct platform_device bast_sio = {
393         .name                   = "serial8250",
394         .id                     = PLAT8250_DEV_PLATFORM,
395         .dev                    = {
396                 .platform_data  = &bast_sio_data,
397         },
398 };
399
400 /* we have devices on the bus which cannot work much over the
401  * standard 100KHz i2c bus frequency
402 */
403
404 static struct s3c2410_platform_i2c bast_i2c_info = {
405         .flags          = 0,
406         .slave_addr     = 0x10,
407         .bus_freq       = 100*1000,
408         .max_freq       = 130*1000,
409 };
410
411
412 static struct s3c2410fb_mach_info __initdata bast_lcd_info = {
413         .width          = 640,
414         .height         = 480,
415
416         .xres           = {
417                 .min            = 320,
418                 .max            = 1024,
419                 .defval         = 640,
420         },
421
422         .yres           = {
423                 .min            = 240,
424                 .max            = 600,
425                 .defval         = 480,
426         },
427
428         .bpp            = {
429                 .min            = 4,
430                 .max            = 16,
431                 .defval         = 8,
432         },
433
434         .regs           = {
435                 .lcdcon1        = 0x00000176,
436                 .lcdcon2        = 0x1d77c7c2,
437                 .lcdcon3        = 0x013a7f13,
438                 .lcdcon4        = 0x00000057,
439                 .lcdcon5        = 0x00014b02,
440         }
441 };
442
443 /* Standard BAST devices */
444
445 static struct platform_device *bast_devices[] __initdata = {
446         &s3c_device_usb,
447         &s3c_device_lcd,
448         &s3c_device_wdt,
449         &s3c_device_i2c,
450         &s3c_device_iis,
451         &s3c_device_rtc,
452         &s3c_device_nand,
453         &bast_device_nor,
454         &bast_device_dm9k,
455         &bast_sio,
456 };
457
458 static struct clk *bast_clocks[] = {
459         &s3c24xx_dclk0,
460         &s3c24xx_dclk1,
461         &s3c24xx_clkout0,
462         &s3c24xx_clkout1,
463         &s3c24xx_uclk,
464 };
465
466 static struct s3c24xx_board bast_board __initdata = {
467         .devices       = bast_devices,
468         .devices_count = ARRAY_SIZE(bast_devices),
469         .clocks        = bast_clocks,
470         .clocks_count  = ARRAY_SIZE(bast_clocks),
471 };
472
473 static void __init bast_map_io(void)
474 {
475         /* initialise the clocks */
476
477         s3c24xx_dclk0.parent = NULL;
478         s3c24xx_dclk0.rate   = 12*1000*1000;
479
480         s3c24xx_dclk1.parent = NULL;
481         s3c24xx_dclk1.rate   = 24*1000*1000;
482
483         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
484         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
485
486         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
487
488         s3c_device_nand.dev.platform_data = &bast_nand_info;
489         s3c_device_i2c.dev.platform_data = &bast_i2c_info;
490
491         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
492         s3c24xx_init_clocks(0);
493         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
494         s3c24xx_set_board(&bast_board);
495         usb_simtec_init();
496 }
497
498 static void __init bast_init(void)
499 {
500         s3c24xx_fb_set_platdata(&bast_lcd_info);
501 }
502
503 MACHINE_START(BAST, "Simtec-BAST")
504         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
505         .phys_io        = S3C2410_PA_UART,
506         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
507         .boot_params    = S3C2410_SDRAM_PA + 0x100,
508         .map_io         = bast_map_io,
509         .init_irq       = s3c24xx_init_irq,
510         .init_machine   = bast_init,
511         .timer          = &s3c24xx_timer,
512 MACHINE_END