Linux-2.6.12-rc2
[linux-2.6.git] / arch / arm / mach-s3c2410 / dma.c
1 /* linux/arch/arm/mach-bast/dma.c
2  *
3  * (c) 2003-2005 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C2410 DMA core
7  *
8  * http://www.simtec.co.uk/products/EB2410ITX/
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14  * Changelog:
15  *  27-Feb-2005 BJD  Added kmem cache for dma descriptors
16  *  18-Nov-2004 BJD  Removed error for loading onto stopped channel
17  *  10-Nov-2004 BJD  Ensure all external symbols exported for modules
18  *  10-Nov-2004 BJD  Use sys_device and sysdev_class for power management
19  *  08-Aug-2004 BJD  Apply rmk's suggestions
20  *  21-Jul-2004 BJD  Ported to linux 2.6
21  *  12-Jul-2004 BJD  Finished re-write and change of API
22  *  06-Jul-2004 BJD  Rewrote dma code to try and cope with various problems
23  *  23-May-2003 BJD  Created file
24  *  19-Aug-2003 BJD  Cleanup, header fix, added URL
25  *
26  * This file is based on the Sangwook Lee/Samsung patches, re-written due
27  * to various ommisions from the code (such as flexible dma configuration)
28  * for use with the BAST system board.
29  *
30  * The re-write is pretty much complete, and should be good enough for any
31  * possible DMA function
32  */
33
34 #include <linux/config.h>
35
36 #ifdef CONFIG_S3C2410_DMA_DEBUG
37 #define DEBUG
38 #endif
39
40 #include <linux/module.h>
41 #include <linux/init.h>
42 #include <linux/sched.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/sysdev.h>
46 #include <linux/slab.h>
47 #include <linux/errno.h>
48 #include <linux/delay.h>
49
50 #include <asm/system.h>
51 #include <asm/irq.h>
52 #include <asm/hardware.h>
53 #include <asm/io.h>
54 #include <asm/dma.h>
55
56 #include <asm/mach/dma.h>
57 #include <asm/arch/map.h>
58
59 /* io map for dma */
60 static void __iomem *dma_base;
61 static kmem_cache_t *dma_kmem;
62
63 /* dma channel state information */
64 s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];
65
66 /* debugging functions */
67
68 #define BUF_MAGIC (0xcafebabe)
69
70 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
71
72 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
73
74 #if 1
75 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
76 #else
77 static inline void
78 dma_wrreg(s3c2410_dma_chan_t *chan, int reg, unsigned long val)
79 {
80         pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
81         writel(val, dma_regaddr(chan, reg));
82 }
83
84 #endif
85
86 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
87
88 /* captured register state for debug */
89
90 struct s3c2410_dma_regstate {
91         unsigned long         dcsrc;
92         unsigned long         disrc;
93         unsigned long         dstat;
94         unsigned long         dcon;
95         unsigned long         dmsktrig;
96 };
97
98 #ifdef CONFIG_S3C2410_DMA_DEBUG
99
100 /* dmadbg_showregs
101  *
102  * simple debug routine to print the current state of the dma registers
103 */
104
105 static void
106 dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs)
107 {
108         regs->dcsrc    = dma_rdreg(chan, S3C2410_DMA_DCSRC);
109         regs->disrc    = dma_rdreg(chan, S3C2410_DMA_DISRC);
110         regs->dstat    = dma_rdreg(chan, S3C2410_DMA_DSTAT);
111         regs->dcon     = dma_rdreg(chan, S3C2410_DMA_DCON);
112         regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
113 }
114
115 static void
116 dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan,
117                  struct s3c2410_dma_regstate *regs)
118 {
119         printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
120                chan->number, fname, line,
121                regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
122                regs->dcon);
123 }
124
125 static void
126 dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan)
127 {
128         struct s3c2410_dma_regstate state;
129
130         dmadbg_capture(chan, &state);
131
132         printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
133                chan->number, fname, line, chan->load_state,
134                chan->curr, chan->next, chan->end);
135
136         dmadbg_showregs(fname, line, chan, &state);
137 }
138
139 #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
140 #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
141 #else
142 #define dbg_showregs(chan) do { } while(0)
143 #define dbg_showchan(chan) do { } while(0)
144 #endif /* CONFIG_S3C2410_DMA_DEBUG */
145
146 #define check_channel(chan) \
147   do { if ((chan) >= S3C2410_DMA_CHANNELS) { \
148     printk(KERN_ERR "%s: invalid channel %d\n", __FUNCTION__, (chan)); \
149     return -EINVAL; \
150   } } while(0)
151
152
153 /* s3c2410_dma_stats_timeout
154  *
155  * Update DMA stats from timeout info
156 */
157
158 static void
159 s3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val)
160 {
161         if (stats == NULL)
162                 return;
163
164         if (val > stats->timeout_longest)
165                 stats->timeout_longest = val;
166         if (val < stats->timeout_shortest)
167                 stats->timeout_shortest = val;
168
169         stats->timeout_avg += val;
170 }
171
172 /* s3c2410_dma_waitforload
173  *
174  * wait for the DMA engine to load a buffer, and update the state accordingly
175 */
176
177 static int
178 s3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line)
179 {
180         int timeout = chan->load_timeout;
181         int took;
182
183         if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
184                 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
185                 return 0;
186         }
187
188         if (chan->stats != NULL)
189                 chan->stats->loads++;
190
191         while (--timeout > 0) {
192                 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
193                         took = chan->load_timeout - timeout;
194
195                         s3c2410_dma_stats_timeout(chan->stats, took);
196
197                         switch (chan->load_state) {
198                         case S3C2410_DMALOAD_1LOADED:
199                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
200                                 break;
201
202                         default:
203                                 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
204                         }
205
206                         return 1;
207                 }
208         }
209
210         if (chan->stats != NULL) {
211                 chan->stats->timeout_failed++;
212         }
213
214         return 0;
215 }
216
217
218
219 /* s3c2410_dma_loadbuffer
220  *
221  * load a buffer, and update the channel state
222 */
223
224 static inline int
225 s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan,
226                        s3c2410_dma_buf_t *buf)
227 {
228         unsigned long reload;
229
230         pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
231                  buf, (unsigned long)buf->data, buf->size);
232
233         if (buf == NULL) {
234                 dmawarn("buffer is NULL\n");
235                 return -EINVAL;
236         }
237
238         /* check the state of the channel before we do anything */
239
240         if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
241                 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
242         }
243
244         if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
245                 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
246         }
247
248         /* it would seem sensible if we are the last buffer to not bother
249          * with the auto-reload bit, so that the DMA engine will not try
250          * and load another transfer after this one has finished...
251          */
252         if (chan->load_state == S3C2410_DMALOAD_NONE) {
253                 pr_debug("load_state is none, checking for noreload (next=%p)\n",
254                          buf->next);
255                 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
256         } else {
257                 pr_debug("load_state is %d => autoreload\n", chan->load_state);
258                 reload = S3C2410_DCON_AUTORELOAD;
259         }
260
261         writel(buf->data, chan->addr_reg);
262
263         dma_wrreg(chan, S3C2410_DMA_DCON,
264                   chan->dcon | reload | (buf->size/chan->xfer_unit));
265
266         chan->next = buf->next;
267
268         /* update the state of the channel */
269
270         switch (chan->load_state) {
271         case S3C2410_DMALOAD_NONE:
272                 chan->load_state = S3C2410_DMALOAD_1LOADED;
273                 break;
274
275         case S3C2410_DMALOAD_1RUNNING:
276                 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
277                 break;
278
279         default:
280                 dmawarn("dmaload: unknown state %d in loadbuffer\n",
281                         chan->load_state);
282                 break;
283         }
284
285         return 0;
286 }
287
288 /* s3c2410_dma_call_op
289  *
290  * small routine to call the op routine with the given op if it has been
291  * registered
292 */
293
294 static void
295 s3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op)
296 {
297         if (chan->op_fn != NULL) {
298                 (chan->op_fn)(chan, op);
299         }
300 }
301
302 /* s3c2410_dma_buffdone
303  *
304  * small wrapper to check if callback routine needs to be called, and
305  * if so, call it
306 */
307
308 static inline void
309 s3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf,
310                      s3c2410_dma_buffresult_t result)
311 {
312         pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
313                  chan->callback_fn, buf, buf->id, buf->size, result);
314
315         if (chan->callback_fn != NULL) {
316                 (chan->callback_fn)(chan, buf->id, buf->size, result);
317         }
318 }
319
320 /* s3c2410_dma_start
321  *
322  * start a dma channel going
323 */
324
325 static int s3c2410_dma_start(s3c2410_dma_chan_t *chan)
326 {
327         unsigned long tmp;
328         unsigned long flags;
329
330         pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
331
332         local_irq_save(flags);
333
334         if (chan->state == S3C2410_DMA_RUNNING) {
335                 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
336                 local_irq_restore(flags);
337                 return 0;
338         }
339
340         chan->state = S3C2410_DMA_RUNNING;
341
342         /* check wether there is anything to load, and if not, see
343          * if we can find anything to load
344          */
345
346         if (chan->load_state == S3C2410_DMALOAD_NONE) {
347                 if (chan->next == NULL) {
348                         printk(KERN_ERR "dma%d: channel has nothing loaded\n",
349                                chan->number);
350                         chan->state = S3C2410_DMA_IDLE;
351                         local_irq_restore(flags);
352                         return -EINVAL;
353                 }
354
355                 s3c2410_dma_loadbuffer(chan, chan->next);
356         }
357
358         dbg_showchan(chan);
359
360         /* enable the channel */
361
362         if (!chan->irq_enabled) {
363                 enable_irq(chan->irq);
364                 chan->irq_enabled = 1;
365         }
366
367         /* start the channel going */
368
369         tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
370         tmp &= ~S3C2410_DMASKTRIG_STOP;
371         tmp |= S3C2410_DMASKTRIG_ON;
372         dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
373
374         pr_debug("wrote %08lx to DMASKTRIG\n", tmp);
375
376 #if 0
377         /* the dma buffer loads should take care of clearing the AUTO
378          * reloading feature */
379         tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
380         tmp &= ~S3C2410_DCON_NORELOAD;
381         dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
382 #endif
383
384         s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
385
386         dbg_showchan(chan);
387
388         local_irq_restore(flags);
389         return 0;
390 }
391
392 /* s3c2410_dma_canload
393  *
394  * work out if we can queue another buffer into the DMA engine
395 */
396
397 static int
398 s3c2410_dma_canload(s3c2410_dma_chan_t *chan)
399 {
400         if (chan->load_state == S3C2410_DMALOAD_NONE ||
401             chan->load_state == S3C2410_DMALOAD_1RUNNING)
402                 return 1;
403
404         return 0;
405 }
406
407
408 /* s3c2410_dma_enqueue
409  *
410  * queue an given buffer for dma transfer.
411  *
412  * id         the device driver's id information for this buffer
413  * data       the physical address of the buffer data
414  * size       the size of the buffer in bytes
415  *
416  * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
417  * is checked, and if set, the channel is started. If this flag isn't set,
418  * then an error will be returned.
419  *
420  * It is possible to queue more than one DMA buffer onto a channel at
421  * once, and the code will deal with the re-loading of the next buffer
422  * when necessary.
423 */
424
425 int s3c2410_dma_enqueue(unsigned int channel, void *id,
426                         dma_addr_t data, int size)
427 {
428         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
429         s3c2410_dma_buf_t *buf;
430         unsigned long flags;
431
432         check_channel(channel);
433
434         pr_debug("%s: id=%p, data=%08x, size=%d\n",
435                  __FUNCTION__, id, (unsigned int)data, size);
436
437         buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
438         if (buf == NULL) {
439                 pr_debug("%s: out of memory (%d alloc)\n",
440                          __FUNCTION__, sizeof(*buf));
441                 return -ENOMEM;
442         }
443
444         pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
445
446         //dbg_showchan(chan);
447
448         buf->next  = NULL;
449         buf->data  = buf->ptr = data;
450         buf->size  = size;
451         buf->id    = id;
452         buf->magic = BUF_MAGIC;
453
454         local_irq_save(flags);
455
456         if (chan->curr == NULL) {
457                 /* we've got nothing loaded... */
458                 pr_debug("%s: buffer %p queued onto empty channel\n",
459                          __FUNCTION__, buf);
460
461                 chan->curr = buf;
462                 chan->end  = buf;
463                 chan->next = NULL;
464         } else {
465                 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
466                          chan->number, __FUNCTION__, buf);
467
468                 if (chan->end == NULL)
469                         pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
470                                  chan->number, __FUNCTION__, chan);
471
472                 chan->end->next = buf;
473                 chan->end = buf;
474         }
475
476         /* if necessary, update the next buffer field */
477         if (chan->next == NULL)
478                 chan->next = buf;
479
480         /* check to see if we can load a buffer */
481         if (chan->state == S3C2410_DMA_RUNNING) {
482                 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
483                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
484                                 printk(KERN_ERR "dma%d: loadbuffer:"
485                                        "timeout loading buffer\n",
486                                        chan->number);
487                                 dbg_showchan(chan);
488                                 local_irq_restore(flags);
489                                 return -EINVAL;
490                         }
491                 }
492
493                 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
494                         s3c2410_dma_loadbuffer(chan, chan->next);
495                 }
496         } else if (chan->state == S3C2410_DMA_IDLE) {
497                 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
498                         s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
499                 }
500         }
501
502         local_irq_restore(flags);
503         return 0;
504 }
505
506 EXPORT_SYMBOL(s3c2410_dma_enqueue);
507
508 static inline void
509 s3c2410_dma_freebuf(s3c2410_dma_buf_t *buf)
510 {
511         int magicok = (buf->magic == BUF_MAGIC);
512
513         buf->magic = -1;
514
515         if (magicok) {
516                 kmem_cache_free(dma_kmem, buf);
517         } else {
518                 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
519         }
520 }
521
522 /* s3c2410_dma_lastxfer
523  *
524  * called when the system is out of buffers, to ensure that the channel
525  * is prepared for shutdown.
526 */
527
528 static inline void
529 s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan)
530 {
531         pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
532                  chan->number, chan->load_state);
533
534         switch (chan->load_state) {
535         case S3C2410_DMALOAD_NONE:
536                 break;
537
538         case S3C2410_DMALOAD_1LOADED:
539                 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
540                                 /* flag error? */
541                         printk(KERN_ERR "dma%d: timeout waiting for load\n",
542                                chan->number);
543                         return;
544                 }
545                 break;
546
547         default:
548                 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",
549                          chan->number, chan->load_state);
550                 return;
551
552         }
553
554         /* hopefully this'll shut the damned thing up after the transfer... */
555         dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
556 }
557
558
559 #define dmadbg2(x...)
560
561 static irqreturn_t
562 s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
563 {
564         s3c2410_dma_chan_t *chan = (s3c2410_dma_chan_t *)devpw;
565         s3c2410_dma_buf_t  *buf;
566
567         buf = chan->curr;
568
569         dbg_showchan(chan);
570
571         /* modify the channel state */
572
573         switch (chan->load_state) {
574         case S3C2410_DMALOAD_1RUNNING:
575                 /* TODO - if we are running only one buffer, we probably
576                  * want to reload here, and then worry about the buffer
577                  * callback */
578
579                 chan->load_state = S3C2410_DMALOAD_NONE;
580                 break;
581
582         case S3C2410_DMALOAD_1LOADED:
583                 /* iirc, we should go back to NONE loaded here, we
584                  * had a buffer, and it was never verified as being
585                  * loaded.
586                  */
587
588                 chan->load_state = S3C2410_DMALOAD_NONE;
589                 break;
590
591         case S3C2410_DMALOAD_1LOADED_1RUNNING:
592                 /* we'll worry about checking to see if another buffer is
593                  * ready after we've called back the owner. This should
594                  * ensure we do not wait around too long for the DMA
595                  * engine to start the next transfer
596                  */
597
598                 chan->load_state = S3C2410_DMALOAD_1LOADED;
599                 break;
600
601         case S3C2410_DMALOAD_NONE:
602                 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
603                        chan->number);
604                 break;
605
606         default:
607                 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
608                        chan->number, chan->load_state);
609                 break;
610         }
611
612         if (buf != NULL) {
613                 /* update the chain to make sure that if we load any more
614                  * buffers when we call the callback function, things should
615                  * work properly */
616
617                 chan->curr = buf->next;
618                 buf->next  = NULL;
619
620                 if (buf->magic != BUF_MAGIC) {
621                         printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
622                                chan->number, __FUNCTION__, buf);
623                         return IRQ_HANDLED;
624                 }
625
626                 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
627
628                 /* free resouces */
629                 s3c2410_dma_freebuf(buf);
630         } else {
631         }
632
633         if (chan->next != NULL) {
634                 unsigned long flags;
635
636                 switch (chan->load_state) {
637                 case S3C2410_DMALOAD_1RUNNING:
638                         /* don't need to do anything for this state */
639                         break;
640
641                 case S3C2410_DMALOAD_NONE:
642                         /* can load buffer immediately */
643                         break;
644
645                 case S3C2410_DMALOAD_1LOADED:
646                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
647                                 /* flag error? */
648                                 printk(KERN_ERR "dma%d: timeout waiting for load\n",
649                                        chan->number);
650                                 return IRQ_HANDLED;
651                         }
652
653                         break;
654
655                 case S3C2410_DMALOAD_1LOADED_1RUNNING:
656                         goto no_load;
657
658                 default:
659                         printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
660                                chan->number, chan->load_state);
661                         return IRQ_HANDLED;
662                 }
663
664                 local_irq_save(flags);
665                 s3c2410_dma_loadbuffer(chan, chan->next);
666                 local_irq_restore(flags);
667         } else {
668                 s3c2410_dma_lastxfer(chan);
669
670                 /* see if we can stop this channel.. */
671                 if (chan->load_state == S3C2410_DMALOAD_NONE) {
672                         pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
673                                  chan->number, jiffies);
674                         s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
675                 }
676         }
677
678  no_load:
679         return IRQ_HANDLED;
680 }
681
682
683
684 /* s3c2410_request_dma
685  *
686  * get control of an dma channel
687 */
688
689 int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client,
690                         void *dev)
691 {
692         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
693         unsigned long flags;
694         int err;
695
696         pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
697                  channel, client->name, dev);
698
699         check_channel(channel);
700
701         local_irq_save(flags);
702
703         dbg_showchan(chan);
704
705         if (chan->in_use) {
706                 if (client != chan->client) {
707                         printk(KERN_ERR "dma%d: already in use\n", channel);
708                         local_irq_restore(flags);
709                         return -EBUSY;
710                 } else {
711                         printk(KERN_ERR "dma%d: client already has channel\n", channel);
712                 }
713         }
714
715         chan->client = client;
716         chan->in_use = 1;
717
718         if (!chan->irq_claimed) {
719                 pr_debug("dma%d: %s : requesting irq %d\n",
720                          channel, __FUNCTION__, chan->irq);
721
722                 err = request_irq(chan->irq, s3c2410_dma_irq, SA_INTERRUPT,
723                                   client->name, (void *)chan);
724
725                 if (err) {
726                         chan->in_use = 0;
727                         local_irq_restore(flags);
728
729                         printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
730                                client->name, chan->irq, chan->number);
731                         return err;
732                 }
733
734                 chan->irq_claimed = 1;
735                 chan->irq_enabled = 1;
736         }
737
738         local_irq_restore(flags);
739
740         /* need to setup */
741
742         pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
743
744         return 0;
745 }
746
747 EXPORT_SYMBOL(s3c2410_dma_request);
748
749 /* s3c2410_dma_free
750  *
751  * release the given channel back to the system, will stop and flush
752  * any outstanding transfers, and ensure the channel is ready for the
753  * next claimant.
754  *
755  * Note, although a warning is currently printed if the freeing client
756  * info is not the same as the registrant's client info, the free is still
757  * allowed to go through.
758 */
759
760 int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client)
761 {
762         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
763         unsigned long flags;
764
765         check_channel(channel);
766
767         local_irq_save(flags);
768
769
770         if (chan->client != client) {
771                 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
772                        channel, chan->client, client);
773         }
774
775         /* sort out stopping and freeing the channel */
776
777         if (chan->state != S3C2410_DMA_IDLE) {
778                 pr_debug("%s: need to stop dma channel %p\n",
779                        __FUNCTION__, chan);
780
781                 /* possibly flush the channel */
782                 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
783         }
784
785         chan->client = NULL;
786         chan->in_use = 0;
787
788         local_irq_restore(flags);
789
790         return 0;
791 }
792
793 EXPORT_SYMBOL(s3c2410_dma_free);
794
795 static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan)
796 {
797         unsigned long tmp;
798         unsigned long flags;
799
800         pr_debug("%s:\n", __FUNCTION__);
801
802         dbg_showchan(chan);
803
804         local_irq_save(flags);
805
806         s3c2410_dma_call_op(chan,  S3C2410_DMAOP_STOP);
807
808         tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
809         tmp |= S3C2410_DMASKTRIG_STOP;
810         dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
811
812 #if 0
813         /* should also clear interrupts, according to WinCE BSP */
814         tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
815         tmp |= S3C2410_DCON_NORELOAD;
816         dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
817 #endif
818
819         chan->state      = S3C2410_DMA_IDLE;
820         chan->load_state = S3C2410_DMALOAD_NONE;
821
822         local_irq_restore(flags);
823
824         return 0;
825 }
826
827 /* s3c2410_dma_flush
828  *
829  * stop the channel, and remove all current and pending transfers
830 */
831
832 static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan)
833 {
834         s3c2410_dma_buf_t *buf, *next;
835         unsigned long flags;
836
837         pr_debug("%s:\n", __FUNCTION__);
838
839         local_irq_save(flags);
840
841         if (chan->state != S3C2410_DMA_IDLE) {
842                 pr_debug("%s: stopping channel...\n", __FUNCTION__ );
843                 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
844         }
845
846         buf = chan->curr;
847         if (buf == NULL)
848                 buf = chan->next;
849
850         chan->curr = chan->next = chan->end = NULL;
851
852         if (buf != NULL) {
853                 for ( ; buf != NULL; buf = next) {
854                         next = buf->next;
855
856                         pr_debug("%s: free buffer %p, next %p\n",
857                                __FUNCTION__, buf, buf->next);
858
859                         s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
860                         s3c2410_dma_freebuf(buf);
861                 }
862         }
863
864         local_irq_restore(flags);
865
866         return 0;
867 }
868
869
870 int
871 s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op)
872 {
873         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
874
875         check_channel(channel);
876
877         switch (op) {
878         case S3C2410_DMAOP_START:
879                 return s3c2410_dma_start(chan);
880
881         case S3C2410_DMAOP_STOP:
882                 return s3c2410_dma_dostop(chan);
883
884         case S3C2410_DMAOP_PAUSE:
885                 return -ENOENT;
886
887         case S3C2410_DMAOP_RESUME:
888                 return -ENOENT;
889
890         case S3C2410_DMAOP_FLUSH:
891                 return s3c2410_dma_flush(chan);
892
893         case S3C2410_DMAOP_TIMEOUT:
894                 return 0;
895
896         }
897
898         return -ENOENT;      /* unknown, don't bother */
899 }
900
901 EXPORT_SYMBOL(s3c2410_dma_ctrl);
902
903 /* DMA configuration for each channel
904  *
905  * DISRCC -> source of the DMA (AHB,APB)
906  * DISRC  -> source address of the DMA
907  * DIDSTC -> destination of the DMA (AHB,APD)
908  * DIDST  -> destination address of the DMA
909 */
910
911 /* s3c2410_dma_config
912  *
913  * xfersize:     size of unit in bytes (1,2,4)
914  * dcon:         base value of the DCONx register
915 */
916
917 int s3c2410_dma_config(dmach_t channel,
918                        int xferunit,
919                        int dcon)
920 {
921         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
922
923         pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
924                  __FUNCTION__, channel, xferunit, dcon);
925
926         check_channel(channel);
927
928         switch (xferunit) {
929         case 1:
930                 dcon |= S3C2410_DCON_BYTE;
931                 break;
932
933         case 2:
934                 dcon |= S3C2410_DCON_HALFWORD;
935                 break;
936
937         case 4:
938                 dcon |= S3C2410_DCON_WORD;
939                 break;
940
941         default:
942                 pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
943                 return -EINVAL;
944         }
945
946         dcon |= S3C2410_DCON_HWTRIG;
947         dcon |= S3C2410_DCON_INTREQ;
948
949         pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
950
951         chan->dcon = dcon;
952         chan->xfer_unit = xferunit;
953
954         return 0;
955 }
956
957 EXPORT_SYMBOL(s3c2410_dma_config);
958
959 int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
960 {
961         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
962
963         check_channel(channel);
964
965         pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
966
967         chan->flags = flags;
968
969         return 0;
970 }
971
972 EXPORT_SYMBOL(s3c2410_dma_setflags);
973
974
975 /* do we need to protect the settings of the fields from
976  * irq?
977 */
978
979 int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
980 {
981         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
982
983         check_channel(channel);
984
985         pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
986
987         chan->op_fn = rtn;
988
989         return 0;
990 }
991
992 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
993
994 int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
995 {
996         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
997
998         check_channel(channel);
999
1000         pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1001
1002         chan->callback_fn = rtn;
1003
1004         return 0;
1005 }
1006
1007 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1008
1009 /* s3c2410_dma_devconfig
1010  *
1011  * configure the dma source/destination hardware type and address
1012  *
1013  * source:    S3C2410_DMASRC_HW: source is hardware
1014  *            S3C2410_DMASRC_MEM: source is memory
1015  *
1016  * hwcfg:     the value for xxxSTCn register,
1017  *            bit 0: 0=increment pointer, 1=leave pointer
1018  *            bit 1: 0=soucre is AHB, 1=soucre is APB
1019  *
1020  * devaddr:   physical address of the source
1021 */
1022
1023 int s3c2410_dma_devconfig(int channel,
1024                           s3c2410_dmasrc_t source,
1025                           int hwcfg,
1026                           unsigned long devaddr)
1027 {
1028         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
1029
1030         check_channel(channel);
1031
1032         pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1033                  __FUNCTION__, (int)source, hwcfg, devaddr);
1034
1035         chan->source = source;
1036         chan->dev_addr = devaddr;
1037
1038         switch (source) {
1039         case S3C2410_DMASRC_HW:
1040                 /* source is hardware */
1041                 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1042                          __FUNCTION__, devaddr, hwcfg);
1043                 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1044                 dma_wrreg(chan, S3C2410_DMA_DISRC,  devaddr);
1045                 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1046
1047                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1048                 return 0;
1049
1050         case S3C2410_DMASRC_MEM:
1051                 /* source is memory */
1052                 pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1053                           __FUNCTION__, devaddr, hwcfg);
1054                 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1055                 dma_wrreg(chan, S3C2410_DMA_DIDST,  devaddr);
1056                 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1057
1058                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1059                 return 0;
1060         }
1061
1062         printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
1063         return -EINVAL;
1064 }
1065
1066 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1067
1068 /* s3c2410_dma_getposition
1069  *
1070  * returns the current transfer points for the dma source and destination
1071 */
1072
1073 int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1074 {
1075         s3c2410_dma_chan_t *chan = &s3c2410_chans[channel];
1076
1077         check_channel(channel);
1078
1079         if (src != NULL)
1080                 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1081
1082         if (dst != NULL)
1083                 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1084
1085         return 0;
1086 }
1087
1088 EXPORT_SYMBOL(s3c2410_dma_getposition);
1089
1090
1091 /* system device class */
1092
1093 #ifdef CONFIG_PM
1094
1095 static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1096 {
1097         s3c2410_dma_chan_t *cp = container_of(dev, s3c2410_dma_chan_t, dev);
1098
1099         printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1100
1101         if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1102                 /* the dma channel is still working, which is probably
1103                  * a bad thing to do over suspend/resume. We stop the
1104                  * channel and assume that the client is either going to
1105                  * retry after resume, or that it is broken.
1106                  */
1107
1108                 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1109                        cp->number);
1110
1111                 s3c2410_dma_dostop(cp);
1112         }
1113
1114         return 0;
1115 }
1116
1117 static int s3c2410_dma_resume(struct sys_device *dev)
1118 {
1119         return 0;
1120 }
1121
1122 #else
1123 #define s3c2410_dma_suspend NULL
1124 #define s3c2410_dma_resume  NULL
1125 #endif /* CONFIG_PM */
1126
1127 static struct sysdev_class dma_sysclass = {
1128         set_kset_name("s3c24xx-dma"),
1129         .suspend        = s3c2410_dma_suspend,
1130         .resume         = s3c2410_dma_resume,
1131 };
1132
1133 /* kmem cache implementation */
1134
1135 static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f)
1136 {
1137         memset(p, 0, sizeof(s3c2410_dma_buf_t));
1138 }
1139
1140
1141 /* initialisation code */
1142
1143 static int __init s3c2410_init_dma(void)
1144 {
1145         s3c2410_dma_chan_t *cp;
1146         int channel;
1147         int ret;
1148
1149         printk("S3C2410 DMA Driver, (c) 2003-2004 Simtec Electronics\n");
1150
1151         dma_base = ioremap(S3C2410_PA_DMA, 0x200);
1152         if (dma_base == NULL) {
1153                 printk(KERN_ERR "dma failed to remap register block\n");
1154                 return -ENOMEM;
1155         }
1156
1157         ret = sysdev_class_register(&dma_sysclass);
1158         if (ret != 0) {
1159                 printk(KERN_ERR "dma sysclass registration failed\n");
1160                 goto err;
1161         }
1162
1163         dma_kmem = kmem_cache_create("dma_desc", sizeof(s3c2410_dma_buf_t), 0,
1164                                      SLAB_HWCACHE_ALIGN,
1165                                      s3c2410_dma_cache_ctor, NULL);
1166
1167         if (dma_kmem == NULL) {
1168                 printk(KERN_ERR "dma failed to make kmem cache\n");
1169                 ret = -ENOMEM;
1170                 goto err;
1171         }
1172
1173         for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) {
1174                 cp = &s3c2410_chans[channel];
1175
1176                 memset(cp, 0, sizeof(s3c2410_dma_chan_t));
1177
1178                 /* dma channel irqs are in order.. */
1179                 cp->number = channel;
1180                 cp->irq    = channel + IRQ_DMA0;
1181                 cp->regs   = dma_base + (channel*0x40);
1182
1183                 /* point current stats somewhere */
1184                 cp->stats  = &cp->stats_store;
1185                 cp->stats_store.timeout_shortest = LONG_MAX;
1186
1187                 /* basic channel configuration */
1188
1189                 cp->load_timeout = 1<<18;
1190
1191                 /* register system device */
1192
1193                 cp->dev.cls = &dma_sysclass;
1194                 cp->dev.id  = channel;
1195                 ret = sysdev_register(&cp->dev);
1196
1197                 printk("DMA channel %d at %p, irq %d\n",
1198                        cp->number, cp->regs, cp->irq);
1199         }
1200
1201         return 0;
1202
1203  err:
1204         kmem_cache_destroy(dma_kmem);
1205         iounmap(dma_base);
1206         dma_base = NULL;
1207         return ret;
1208 }
1209
1210 __initcall(s3c2410_init_dma);