[ARM] pxa/zeus: make internal zeus_get_pcb_info static
[linux-2.6.git] / arch / arm / mach-pxa / zeus.c
1 /*
2  *  Support for the Arcom ZEUS.
3  *
4  *  Copyright (C) 2006 Arcom Control Systems Ltd.
5  *
6  *  Loosely based on Arcom's 2.6.16.28.
7  *  Maintained by Marc Zyngier <maz@misterjones.org>
8  *
9  *  This program is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License version 2 as
11  *  published by the Free Software Foundation.
12  */
13
14 #include <linux/cpufreq.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/pm.h>
18 #include <linux/gpio.h>
19 #include <linux/serial_8250.h>
20 #include <linux/dm9000.h>
21 #include <linux/mmc/host.h>
22 #include <linux/spi/spi.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/partitions.h>
25 #include <linux/mtd/physmap.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/pca953x.h>
28
29 #include <asm/mach-types.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32
33 #include <plat/i2c.h>
34
35 #include <mach/pxa2xx-regs.h>
36 #include <mach/regs-uart.h>
37 #include <mach/ohci.h>
38 #include <mach/mmc.h>
39 #include <mach/pxa27x-udc.h>
40 #include <mach/udc.h>
41 #include <mach/pxafb.h>
42 #include <mach/pxa2xx_spi.h>
43 #include <mach/mfp-pxa27x.h>
44 #include <mach/pm.h>
45 #include <mach/audio.h>
46 #include <mach/arcom-pcmcia.h>
47 #include <mach/zeus.h>
48
49 #include "generic.h"
50
51 /*
52  * Interrupt handling
53  */
54
55 static unsigned long zeus_irq_enabled_mask;
56 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
57 static const int zeus_isa_irq_map[] = {
58         0,              /* ISA irq #0, invalid */
59         0,              /* ISA irq #1, invalid */
60         0,              /* ISA irq #2, invalid */
61         1 << 0,         /* ISA irq #3 */
62         1 << 1,         /* ISA irq #4 */
63         1 << 2,         /* ISA irq #5 */
64         1 << 3,         /* ISA irq #6 */
65         1 << 4,         /* ISA irq #7 */
66         0,              /* ISA irq #8, invalid */
67         0,              /* ISA irq #9, invalid */
68         1 << 5,         /* ISA irq #10 */
69         1 << 6,         /* ISA irq #11 */
70         1 << 7,         /* ISA irq #12 */
71 };
72
73 static inline int zeus_irq_to_bitmask(unsigned int irq)
74 {
75         return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
76 }
77
78 static inline int zeus_bit_to_irq(int bit)
79 {
80         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
81 }
82
83 static void zeus_ack_irq(unsigned int irq)
84 {
85         __raw_writew(zeus_irq_to_bitmask(irq), ZEUS_CPLD_ISA_IRQ);
86 }
87
88 static void zeus_mask_irq(unsigned int irq)
89 {
90         zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(irq));
91 }
92
93 static void zeus_unmask_irq(unsigned int irq)
94 {
95         zeus_irq_enabled_mask |= zeus_irq_to_bitmask(irq);
96 }
97
98 static inline unsigned long zeus_irq_pending(void)
99 {
100         return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
101 }
102
103 static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
104 {
105         unsigned long pending;
106
107         pending = zeus_irq_pending();
108         do {
109                 /* we're in a chained irq handler,
110                  * so ack the interrupt by hand */
111                 desc->chip->ack(gpio_to_irq(ZEUS_ISA_GPIO));
112
113                 if (likely(pending)) {
114                         irq = zeus_bit_to_irq(__ffs(pending));
115                         generic_handle_irq(irq);
116                 }
117                 pending = zeus_irq_pending();
118         } while (pending);
119 }
120
121 static struct irq_chip zeus_irq_chip = {
122         .name   = "ISA",
123         .ack    = zeus_ack_irq,
124         .mask   = zeus_mask_irq,
125         .unmask = zeus_unmask_irq,
126 };
127
128 static void __init zeus_init_irq(void)
129 {
130         int level;
131         int isa_irq;
132
133         pxa27x_init_irq();
134
135         /* Peripheral IRQs. It would be nice to move those inside driver
136            configuration, but it is not supported at the moment. */
137         set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO),       IRQ_TYPE_EDGE_RISING);
138         set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO),     IRQ_TYPE_EDGE_RISING);
139         set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO),        IRQ_TYPE_EDGE_RISING);
140         set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),    IRQ_TYPE_EDGE_FALLING);
141         set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO),        IRQ_TYPE_EDGE_FALLING);
142
143         /* Setup ISA IRQs */
144         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
145                 isa_irq = zeus_bit_to_irq(level);
146                 set_irq_chip(isa_irq, &zeus_irq_chip);
147                 set_irq_handler(isa_irq, handle_edge_irq);
148                 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
149         }
150
151         set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
152         set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
153 }
154
155
156 /*
157  * Platform devices
158  */
159
160 /* Flash */
161 static struct resource zeus_mtd_resources[] = {
162         [0] = { /* NOR Flash (up to 64MB) */
163                 .start  = ZEUS_FLASH_PHYS,
164                 .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
165                 .flags  = IORESOURCE_MEM,
166         },
167         [1] = { /* SRAM */
168                 .start  = ZEUS_SRAM_PHYS,
169                 .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
170                 .flags  = IORESOURCE_MEM,
171         },
172 };
173
174 static struct physmap_flash_data zeus_flash_data[] = {
175         [0] = {
176                 .width          = 2,
177                 .parts          = NULL,
178                 .nr_parts       = 0,
179         },
180 };
181
182 static struct platform_device zeus_mtd_devices[] = {
183         [0] = {
184                 .name           = "physmap-flash",
185                 .id             = 0,
186                 .dev            = {
187                         .platform_data = &zeus_flash_data[0],
188                 },
189                 .resource       = &zeus_mtd_resources[0],
190                 .num_resources  = 1,
191         },
192 };
193
194 /* Serial */
195 static struct resource zeus_serial_resources[] = {
196         {
197                 .start  = 0x10000000,
198                 .end    = 0x1000000f,
199                 .flags  = IORESOURCE_MEM,
200         },
201         {
202                 .start  = 0x10800000,
203                 .end    = 0x1080000f,
204                 .flags  = IORESOURCE_MEM,
205         },
206         {
207                 .start  = 0x11000000,
208                 .end    = 0x1100000f,
209                 .flags  = IORESOURCE_MEM,
210         },
211         {
212                 .start  = 0x40100000,
213                 .end    = 0x4010001f,
214                 .flags  = IORESOURCE_MEM,
215         },
216         {
217                 .start  = 0x40200000,
218                 .end    = 0x4020001f,
219                 .flags  = IORESOURCE_MEM,
220         },
221         {
222                 .start  = 0x40700000,
223                 .end    = 0x4070001f,
224                 .flags  = IORESOURCE_MEM,
225         },
226 };
227
228 static struct plat_serial8250_port serial_platform_data[] = {
229         /* External UARTs */
230         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
231         { /* COM1 */
232                 .mapbase        = 0x10000000,
233                 .irq            = gpio_to_irq(ZEUS_UARTA_GPIO),
234                 .irqflags       = IRQF_TRIGGER_RISING,
235                 .uartclk        = 14745600,
236                 .regshift       = 1,
237                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
238                 .iotype         = UPIO_MEM,
239         },
240         { /* COM2 */
241                 .mapbase        = 0x10800000,
242                 .irq            = gpio_to_irq(ZEUS_UARTB_GPIO),
243                 .irqflags       = IRQF_TRIGGER_RISING,
244                 .uartclk        = 14745600,
245                 .regshift       = 1,
246                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
247                 .iotype         = UPIO_MEM,
248         },
249         { /* COM3 */
250                 .mapbase        = 0x11000000,
251                 .irq            = gpio_to_irq(ZEUS_UARTC_GPIO),
252                 .irqflags       = IRQF_TRIGGER_RISING,
253                 .uartclk        = 14745600,
254                 .regshift       = 1,
255                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
256                 .iotype         = UPIO_MEM,
257         },
258         { /* COM4 */
259                 .mapbase        = 0x11800000,
260                 .irq            = gpio_to_irq(ZEUS_UARTD_GPIO),
261                 .irqflags       = IRQF_TRIGGER_RISING,
262                 .uartclk        = 14745600,
263                 .regshift       = 1,
264                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
265                 .iotype         = UPIO_MEM,
266         },
267         /* Internal UARTs */
268         { /* FFUART */
269                 .membase        = (void *)&FFUART,
270                 .mapbase        = __PREG(FFUART),
271                 .irq            = IRQ_FFUART,
272                 .uartclk        = 921600 * 16,
273                 .regshift       = 2,
274                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
275                 .iotype         = UPIO_MEM,
276         },
277         { /* BTUART */
278                 .membase        = (void *)&BTUART,
279                 .mapbase        = __PREG(BTUART),
280                 .irq            = IRQ_BTUART,
281                 .uartclk        = 921600 * 16,
282                 .regshift       = 2,
283                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
284                 .iotype         = UPIO_MEM,
285         },
286         { /* STUART */
287                 .membase        = (void *)&STUART,
288                 .mapbase        = __PREG(STUART),
289                 .irq            = IRQ_STUART,
290                 .uartclk        = 921600 * 16,
291                 .regshift       = 2,
292                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
293                 .iotype         = UPIO_MEM,
294         },
295         { },
296 };
297
298 static struct platform_device zeus_serial_device = {
299         .name = "serial8250",
300         .id   = PLAT8250_DEV_PLATFORM,
301         .dev  = {
302                 .platform_data = serial_platform_data,
303         },
304         .num_resources  = ARRAY_SIZE(zeus_serial_resources),
305         .resource       = zeus_serial_resources,
306 };
307
308 /* Ethernet */
309 static struct resource zeus_dm9k0_resource[] = {
310         [0] = {
311                 .start = ZEUS_ETH0_PHYS,
312                 .end   = ZEUS_ETH0_PHYS + 1,
313                 .flags = IORESOURCE_MEM
314         },
315         [1] = {
316                 .start = ZEUS_ETH0_PHYS + 2,
317                 .end   = ZEUS_ETH0_PHYS + 3,
318                 .flags = IORESOURCE_MEM
319         },
320         [2] = {
321                 .start = gpio_to_irq(ZEUS_ETH0_GPIO),
322                 .end   = gpio_to_irq(ZEUS_ETH0_GPIO),
323                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
324         },
325 };
326
327 static struct resource zeus_dm9k1_resource[] = {
328         [0] = {
329                 .start = ZEUS_ETH1_PHYS,
330                 .end   = ZEUS_ETH1_PHYS + 1,
331                 .flags = IORESOURCE_MEM
332         },
333         [1] = {
334                 .start = ZEUS_ETH1_PHYS + 2,
335                 .end   = ZEUS_ETH1_PHYS + 3,
336                 .flags = IORESOURCE_MEM,
337         },
338         [2] = {
339                 .start = gpio_to_irq(ZEUS_ETH1_GPIO),
340                 .end   = gpio_to_irq(ZEUS_ETH1_GPIO),
341                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
342         },
343 };
344
345 static struct dm9000_plat_data zeus_dm9k_platdata = {
346         .flags          = DM9000_PLATF_16BITONLY,
347 };
348
349 static struct platform_device zeus_dm9k0_device = {
350         .name           = "dm9000",
351         .id             = 0,
352         .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
353         .resource       = zeus_dm9k0_resource,
354         .dev            = {
355                 .platform_data = &zeus_dm9k_platdata,
356         }
357 };
358
359 static struct platform_device zeus_dm9k1_device = {
360         .name           = "dm9000",
361         .id             = 1,
362         .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
363         .resource       = zeus_dm9k1_resource,
364         .dev            = {
365                 .platform_data = &zeus_dm9k_platdata,
366         }
367 };
368
369 /* External SRAM */
370 static struct resource zeus_sram_resource = {
371         .start          = ZEUS_SRAM_PHYS,
372         .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
373         .flags          = IORESOURCE_MEM,
374 };
375
376 static struct platform_device zeus_sram_device = {
377         .name           = "pxa2xx-8bit-sram",
378         .id             = 0,
379         .num_resources  = 1,
380         .resource       = &zeus_sram_resource,
381 };
382
383 /* SPI interface on SSP3 */
384 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
385         .num_chipselect = 1,
386         .enable_dma     = 1,
387 };
388
389 static struct platform_device pxa2xx_spi_ssp3_device = {
390         .name = "pxa2xx-spi",
391         .id = 3,
392         .dev = {
393                 .platform_data = &pxa2xx_spi_ssp3_master_info,
394         },
395 };
396
397 /* Leds */
398 static struct gpio_led zeus_leds[] = {
399         [0] = {
400                 .name            = "zeus:yellow:1",
401                 .default_trigger = "heartbeat",
402                 .gpio            = ZEUS_EXT0_GPIO(3),
403                 .active_low      = 1,
404         },
405         [1] = {
406                 .name            = "zeus:yellow:2",
407                 .default_trigger = "default-on",
408                 .gpio            = ZEUS_EXT0_GPIO(4),
409                 .active_low      = 1,
410         },
411         [2] = {
412                 .name            = "zeus:yellow:3",
413                 .default_trigger = "default-on",
414                 .gpio            = ZEUS_EXT0_GPIO(5),
415                 .active_low      = 1,
416         },
417 };
418
419 static struct gpio_led_platform_data zeus_leds_info = {
420         .leds           = zeus_leds,
421         .num_leds       = ARRAY_SIZE(zeus_leds),
422 };
423
424 static struct platform_device zeus_leds_device = {
425         .name           = "leds-gpio",
426         .id             = -1,
427         .dev            = {
428                 .platform_data  = &zeus_leds_info,
429         },
430 };
431
432 static void zeus_cf_reset(int state)
433 {
434         u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
435
436         if (state)
437                 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
438         else
439                 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
440
441         __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
442 }
443
444 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
445         .cd_gpio        = ZEUS_CF_CD_GPIO,
446         .rdy_gpio       = ZEUS_CF_RDY_GPIO,
447         .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
448         .reset          = zeus_cf_reset,
449 };
450
451 static struct platform_device zeus_pcmcia_device = {
452         .name           = "zeus-pcmcia",
453         .id             = -1,
454         .dev            = {
455                 .platform_data  = &zeus_pcmcia_info,
456         },
457 };
458
459 static struct platform_device *zeus_devices[] __initdata = {
460         &zeus_serial_device,
461         &zeus_mtd_devices[0],
462         &zeus_dm9k0_device,
463         &zeus_dm9k1_device,
464         &zeus_sram_device,
465         &pxa2xx_spi_ssp3_device,
466         &zeus_leds_device,
467         &zeus_pcmcia_device,
468 };
469
470 /* AC'97 */
471 static pxa2xx_audio_ops_t zeus_ac97_info = {
472         .reset_gpio = 95,
473 };
474
475
476 /*
477  * USB host
478  */
479
480 static int zeus_ohci_init(struct device *dev)
481 {
482         int err;
483
484         /* Switch on port 2. */
485         if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
486                 dev_err(dev, "Can't request USB2_PWREN\n");
487                 return err;
488         }
489
490         if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
491                 gpio_free(ZEUS_USB2_PWREN_GPIO);
492                 dev_err(dev, "Can't enable USB2_PWREN\n");
493                 return err;
494         }
495
496         /* Port 2 is shared between host and client interface. */
497         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
498
499         return 0;
500 }
501
502 static void zeus_ohci_exit(struct device *dev)
503 {
504         /* Power-off port 2 */
505         gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
506         gpio_free(ZEUS_USB2_PWREN_GPIO);
507 }
508
509 static struct pxaohci_platform_data zeus_ohci_platform_data = {
510         .port_mode      = PMM_NPS_MODE,
511         .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
512         .init           = zeus_ohci_init,
513         .exit           = zeus_ohci_exit,
514 };
515
516 /*
517  * Flat Panel
518  */
519
520 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
521 {
522         gpio_set_value(ZEUS_LCD_EN_GPIO, on);
523 }
524
525 static void zeus_backlight_power(int on)
526 {
527         gpio_set_value(ZEUS_BKLEN_GPIO, on);
528 }
529
530 static int zeus_setup_fb_gpios(void)
531 {
532         int err;
533
534         if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
535                 goto out_err;
536
537         if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
538                 goto out_err_lcd;
539
540         if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
541                 goto out_err_lcd;
542
543         if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
544                 goto out_err_bkl;
545
546         return 0;
547
548 out_err_bkl:
549         gpio_free(ZEUS_BKLEN_GPIO);
550 out_err_lcd:
551         gpio_free(ZEUS_LCD_EN_GPIO);
552 out_err:
553         return err;
554 }
555
556 static struct pxafb_mode_info zeus_fb_mode_info[] = {
557         {
558                 .pixclock       = 39722,
559
560                 .xres           = 640,
561                 .yres           = 480,
562
563                 .bpp            = 16,
564
565                 .hsync_len      = 63,
566                 .left_margin    = 16,
567                 .right_margin   = 81,
568
569                 .vsync_len      = 2,
570                 .upper_margin   = 12,
571                 .lower_margin   = 31,
572
573                 .sync           = 0,
574         },
575 };
576
577 static struct pxafb_mach_info zeus_fb_info = {
578         .modes                  = zeus_fb_mode_info,
579         .num_modes              = 1,
580         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
581         .pxafb_lcd_power        = zeus_lcd_power,
582         .pxafb_backlight_power  = zeus_backlight_power,
583 };
584
585 /*
586  * MMC/SD Device
587  *
588  * The card detect interrupt isn't debounced so we delay it by 250ms
589  * to give the card a chance to fully insert/eject.
590  */
591
592 static struct pxamci_platform_data zeus_mci_platform_data = {
593         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
594         .detect_delay           = HZ/4,
595         .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
596         .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
597         .gpio_card_ro_invert    = 1,
598         .gpio_power             = -1
599 };
600
601 /*
602  * USB Device Controller
603  */
604 static void zeus_udc_command(int cmd)
605 {
606         switch (cmd) {
607         case PXA2XX_UDC_CMD_DISCONNECT:
608                 pr_info("zeus: disconnecting USB client\n");
609                 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
610                 break;
611
612         case PXA2XX_UDC_CMD_CONNECT:
613                 pr_info("zeus: connecting USB client\n");
614                 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
615                 break;
616         }
617 }
618
619 static struct pxa2xx_udc_mach_info zeus_udc_info = {
620         .udc_command = zeus_udc_command,
621 };
622
623 static void zeus_power_off(void)
624 {
625         local_irq_disable();
626         pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP);
627 }
628
629 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
630                              unsigned ngpio, void *context)
631 {
632         int i;
633         u8 pcb_info = 0;
634
635         for (i = 0; i < 8; i++) {
636                 int pcb_bit = gpio + i + 8;
637
638                 if (gpio_request(pcb_bit, "pcb info")) {
639                         dev_err(&client->dev, "Can't request pcb info %d\n", i);
640                         continue;
641                 }
642
643                 if (gpio_direction_input(pcb_bit)) {
644                         dev_err(&client->dev, "Can't read pcb info %d\n", i);
645                         gpio_free(pcb_bit);
646                         continue;
647                 }
648
649                 pcb_info |= !!gpio_get_value(pcb_bit) << i;
650
651                 gpio_free(pcb_bit);
652         }
653
654         dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
655                  pcb_info >> 4, pcb_info & 0xf);
656
657         return 0;
658 }
659
660 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
661         [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
662         [1] = {
663                 .gpio_base      = ZEUS_EXT1_GPIO_BASE,
664                 .setup          = zeus_get_pcb_info,
665         },
666         [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
667 };
668
669 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
670         {
671                 I2C_BOARD_INFO("pca9535",       0x21),
672                 .platform_data  = &zeus_pca953x_pdata[0],
673         },
674         {
675                 I2C_BOARD_INFO("pca9535",       0x22),
676                 .platform_data  = &zeus_pca953x_pdata[1],
677         },
678         {
679                 I2C_BOARD_INFO("pca9535",       0x20),
680                 .platform_data  = &zeus_pca953x_pdata[2],
681                 .irq            = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
682         },
683         { I2C_BOARD_INFO("lm75a",       0x48) },
684         { I2C_BOARD_INFO("24c01",       0x50) },
685         { I2C_BOARD_INFO("isl1208",     0x6f) },
686 };
687
688 static mfp_cfg_t zeus_pin_config[] __initdata = {
689         GPIO15_nCS_1,
690         GPIO78_nCS_2,
691         GPIO80_nCS_4,
692         GPIO33_nCS_5,
693
694         GPIO22_GPIO,
695         GPIO32_MMC_CLK,
696         GPIO92_MMC_DAT_0,
697         GPIO109_MMC_DAT_1,
698         GPIO110_MMC_DAT_2,
699         GPIO111_MMC_DAT_3,
700         GPIO112_MMC_CMD,
701
702         GPIO88_USBH1_PWR,
703         GPIO89_USBH1_PEN,
704         GPIO119_USBH2_PWR,
705         GPIO120_USBH2_PEN,
706
707         GPIO86_LCD_LDD_16,
708         GPIO87_LCD_LDD_17,
709
710         GPIO102_GPIO,
711         GPIO104_CIF_DD_2,
712         GPIO105_CIF_DD_1,
713
714         GPIO48_nPOE,
715         GPIO49_nPWE,
716         GPIO50_nPIOR,
717         GPIO51_nPIOW,
718         GPIO85_nPCE_1,
719         GPIO54_nPCE_2,
720         GPIO79_PSKTSEL,
721         GPIO55_nPREG,
722         GPIO56_nPWAIT,
723         GPIO57_nIOIS16,
724         GPIO36_GPIO,            /* CF CD */
725         GPIO97_GPIO,            /* CF PWREN */
726         GPIO99_GPIO,            /* CF RDY */
727 };
728
729 static void __init zeus_init(void)
730 {
731         u16 dm9000_msc = 0xe279;
732
733         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
734         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
735
736         /* Fix timings for dm9000s (CS1/CS2)*/
737         MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
738         MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
739
740         pm_power_off = zeus_power_off;
741
742         pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
743
744         platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
745
746         pxa_set_ohci_info(&zeus_ohci_platform_data);
747
748         if (zeus_setup_fb_gpios())
749                 pr_err("Failed to setup fb gpios\n");
750         else
751                 set_pxa_fb_info(&zeus_fb_info);
752
753         pxa_set_mci_info(&zeus_mci_platform_data);
754         pxa_set_udc_info(&zeus_udc_info);
755         pxa_set_ac97_info(&zeus_ac97_info);
756         pxa_set_i2c_info(NULL);
757         i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
758 }
759
760 static struct map_desc zeus_io_desc[] __initdata = {
761         {
762                 .virtual = ZEUS_CPLD_VERSION,
763                 .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
764                 .length  = 0x1000,
765                 .type    = MT_DEVICE,
766         },
767         {
768                 .virtual = ZEUS_CPLD_ISA_IRQ,
769                 .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
770                 .length  = 0x1000,
771                 .type    = MT_DEVICE,
772         },
773         {
774                 .virtual = ZEUS_CPLD_CONTROL,
775                 .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
776                 .length  = 0x1000,
777                 .type    = MT_DEVICE,
778         },
779         {
780                 .virtual = ZEUS_CPLD_EXTWDOG,
781                 .pfn     = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS),
782                 .length  = 0x1000,
783                 .type    = MT_DEVICE,
784         },
785         {
786                 .virtual = ZEUS_PC104IO,
787                 .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
788                 .length  = 0x00800000,
789                 .type    = MT_DEVICE,
790         },
791 };
792
793 static void __init zeus_map_io(void)
794 {
795         pxa_map_io();
796
797         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
798
799         /* Clear PSPR to ensure a full restart on wake-up. */
800         PMCR = PSPR = 0;
801
802         /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
803         OSCC |= OSCC_OON;
804
805         /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
806          * float chip selects and PCMCIA */
807         PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
808 }
809
810 MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS")
811         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
812         .phys_io        = 0x40000000,
813         .io_pg_offst    = ((io_p2v(0x40000000) >> 18) & 0xfffc),
814         .boot_params    = 0xa0000100,
815         .map_io         = zeus_map_io,
816         .init_irq       = zeus_init_irq,
817         .timer          = &pxa_timer,
818         .init_machine   = zeus_init,
819 MACHINE_END
820