1b4ad9d5e2ebeedeab6804e47b52651cc3e6c74e
[linux-2.6.git] / arch / arm / mach-orion5x / wrt350n-v2-setup.c
1 /*
2  * arch/arm/mach-orion5x/wrt350n-v2-setup.c
3  *
4  * This file is licensed under the terms of the GNU General Public
5  * License version 2.  This program is licensed "as is" without any
6  * warranty of any kind, whether express or implied.
7  */
8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/platform_device.h>
12 #include <linux/pci.h>
13 #include <linux/irq.h>
14 #include <linux/delay.h>
15 #include <linux/mtd/physmap.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/ethtool.h>
18 #include <net/dsa.h>
19 #include <asm/mach-types.h>
20 #include <asm/gpio.h>
21 #include <asm/mach/arch.h>
22 #include <asm/mach/pci.h>
23 #include <mach/orion5x.h>
24 #include "common.h"
25 #include "mpp.h"
26
27 static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
28         {  0, MPP_GPIO },               /* Power LED green (0=on) */
29         {  1, MPP_GPIO },               /* Security LED (0=on) */
30         {  2, MPP_GPIO },               /* Internal Button (0=on) */
31         {  3, MPP_GPIO },               /* Reset Button (0=on) */
32         {  4, MPP_GPIO },               /* PCI int */
33         {  5, MPP_GPIO },               /* Power LED orange (0=on) */
34         {  6, MPP_GPIO },               /* USB LED (0=on) */
35         {  7, MPP_GPIO },               /* Wireless LED (0=on) */
36         {  8, MPP_UNUSED },             /* ??? */
37         {  9, MPP_GIGE },               /* GE_RXERR */
38         { 10, MPP_UNUSED },             /* ??? */
39         { 11, MPP_UNUSED },             /* ??? */
40         { 12, MPP_GIGE },               /* GE_TXD[4] */
41         { 13, MPP_GIGE },               /* GE_TXD[5] */
42         { 14, MPP_GIGE },               /* GE_TXD[6] */
43         { 15, MPP_GIGE },               /* GE_TXD[7] */
44         { 16, MPP_GIGE },               /* GE_RXD[4] */
45         { 17, MPP_GIGE },               /* GE_RXD[5] */
46         { 18, MPP_GIGE },               /* GE_RXD[6] */
47         { 19, MPP_GIGE },               /* GE_RXD[7] */
48         { -1 },
49 };
50
51 /*
52  * 8M NOR flash Device bus boot chip select
53  */
54 #define WRT350N_V2_NOR_BOOT_BASE        0xf4000000
55 #define WRT350N_V2_NOR_BOOT_SIZE        SZ_8M
56
57 static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
58         {
59                 .name           = "kernel",
60                 .offset         = 0x00000000,
61                 .size           = 0x00760000,
62         }, {
63                 .name           = "rootfs",
64                 .offset         = 0x001a0000,
65                 .size           = 0x005c0000,
66         }, {
67                 .name           = "lang",
68                 .offset         = 0x00760000,
69                 .size           = 0x00040000,
70         }, {
71                 .name           = "nvram",
72                 .offset         = 0x007a0000,
73                 .size           = 0x00020000,
74         }, {
75                 .name           = "u-boot",
76                 .offset         = 0x007c0000,
77                 .size           = 0x00040000,
78         },
79 };
80
81 static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
82         .width          = 1,
83         .parts          = wrt350n_v2_nor_flash_partitions,
84         .nr_parts       = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
85 };
86
87 static struct resource wrt350n_v2_nor_flash_resource = {
88         .flags          = IORESOURCE_MEM,
89         .start          = WRT350N_V2_NOR_BOOT_BASE,
90         .end            = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
91 };
92
93 static struct platform_device wrt350n_v2_nor_flash = {
94         .name                   = "physmap-flash",
95         .id                     = 0,
96         .dev            = {
97                 .platform_data  = &wrt350n_v2_nor_flash_data,
98         },
99         .num_resources          = 1,
100         .resource               = &wrt350n_v2_nor_flash_resource,
101 };
102
103 static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
104         .phy_addr       = MV643XX_ETH_PHY_NONE,
105         .speed          = SPEED_1000,
106         .duplex         = DUPLEX_FULL,
107 };
108
109 static struct dsa_chip_data wrt350n_v2_switch_chip_data = {
110         .port_names[0]  = "lan2",
111         .port_names[1]  = "lan1",
112         .port_names[2]  = "wan",
113         .port_names[3]  = "cpu",
114         .port_names[5]  = "lan3",
115         .port_names[7]  = "lan4",
116 };
117
118 static struct dsa_platform_data wrt350n_v2_switch_plat_data = {
119         .nr_chips       = 1,
120         .chip           = &wrt350n_v2_switch_chip_data,
121 };
122
123 static void __init wrt350n_v2_init(void)
124 {
125         /*
126          * Setup basic Orion functions. Need to be called early.
127          */
128         orion5x_init();
129
130         orion5x_mpp_conf(wrt350n_v2_mpp_modes);
131
132         /*
133          * Configure peripherals.
134          */
135         orion5x_ehci0_init();
136         orion5x_eth_init(&wrt350n_v2_eth_data);
137         orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
138         orion5x_uart0_init();
139
140         orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
141                                    WRT350N_V2_NOR_BOOT_SIZE);
142         platform_device_register(&wrt350n_v2_nor_flash);
143 }
144
145 static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
146 {
147         int irq;
148
149         /*
150          * Check for devices with hard-wired IRQs.
151          */
152         irq = orion5x_pci_map_irq(dev, slot, pin);
153         if (irq != -1)
154                 return irq;
155
156         /*
157          * Mini-PCI slot.
158          */
159         if (slot == 7)
160                 return gpio_to_irq(4);
161
162         return -1;
163 }
164
165 static struct hw_pci wrt350n_v2_pci __initdata = {
166         .nr_controllers = 2,
167         .swizzle        = pci_std_swizzle,
168         .setup          = orion5x_pci_sys_setup,
169         .scan           = orion5x_pci_sys_scan_bus,
170         .map_irq        = wrt350n_v2_pci_map_irq,
171 };
172
173 static int __init wrt350n_v2_pci_init(void)
174 {
175         if (machine_is_wrt350n_v2())
176                 pci_common_init(&wrt350n_v2_pci);
177
178         return 0;
179 }
180 subsys_initcall(wrt350n_v2_pci_init);
181
182 MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
183         /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
184         .phys_io        = ORION5X_REGS_PHYS_BASE,
185         .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
186         .boot_params    = 0x00000100,
187         .init_machine   = wrt350n_v2_init,
188         .map_io         = orion5x_map_io,
189         .init_irq       = orion5x_init_irq,
190         .timer          = &orion5x_timer,
191         .fixup          = tag_fixup_mem32,
192 MACHINE_END