omap: headers: Move remaining headers from include/mach to include/plat
[linux-2.6.git] / arch / arm / mach-omap2 / serial.c
1 /*
2  * arch/arm/mach-omap2/serial.c
3  *
4  * OMAP2 serial support.
5  *
6  * Copyright (C) 2005-2008 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * Major rework for PM support by Kevin Hilman
10  *
11  * Based off of arch/arm/mach-omap/omap1/serial.c
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License. See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #include <plat/common.h>
28 #include <plat/board.h>
29 #include <plat/clock.h>
30 #include <plat/control.h>
31
32 #include "prm.h"
33 #include "pm.h"
34 #include "prm-regbits-34xx.h"
35
36 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
37
38 #define DEFAULT_TIMEOUT (5 * HZ)
39
40 struct omap_uart_state {
41         int num;
42         int can_sleep;
43         struct timer_list timer;
44         u32 timeout;
45
46         void __iomem *wk_st;
47         void __iomem *wk_en;
48         u32 wk_mask;
49         u32 padconf;
50
51         struct clk *ick;
52         struct clk *fck;
53         int clocked;
54
55         struct plat_serial8250_port *p;
56         struct list_head node;
57         struct platform_device pdev;
58
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
60         int context_valid;
61
62         /* Registers to be saved/restored for OFF-mode */
63         u16 dll;
64         u16 dlh;
65         u16 ier;
66         u16 sysc;
67         u16 scr;
68         u16 wer;
69 #endif
70 };
71
72 static LIST_HEAD(uart_list);
73
74 static struct plat_serial8250_port serial_platform_data0[] = {
75         {
76                 .mapbase        = OMAP_UART1_BASE,
77                 .irq            = 72,
78                 .flags          = UPF_BOOT_AUTOCONF,
79                 .iotype         = UPIO_MEM,
80                 .regshift       = 2,
81                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
82         }, {
83                 .flags          = 0
84         }
85 };
86
87 static struct plat_serial8250_port serial_platform_data1[] = {
88         {
89                 .mapbase        = OMAP_UART2_BASE,
90                 .irq            = 73,
91                 .flags          = UPF_BOOT_AUTOCONF,
92                 .iotype         = UPIO_MEM,
93                 .regshift       = 2,
94                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
95         }, {
96                 .flags          = 0
97         }
98 };
99
100 static struct plat_serial8250_port serial_platform_data2[] = {
101         {
102                 .mapbase        = OMAP_UART3_BASE,
103                 .irq            = 74,
104                 .flags          = UPF_BOOT_AUTOCONF,
105                 .iotype         = UPIO_MEM,
106                 .regshift       = 2,
107                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
108         }, {
109 #ifdef CONFIG_ARCH_OMAP4
110                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART4_BASE),
111                 .mapbase        = OMAP_UART4_BASE,
112                 .irq            = 70,
113                 .flags          = UPF_BOOT_AUTOCONF,
114                 .iotype         = UPIO_MEM,
115                 .regshift       = 2,
116                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
117         }, {
118 #endif
119                 .flags          = 0
120         }
121 };
122
123 #ifdef CONFIG_ARCH_OMAP4
124 static struct plat_serial8250_port serial_platform_data3[] = {
125         {
126                 .mapbase        = OMAP_UART4_BASE,
127                 .irq            = 70,
128                 .flags          = UPF_BOOT_AUTOCONF,
129                 .iotype         = UPIO_MEM,
130                 .regshift       = 2,
131                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
132         }, {
133                 .flags          = 0
134         }
135 };
136 #endif
137 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
138                                            int offset)
139 {
140         offset <<= up->regshift;
141         return (unsigned int)__raw_readb(up->membase + offset);
142 }
143
144 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
145                                     int value)
146 {
147         offset <<= p->regshift;
148         __raw_writeb(value, p->membase + offset);
149 }
150
151 /*
152  * Internal UARTs need to be initialized for the 8250 autoconfig to work
153  * properly. Note that the TX watermark initialization may not be needed
154  * once the 8250.c watermark handling code is merged.
155  */
156 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
157 {
158         struct plat_serial8250_port *p = uart->p;
159
160         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
161         serial_write_reg(p, UART_OMAP_SCR, 0x08);
162         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
163         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
164 }
165
166 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
167
168 static int enable_off_mode; /* to be removed by full off-mode patches */
169
170 static void omap_uart_save_context(struct omap_uart_state *uart)
171 {
172         u16 lcr = 0;
173         struct plat_serial8250_port *p = uart->p;
174
175         if (!enable_off_mode)
176                 return;
177
178         lcr = serial_read_reg(p, UART_LCR);
179         serial_write_reg(p, UART_LCR, 0xBF);
180         uart->dll = serial_read_reg(p, UART_DLL);
181         uart->dlh = serial_read_reg(p, UART_DLM);
182         serial_write_reg(p, UART_LCR, lcr);
183         uart->ier = serial_read_reg(p, UART_IER);
184         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
185         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
186         uart->wer = serial_read_reg(p, UART_OMAP_WER);
187
188         uart->context_valid = 1;
189 }
190
191 static void omap_uart_restore_context(struct omap_uart_state *uart)
192 {
193         u16 efr = 0;
194         struct plat_serial8250_port *p = uart->p;
195
196         if (!enable_off_mode)
197                 return;
198
199         if (!uart->context_valid)
200                 return;
201
202         uart->context_valid = 0;
203
204         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
205         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
206         efr = serial_read_reg(p, UART_EFR);
207         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
208         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
209         serial_write_reg(p, UART_IER, 0x0);
210         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
211         serial_write_reg(p, UART_DLL, uart->dll);
212         serial_write_reg(p, UART_DLM, uart->dlh);
213         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
214         serial_write_reg(p, UART_IER, uart->ier);
215         serial_write_reg(p, UART_FCR, 0xA1);
216         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
217         serial_write_reg(p, UART_EFR, efr);
218         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
219         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
220         serial_write_reg(p, UART_OMAP_WER, uart->wer);
221         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
222         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
223 }
224 #else
225 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
226 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
227 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
228
229 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
230 {
231         if (uart->clocked)
232                 return;
233
234         clk_enable(uart->ick);
235         clk_enable(uart->fck);
236         uart->clocked = 1;
237         omap_uart_restore_context(uart);
238 }
239
240 #ifdef CONFIG_PM
241
242 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
243 {
244         if (!uart->clocked)
245                 return;
246
247         omap_uart_save_context(uart);
248         uart->clocked = 0;
249         clk_disable(uart->ick);
250         clk_disable(uart->fck);
251 }
252
253 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
254 {
255         /* Set wake-enable bit */
256         if (uart->wk_en && uart->wk_mask) {
257                 u32 v = __raw_readl(uart->wk_en);
258                 v |= uart->wk_mask;
259                 __raw_writel(v, uart->wk_en);
260         }
261
262         /* Ensure IOPAD wake-enables are set */
263         if (cpu_is_omap34xx() && uart->padconf) {
264                 u16 v = omap_ctrl_readw(uart->padconf);
265                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
266                 omap_ctrl_writew(v, uart->padconf);
267         }
268 }
269
270 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
271 {
272         /* Clear wake-enable bit */
273         if (uart->wk_en && uart->wk_mask) {
274                 u32 v = __raw_readl(uart->wk_en);
275                 v &= ~uart->wk_mask;
276                 __raw_writel(v, uart->wk_en);
277         }
278
279         /* Ensure IOPAD wake-enables are cleared */
280         if (cpu_is_omap34xx() && uart->padconf) {
281                 u16 v = omap_ctrl_readw(uart->padconf);
282                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
283                 omap_ctrl_writew(v, uart->padconf);
284         }
285 }
286
287 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
288                                           int enable)
289 {
290         struct plat_serial8250_port *p = uart->p;
291         u16 sysc;
292
293         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
294         if (enable)
295                 sysc |= 0x2 << 3;
296         else
297                 sysc |= 0x1 << 3;
298
299         serial_write_reg(p, UART_OMAP_SYSC, sysc);
300 }
301
302 static void omap_uart_block_sleep(struct omap_uart_state *uart)
303 {
304         omap_uart_enable_clocks(uart);
305
306         omap_uart_smart_idle_enable(uart, 0);
307         uart->can_sleep = 0;
308         if (uart->timeout)
309                 mod_timer(&uart->timer, jiffies + uart->timeout);
310         else
311                 del_timer(&uart->timer);
312 }
313
314 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
315 {
316         if (device_may_wakeup(&uart->pdev.dev))
317                 omap_uart_enable_wakeup(uart);
318         else
319                 omap_uart_disable_wakeup(uart);
320
321         if (!uart->clocked)
322                 return;
323
324         omap_uart_smart_idle_enable(uart, 1);
325         uart->can_sleep = 1;
326         del_timer(&uart->timer);
327 }
328
329 static void omap_uart_idle_timer(unsigned long data)
330 {
331         struct omap_uart_state *uart = (struct omap_uart_state *)data;
332
333         omap_uart_allow_sleep(uart);
334 }
335
336 void omap_uart_prepare_idle(int num)
337 {
338         struct omap_uart_state *uart;
339
340         list_for_each_entry(uart, &uart_list, node) {
341                 if (num == uart->num && uart->can_sleep) {
342                         omap_uart_disable_clocks(uart);
343                         return;
344                 }
345         }
346 }
347
348 void omap_uart_resume_idle(int num)
349 {
350         struct omap_uart_state *uart;
351
352         list_for_each_entry(uart, &uart_list, node) {
353                 if (num == uart->num) {
354                         omap_uart_enable_clocks(uart);
355
356                         /* Check for IO pad wakeup */
357                         if (cpu_is_omap34xx() && uart->padconf) {
358                                 u16 p = omap_ctrl_readw(uart->padconf);
359
360                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
361                                         omap_uart_block_sleep(uart);
362                         }
363
364                         /* Check for normal UART wakeup */
365                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
366                                 omap_uart_block_sleep(uart);
367                         return;
368                 }
369         }
370 }
371
372 void omap_uart_prepare_suspend(void)
373 {
374         struct omap_uart_state *uart;
375
376         list_for_each_entry(uart, &uart_list, node) {
377                 omap_uart_allow_sleep(uart);
378         }
379 }
380
381 int omap_uart_can_sleep(void)
382 {
383         struct omap_uart_state *uart;
384         int can_sleep = 1;
385
386         list_for_each_entry(uart, &uart_list, node) {
387                 if (!uart->clocked)
388                         continue;
389
390                 if (!uart->can_sleep) {
391                         can_sleep = 0;
392                         continue;
393                 }
394
395                 /* This UART can now safely sleep. */
396                 omap_uart_allow_sleep(uart);
397         }
398
399         return can_sleep;
400 }
401
402 /**
403  * omap_uart_interrupt()
404  *
405  * This handler is used only to detect that *any* UART interrupt has
406  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
407  * any UART interrupt will trigger the inactivity timer so the
408  * UART will not idle or sleep for its timeout period.
409  *
410  **/
411 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
412 {
413         struct omap_uart_state *uart = dev_id;
414
415         omap_uart_block_sleep(uart);
416
417         return IRQ_NONE;
418 }
419
420 static void omap_uart_idle_init(struct omap_uart_state *uart)
421 {
422         struct plat_serial8250_port *p = uart->p;
423         int ret;
424
425         uart->can_sleep = 0;
426         uart->timeout = DEFAULT_TIMEOUT;
427         setup_timer(&uart->timer, omap_uart_idle_timer,
428                     (unsigned long) uart);
429         mod_timer(&uart->timer, jiffies + uart->timeout);
430         omap_uart_smart_idle_enable(uart, 0);
431
432         if (cpu_is_omap34xx()) {
433                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
434                 u32 wk_mask = 0;
435                 u32 padconf = 0;
436
437                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
438                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
439                 switch (uart->num) {
440                 case 0:
441                         wk_mask = OMAP3430_ST_UART1_MASK;
442                         padconf = 0x182;
443                         break;
444                 case 1:
445                         wk_mask = OMAP3430_ST_UART2_MASK;
446                         padconf = 0x17a;
447                         break;
448                 case 2:
449                         wk_mask = OMAP3430_ST_UART3_MASK;
450                         padconf = 0x19e;
451                         break;
452                 }
453                 uart->wk_mask = wk_mask;
454                 uart->padconf = padconf;
455         } else if (cpu_is_omap24xx()) {
456                 u32 wk_mask = 0;
457
458                 if (cpu_is_omap2430()) {
459                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
460                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
461                 } else if (cpu_is_omap2420()) {
462                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
463                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
464                 }
465                 switch (uart->num) {
466                 case 0:
467                         wk_mask = OMAP24XX_ST_UART1_MASK;
468                         break;
469                 case 1:
470                         wk_mask = OMAP24XX_ST_UART2_MASK;
471                         break;
472                 case 2:
473                         wk_mask = OMAP24XX_ST_UART3_MASK;
474                         break;
475                 }
476                 uart->wk_mask = wk_mask;
477         } else {
478                 uart->wk_en = 0;
479                 uart->wk_st = 0;
480                 uart->wk_mask = 0;
481                 uart->padconf = 0;
482         }
483
484         p->irqflags |= IRQF_SHARED;
485         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
486                           "serial idle", (void *)uart);
487         WARN_ON(ret);
488 }
489
490 void omap_uart_enable_irqs(int enable)
491 {
492         int ret;
493         struct omap_uart_state *uart;
494
495         list_for_each_entry(uart, &uart_list, node) {
496                 if (enable)
497                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
498                                 IRQF_SHARED, "serial idle", (void *)uart);
499                 else
500                         free_irq(uart->p->irq, (void *)uart);
501         }
502 }
503
504 static ssize_t sleep_timeout_show(struct device *dev,
505                                   struct device_attribute *attr,
506                                   char *buf)
507 {
508         struct platform_device *pdev = container_of(dev,
509                                         struct platform_device, dev);
510         struct omap_uart_state *uart = container_of(pdev,
511                                         struct omap_uart_state, pdev);
512
513         return sprintf(buf, "%u\n", uart->timeout / HZ);
514 }
515
516 static ssize_t sleep_timeout_store(struct device *dev,
517                                    struct device_attribute *attr,
518                                    const char *buf, size_t n)
519 {
520         struct platform_device *pdev = container_of(dev,
521                                         struct platform_device, dev);
522         struct omap_uart_state *uart = container_of(pdev,
523                                         struct omap_uart_state, pdev);
524         unsigned int value;
525
526         if (sscanf(buf, "%u", &value) != 1) {
527                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
528                 return -EINVAL;
529         }
530
531         uart->timeout = value * HZ;
532         if (uart->timeout)
533                 mod_timer(&uart->timer, jiffies + uart->timeout);
534         else
535                 /* A zero value means disable timeout feature */
536                 omap_uart_block_sleep(uart);
537
538         return n;
539 }
540
541 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
542 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
543 #else
544 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
545 #define DEV_CREATE_FILE(dev, attr)
546 #endif /* CONFIG_PM */
547
548 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
549         {
550                 .pdev = {
551                         .name                   = "serial8250",
552                         .id                     = PLAT8250_DEV_PLATFORM,
553                         .dev                    = {
554                                 .platform_data  = serial_platform_data0,
555                         },
556                 },
557         }, {
558                 .pdev = {
559                         .name                   = "serial8250",
560                         .id                     = PLAT8250_DEV_PLATFORM1,
561                         .dev                    = {
562                                 .platform_data  = serial_platform_data1,
563                         },
564                 },
565         }, {
566                 .pdev = {
567                         .name                   = "serial8250",
568                         .id                     = PLAT8250_DEV_PLATFORM2,
569                         .dev                    = {
570                                 .platform_data  = serial_platform_data2,
571                         },
572                 },
573         },
574 #ifdef CONFIG_ARCH_OMAP4
575         {
576                 .pdev = {
577                         .name                   = "serial8250",
578                         .id                     = 3,
579                         .dev                    = {
580                                 .platform_data  = serial_platform_data3,
581                         },
582                 },
583         },
584 #endif
585 };
586
587 void __init omap_serial_early_init(void)
588 {
589         int i;
590         char name[16];
591
592         /*
593          * Make sure the serial ports are muxed on at this point.
594          * You have to mux them off in device drivers later on
595          * if not needed.
596          */
597
598         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
599                 struct omap_uart_state *uart = &omap_uart[i];
600                 struct platform_device *pdev = &uart->pdev;
601                 struct device *dev = &pdev->dev;
602                 struct plat_serial8250_port *p = dev->platform_data;
603
604                 /*
605                  * Module 4KB + L4 interconnect 4KB
606                  * Static mapping, never released
607                  */
608                 p->membase = ioremap(p->mapbase, SZ_8K);
609                 if (!p->membase) {
610                         printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
611                         continue;
612                 }
613
614                 sprintf(name, "uart%d_ick", i+1);
615                 uart->ick = clk_get(NULL, name);
616                 if (IS_ERR(uart->ick)) {
617                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
618                         uart->ick = NULL;
619                 }
620
621                 sprintf(name, "uart%d_fck", i+1);
622                 uart->fck = clk_get(NULL, name);
623                 if (IS_ERR(uart->fck)) {
624                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
625                         uart->fck = NULL;
626                 }
627
628                 /* FIXME: Remove this once the clkdev is ready */
629                 if (!cpu_is_omap44xx()) {
630                         if (!uart->ick || !uart->fck)
631                                 continue;
632                 }
633
634                 uart->num = i;
635                 p->private_data = uart;
636                 uart->p = p;
637                 list_add_tail(&uart->node, &uart_list);
638
639                 if (cpu_is_omap44xx())
640                         p->irq += 32;
641
642                 omap_uart_enable_clocks(uart);
643         }
644 }
645
646 void __init omap_serial_init(void)
647 {
648         int i;
649
650         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
651                 struct omap_uart_state *uart = &omap_uart[i];
652                 struct platform_device *pdev = &uart->pdev;
653                 struct device *dev = &pdev->dev;
654
655                 omap_uart_reset(uart);
656                 omap_uart_idle_init(uart);
657
658                 if (WARN_ON(platform_device_register(pdev)))
659                         continue;
660                 if ((cpu_is_omap34xx() && uart->padconf) ||
661                     (uart->wk_en && uart->wk_mask)) {
662                         device_init_wakeup(dev, true);
663                         DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
664                 }
665         }
666 }