OMAP: Remove OMAP_IO_ADDRESS, use OMAP1_IO_ADDRESS and OMAP2_IO_ADDRESS instead
[linux-2.6.git] / arch / arm / mach-omap2 / serial.c
1 /*
2  * arch/arm/mach-omap2/serial.c
3  *
4  * OMAP2 serial support.
5  *
6  * Copyright (C) 2005-2008 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * Major rework for PM support by Kevin Hilman
10  *
11  * Based off of arch/arm/mach-omap/omap1/serial.c
12  *
13  * Copyright (C) 2009 Texas Instruments
14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
15  *
16  * This file is subject to the terms and conditions of the GNU General Public
17  * License. See the file "COPYING" in the main directory of this archive
18  * for more details.
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
25 #include <linux/io.h>
26
27 #include <mach/common.h>
28 #include <mach/board.h>
29 #include <mach/clock.h>
30 #include <mach/control.h>
31
32 #include "prm.h"
33 #include "pm.h"
34 #include "prm-regbits-34xx.h"
35
36 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
37
38 #define DEFAULT_TIMEOUT (5 * HZ)
39
40 struct omap_uart_state {
41         int num;
42         int can_sleep;
43         struct timer_list timer;
44         u32 timeout;
45
46         void __iomem *wk_st;
47         void __iomem *wk_en;
48         u32 wk_mask;
49         u32 padconf;
50
51         struct clk *ick;
52         struct clk *fck;
53         int clocked;
54
55         struct plat_serial8250_port *p;
56         struct list_head node;
57         struct platform_device pdev;
58
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
60         int context_valid;
61
62         /* Registers to be saved/restored for OFF-mode */
63         u16 dll;
64         u16 dlh;
65         u16 ier;
66         u16 sysc;
67         u16 scr;
68         u16 wer;
69 #endif
70 };
71
72 static LIST_HEAD(uart_list);
73
74 static struct plat_serial8250_port serial_platform_data0[] = {
75         {
76                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
77                 .mapbase        = OMAP_UART1_BASE,
78                 .irq            = 72,
79                 .flags          = UPF_BOOT_AUTOCONF,
80                 .iotype         = UPIO_MEM,
81                 .regshift       = 2,
82                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
83         }, {
84                 .flags          = 0
85         }
86 };
87
88 static struct plat_serial8250_port serial_platform_data1[] = {
89         {
90                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
91                 .mapbase        = OMAP_UART2_BASE,
92                 .irq            = 73,
93                 .flags          = UPF_BOOT_AUTOCONF,
94                 .iotype         = UPIO_MEM,
95                 .regshift       = 2,
96                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
97         }, {
98                 .flags          = 0
99         }
100 };
101
102 static struct plat_serial8250_port serial_platform_data2[] = {
103         {
104                 .membase        = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
105                 .mapbase        = OMAP_UART3_BASE,
106                 .irq            = 74,
107                 .flags          = UPF_BOOT_AUTOCONF,
108                 .iotype         = UPIO_MEM,
109                 .regshift       = 2,
110                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
111         }, {
112                 .flags          = 0
113         }
114 };
115
116 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
117                                            int offset)
118 {
119         offset <<= up->regshift;
120         return (unsigned int)__raw_readb(up->membase + offset);
121 }
122
123 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
124                                     int value)
125 {
126         offset <<= p->regshift;
127         __raw_writeb(value, p->membase + offset);
128 }
129
130 /*
131  * Internal UARTs need to be initialized for the 8250 autoconfig to work
132  * properly. Note that the TX watermark initialization may not be needed
133  * once the 8250.c watermark handling code is merged.
134  */
135 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
136 {
137         struct plat_serial8250_port *p = uart->p;
138
139         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
140         serial_write_reg(p, UART_OMAP_SCR, 0x08);
141         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
142         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
143 }
144
145 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
146
147 static int enable_off_mode; /* to be removed by full off-mode patches */
148
149 static void omap_uart_save_context(struct omap_uart_state *uart)
150 {
151         u16 lcr = 0;
152         struct plat_serial8250_port *p = uart->p;
153
154         if (!enable_off_mode)
155                 return;
156
157         lcr = serial_read_reg(p, UART_LCR);
158         serial_write_reg(p, UART_LCR, 0xBF);
159         uart->dll = serial_read_reg(p, UART_DLL);
160         uart->dlh = serial_read_reg(p, UART_DLM);
161         serial_write_reg(p, UART_LCR, lcr);
162         uart->ier = serial_read_reg(p, UART_IER);
163         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
164         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
165         uart->wer = serial_read_reg(p, UART_OMAP_WER);
166
167         uart->context_valid = 1;
168 }
169
170 static void omap_uart_restore_context(struct omap_uart_state *uart)
171 {
172         u16 efr = 0;
173         struct plat_serial8250_port *p = uart->p;
174
175         if (!enable_off_mode)
176                 return;
177
178         if (!uart->context_valid)
179                 return;
180
181         uart->context_valid = 0;
182
183         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
184         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
185         efr = serial_read_reg(p, UART_EFR);
186         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
187         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
188         serial_write_reg(p, UART_IER, 0x0);
189         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
190         serial_write_reg(p, UART_DLL, uart->dll);
191         serial_write_reg(p, UART_DLM, uart->dlh);
192         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
193         serial_write_reg(p, UART_IER, uart->ier);
194         serial_write_reg(p, UART_FCR, 0xA1);
195         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
196         serial_write_reg(p, UART_EFR, efr);
197         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
198         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
199         serial_write_reg(p, UART_OMAP_WER, uart->wer);
200         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
201         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
202 }
203 #else
204 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
205 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
206 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
207
208 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
209 {
210         if (uart->clocked)
211                 return;
212
213         clk_enable(uart->ick);
214         clk_enable(uart->fck);
215         uart->clocked = 1;
216         omap_uart_restore_context(uart);
217 }
218
219 #ifdef CONFIG_PM
220
221 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
222 {
223         if (!uart->clocked)
224                 return;
225
226         omap_uart_save_context(uart);
227         uart->clocked = 0;
228         clk_disable(uart->ick);
229         clk_disable(uart->fck);
230 }
231
232 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
233 {
234         /* Set wake-enable bit */
235         if (uart->wk_en && uart->wk_mask) {
236                 u32 v = __raw_readl(uart->wk_en);
237                 v |= uart->wk_mask;
238                 __raw_writel(v, uart->wk_en);
239         }
240
241         /* Ensure IOPAD wake-enables are set */
242         if (cpu_is_omap34xx() && uart->padconf) {
243                 u16 v = omap_ctrl_readw(uart->padconf);
244                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
245                 omap_ctrl_writew(v, uart->padconf);
246         }
247 }
248
249 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
250 {
251         /* Clear wake-enable bit */
252         if (uart->wk_en && uart->wk_mask) {
253                 u32 v = __raw_readl(uart->wk_en);
254                 v &= ~uart->wk_mask;
255                 __raw_writel(v, uart->wk_en);
256         }
257
258         /* Ensure IOPAD wake-enables are cleared */
259         if (cpu_is_omap34xx() && uart->padconf) {
260                 u16 v = omap_ctrl_readw(uart->padconf);
261                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
262                 omap_ctrl_writew(v, uart->padconf);
263         }
264 }
265
266 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
267                                           int enable)
268 {
269         struct plat_serial8250_port *p = uart->p;
270         u16 sysc;
271
272         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
273         if (enable)
274                 sysc |= 0x2 << 3;
275         else
276                 sysc |= 0x1 << 3;
277
278         serial_write_reg(p, UART_OMAP_SYSC, sysc);
279 }
280
281 static void omap_uart_block_sleep(struct omap_uart_state *uart)
282 {
283         omap_uart_enable_clocks(uart);
284
285         omap_uart_smart_idle_enable(uart, 0);
286         uart->can_sleep = 0;
287         if (uart->timeout)
288                 mod_timer(&uart->timer, jiffies + uart->timeout);
289         else
290                 del_timer(&uart->timer);
291 }
292
293 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
294 {
295         if (device_may_wakeup(&uart->pdev.dev))
296                 omap_uart_enable_wakeup(uart);
297         else
298                 omap_uart_disable_wakeup(uart);
299
300         if (!uart->clocked)
301                 return;
302
303         omap_uart_smart_idle_enable(uart, 1);
304         uart->can_sleep = 1;
305         del_timer(&uart->timer);
306 }
307
308 static void omap_uart_idle_timer(unsigned long data)
309 {
310         struct omap_uart_state *uart = (struct omap_uart_state *)data;
311
312         omap_uart_allow_sleep(uart);
313 }
314
315 void omap_uart_prepare_idle(int num)
316 {
317         struct omap_uart_state *uart;
318
319         list_for_each_entry(uart, &uart_list, node) {
320                 if (num == uart->num && uart->can_sleep) {
321                         omap_uart_disable_clocks(uart);
322                         return;
323                 }
324         }
325 }
326
327 void omap_uart_resume_idle(int num)
328 {
329         struct omap_uart_state *uart;
330
331         list_for_each_entry(uart, &uart_list, node) {
332                 if (num == uart->num) {
333                         omap_uart_enable_clocks(uart);
334
335                         /* Check for IO pad wakeup */
336                         if (cpu_is_omap34xx() && uart->padconf) {
337                                 u16 p = omap_ctrl_readw(uart->padconf);
338
339                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
340                                         omap_uart_block_sleep(uart);
341                         }
342
343                         /* Check for normal UART wakeup */
344                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
345                                 omap_uart_block_sleep(uart);
346                         return;
347                 }
348         }
349 }
350
351 void omap_uart_prepare_suspend(void)
352 {
353         struct omap_uart_state *uart;
354
355         list_for_each_entry(uart, &uart_list, node) {
356                 omap_uart_allow_sleep(uart);
357         }
358 }
359
360 int omap_uart_can_sleep(void)
361 {
362         struct omap_uart_state *uart;
363         int can_sleep = 1;
364
365         list_for_each_entry(uart, &uart_list, node) {
366                 if (!uart->clocked)
367                         continue;
368
369                 if (!uart->can_sleep) {
370                         can_sleep = 0;
371                         continue;
372                 }
373
374                 /* This UART can now safely sleep. */
375                 omap_uart_allow_sleep(uart);
376         }
377
378         return can_sleep;
379 }
380
381 /**
382  * omap_uart_interrupt()
383  *
384  * This handler is used only to detect that *any* UART interrupt has
385  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
386  * any UART interrupt will trigger the inactivity timer so the
387  * UART will not idle or sleep for its timeout period.
388  *
389  **/
390 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
391 {
392         struct omap_uart_state *uart = dev_id;
393
394         omap_uart_block_sleep(uart);
395
396         return IRQ_NONE;
397 }
398
399 static void omap_uart_idle_init(struct omap_uart_state *uart)
400 {
401         struct plat_serial8250_port *p = uart->p;
402         int ret;
403
404         uart->can_sleep = 0;
405         uart->timeout = DEFAULT_TIMEOUT;
406         setup_timer(&uart->timer, omap_uart_idle_timer,
407                     (unsigned long) uart);
408         mod_timer(&uart->timer, jiffies + uart->timeout);
409         omap_uart_smart_idle_enable(uart, 0);
410
411         if (cpu_is_omap34xx()) {
412                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
413                 u32 wk_mask = 0;
414                 u32 padconf = 0;
415
416                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
417                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
418                 switch (uart->num) {
419                 case 0:
420                         wk_mask = OMAP3430_ST_UART1_MASK;
421                         padconf = 0x182;
422                         break;
423                 case 1:
424                         wk_mask = OMAP3430_ST_UART2_MASK;
425                         padconf = 0x17a;
426                         break;
427                 case 2:
428                         wk_mask = OMAP3430_ST_UART3_MASK;
429                         padconf = 0x19e;
430                         break;
431                 }
432                 uart->wk_mask = wk_mask;
433                 uart->padconf = padconf;
434         } else if (cpu_is_omap24xx()) {
435                 u32 wk_mask = 0;
436
437                 if (cpu_is_omap2430()) {
438                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
439                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
440                 } else if (cpu_is_omap2420()) {
441                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
442                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
443                 }
444                 switch (uart->num) {
445                 case 0:
446                         wk_mask = OMAP24XX_ST_UART1_MASK;
447                         break;
448                 case 1:
449                         wk_mask = OMAP24XX_ST_UART2_MASK;
450                         break;
451                 case 2:
452                         wk_mask = OMAP24XX_ST_UART3_MASK;
453                         break;
454                 }
455                 uart->wk_mask = wk_mask;
456         } else {
457                 uart->wk_en = 0;
458                 uart->wk_st = 0;
459                 uart->wk_mask = 0;
460                 uart->padconf = 0;
461         }
462
463         p->flags |= UPF_SHARE_IRQ;
464         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
465                           "serial idle", (void *)uart);
466         WARN_ON(ret);
467 }
468
469 void omap_uart_enable_irqs(int enable)
470 {
471         int ret;
472         struct omap_uart_state *uart;
473
474         list_for_each_entry(uart, &uart_list, node) {
475                 if (enable)
476                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
477                                 IRQF_SHARED, "serial idle", (void *)uart);
478                 else
479                         free_irq(uart->p->irq, (void *)uart);
480         }
481 }
482
483 static ssize_t sleep_timeout_show(struct device *dev,
484                                   struct device_attribute *attr,
485                                   char *buf)
486 {
487         struct platform_device *pdev = container_of(dev,
488                                         struct platform_device, dev);
489         struct omap_uart_state *uart = container_of(pdev,
490                                         struct omap_uart_state, pdev);
491
492         return sprintf(buf, "%u\n", uart->timeout / HZ);
493 }
494
495 static ssize_t sleep_timeout_store(struct device *dev,
496                                    struct device_attribute *attr,
497                                    const char *buf, size_t n)
498 {
499         struct platform_device *pdev = container_of(dev,
500                                         struct platform_device, dev);
501         struct omap_uart_state *uart = container_of(pdev,
502                                         struct omap_uart_state, pdev);
503         unsigned int value;
504
505         if (sscanf(buf, "%u", &value) != 1) {
506                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
507                 return -EINVAL;
508         }
509
510         uart->timeout = value * HZ;
511         if (uart->timeout)
512                 mod_timer(&uart->timer, jiffies + uart->timeout);
513         else
514                 /* A zero value means disable timeout feature */
515                 omap_uart_block_sleep(uart);
516
517         return n;
518 }
519
520 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
521 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
522 #else
523 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
524 #define DEV_CREATE_FILE(dev, attr)
525 #endif /* CONFIG_PM */
526
527 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
528         {
529                 .pdev = {
530                         .name                   = "serial8250",
531                         .id                     = PLAT8250_DEV_PLATFORM,
532                         .dev                    = {
533                                 .platform_data  = serial_platform_data0,
534                         },
535                 },
536         }, {
537                 .pdev = {
538                         .name                   = "serial8250",
539                         .id                     = PLAT8250_DEV_PLATFORM1,
540                         .dev                    = {
541                                 .platform_data  = serial_platform_data1,
542                         },
543                 },
544         }, {
545                 .pdev = {
546                         .name                   = "serial8250",
547                         .id                     = PLAT8250_DEV_PLATFORM2,
548                         .dev                    = {
549                                 .platform_data  = serial_platform_data2,
550                         },
551                 },
552         },
553 };
554
555 void __init omap_serial_init(void)
556 {
557         int i;
558         const struct omap_uart_config *info;
559         char name[16];
560
561         /*
562          * Make sure the serial ports are muxed on at this point.
563          * You have to mux them off in device drivers later on
564          * if not needed.
565          */
566
567         info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
568
569         if (info == NULL)
570                 return;
571
572         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
573                 struct omap_uart_state *uart = &omap_uart[i];
574                 struct platform_device *pdev = &uart->pdev;
575                 struct device *dev = &pdev->dev;
576                 struct plat_serial8250_port *p = dev->platform_data;
577
578                 if (!(info->enabled_uarts & (1 << i))) {
579                         p->membase = NULL;
580                         p->mapbase = 0;
581                         continue;
582                 }
583
584                 sprintf(name, "uart%d_ick", i+1);
585                 uart->ick = clk_get(NULL, name);
586                 if (IS_ERR(uart->ick)) {
587                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
588                         uart->ick = NULL;
589                 }
590
591                 sprintf(name, "uart%d_fck", i+1);
592                 uart->fck = clk_get(NULL, name);
593                 if (IS_ERR(uart->fck)) {
594                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
595                         uart->fck = NULL;
596                 }
597
598                 if (!uart->ick || !uart->fck)
599                         continue;
600
601                 uart->num = i;
602                 p->private_data = uart;
603                 uart->p = p;
604                 list_add_tail(&uart->node, &uart_list);
605
606                 if (cpu_is_omap44xx())
607                         p->irq += 32;
608
609                 omap_uart_enable_clocks(uart);
610                 omap_uart_reset(uart);
611                 omap_uart_idle_init(uart);
612
613                 if (WARN_ON(platform_device_register(pdev)))
614                         continue;
615                 if ((cpu_is_omap34xx() && uart->padconf) ||
616                     (uart->wk_en && uart->wk_mask)) {
617                         device_init_wakeup(dev, true);
618                         DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
619                 }
620         }
621 }