Merge branch 'for-davem' of ssh://master.kernel.org/pub/scm/linux/kernel/git/linville...
[linux-2.6.git] / arch / arm / mach-omap2 / prcm_mpu44xx.h
1 /*
2  * OMAP44xx PRCM MPU instance offset macros
3  *
4  * Copyright (C) 2010 Texas Instruments, Inc.
5  * Copyright (C) 2010 Nokia Corporation
6  *
7  * Paul Walmsley (paul@pwsan.com)
8  * Rajendra Nayak (rnayak@ti.com)
9  * Benoit Cousson (b-cousson@ti.com)
10  *
11  * This file is automatically generated from the OMAP hardware databases.
12  * We respectfully ask that any modifications to this file be coordinated
13  * with the public linux-omap@vger.kernel.org mailing list and the
14  * authors above to ensure that the autogeneration scripts are kept
15  * up-to-date with the file contents.
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License version 2 as
19  * published by the Free Software Foundation.
20  *
21  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22  *     or "OMAP4430".
23  */
24
25 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
26 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
27
28 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
29
30 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
31         OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
32
33 /* PRCM_MPU instances */
34
35 #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST  0x0000
36 #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST       0x0200
37 #define OMAP4430_PRCM_MPU_CPU0_INST             0x0400
38 #define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
39
40 /* PRCM_MPU clockdomain register offsets (from instance start) */
41 #define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS       0x0018
42 #define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS       0x0018
43
44
45 /*
46  * PRCM_MPU
47  *
48  * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
49  * point of view the PRCM_MPU is a single entity. It shares the same
50  * programming model as the global PRCM and thus can be assimilate as two new
51  * MOD inside the PRCM
52  */
53
54 /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
55 #define OMAP4_REVISION_PRCM_OFFSET                      0x0000
56 #define OMAP4430_REVISION_PRCM                          OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57
58 /* PRCM_MPU.DEVICE_PRM register offsets */
59 #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET                 0x0000
60 #define OMAP4430_PRCM_MPU_PRM_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
61 #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET           0x0004
62 #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT               OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
63
64 /* PRCM_MPU.CPU0 register offsets */
65 #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET                  0x0000
66 #define OMAP4430_PM_CPU0_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
67 #define OMAP4_PM_CPU0_PWRSTST_OFFSET                    0x0004
68 #define OMAP4430_PM_CPU0_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
69 #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET               0x0008
70 #define OMAP4430_RM_CPU0_CPU0_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
71 #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET               0x000c
72 #define OMAP4430_RM_CPU0_CPU0_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
73 #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET                 0x0010
74 #define OMAP4430_RM_CPU0_CPU0_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
75 #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET               0x0014
76 #define OMAP4430_CM_CPU0_CPU0_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
77 #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET                  0x0018
78 #define OMAP4430_CM_CPU0_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
79
80 /* PRCM_MPU.CPU1 register offsets */
81 #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET                  0x0000
82 #define OMAP4430_PM_CPU1_PWRSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
83 #define OMAP4_PM_CPU1_PWRSTST_OFFSET                    0x0004
84 #define OMAP4430_PM_CPU1_PWRSTST                        OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
85 #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET               0x0008
86 #define OMAP4430_RM_CPU1_CPU1_CONTEXT                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
87 #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET               0x000c
88 #define OMAP4430_RM_CPU1_CPU1_RSTCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
89 #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET                 0x0010
90 #define OMAP4430_RM_CPU1_CPU1_RSTST                     OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
91 #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET               0x0014
92 #define OMAP4430_CM_CPU1_CPU1_CLKCTRL                   OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
93 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET                  0x0018
94 #define OMAP4430_CM_CPU1_CLKSTCTRL                      OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
95
96 /* Function prototypes */
97 # ifndef __ASSEMBLER__
98 extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
99 extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
100 extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
101                                             s16 idx);
102 # endif
103
104 #endif