Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / arm / mach-omap2 / prcm.c
1 /*
2  * linux/arch/arm/mach-omap2/prcm.c
3  *
4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  *
8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
9  *
10  * Copyright (C) 2007 Texas Instruments, Inc.
11  * Rajendra Nayak <rnayak@ti.com>
12  *
13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License version 2 as
17  * published by the Free Software Foundation.
18  */
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/delay.h>
24
25 #include <plat/common.h>
26 #include <plat/prcm.h>
27 #include <plat/irqs.h>
28 #include <plat/control.h>
29
30 #include "clock.h"
31 #include "cm.h"
32 #include "prm.h"
33 #include "prm-regbits-24xx.h"
34
35 static void __iomem *prm_base;
36 static void __iomem *cm_base;
37 static void __iomem *cm2_base;
38
39 #define MAX_MODULE_ENABLE_WAIT          100000
40
41 struct omap3_prcm_regs {
42         u32 control_padconf_sys_nirq;
43         u32 iva2_cm_clksel1;
44         u32 iva2_cm_clksel2;
45         u32 cm_sysconfig;
46         u32 sgx_cm_clksel;
47         u32 wkup_cm_clksel;
48         u32 dss_cm_clksel;
49         u32 cam_cm_clksel;
50         u32 per_cm_clksel;
51         u32 emu_cm_clksel;
52         u32 emu_cm_clkstctrl;
53         u32 pll_cm_autoidle2;
54         u32 pll_cm_clksel4;
55         u32 pll_cm_clksel5;
56         u32 pll_cm_clken;
57         u32 pll_cm_clken2;
58         u32 cm_polctrl;
59         u32 iva2_cm_fclken;
60         u32 iva2_cm_clken_pll;
61         u32 core_cm_fclken1;
62         u32 core_cm_fclken3;
63         u32 sgx_cm_fclken;
64         u32 wkup_cm_fclken;
65         u32 dss_cm_fclken;
66         u32 cam_cm_fclken;
67         u32 per_cm_fclken;
68         u32 usbhost_cm_fclken;
69         u32 core_cm_iclken1;
70         u32 core_cm_iclken2;
71         u32 core_cm_iclken3;
72         u32 sgx_cm_iclken;
73         u32 wkup_cm_iclken;
74         u32 dss_cm_iclken;
75         u32 cam_cm_iclken;
76         u32 per_cm_iclken;
77         u32 usbhost_cm_iclken;
78         u32 iva2_cm_autiidle2;
79         u32 mpu_cm_autoidle2;
80         u32 pll_cm_autoidle;
81         u32 iva2_cm_clkstctrl;
82         u32 mpu_cm_clkstctrl;
83         u32 core_cm_clkstctrl;
84         u32 sgx_cm_clkstctrl;
85         u32 dss_cm_clkstctrl;
86         u32 cam_cm_clkstctrl;
87         u32 per_cm_clkstctrl;
88         u32 neon_cm_clkstctrl;
89         u32 usbhost_cm_clkstctrl;
90         u32 core_cm_autoidle1;
91         u32 core_cm_autoidle2;
92         u32 core_cm_autoidle3;
93         u32 wkup_cm_autoidle;
94         u32 dss_cm_autoidle;
95         u32 cam_cm_autoidle;
96         u32 per_cm_autoidle;
97         u32 usbhost_cm_autoidle;
98         u32 sgx_cm_sleepdep;
99         u32 dss_cm_sleepdep;
100         u32 cam_cm_sleepdep;
101         u32 per_cm_sleepdep;
102         u32 usbhost_cm_sleepdep;
103         u32 cm_clkout_ctrl;
104         u32 prm_clkout_ctrl;
105         u32 sgx_pm_wkdep;
106         u32 dss_pm_wkdep;
107         u32 cam_pm_wkdep;
108         u32 per_pm_wkdep;
109         u32 neon_pm_wkdep;
110         u32 usbhost_pm_wkdep;
111         u32 core_pm_mpugrpsel1;
112         u32 iva2_pm_ivagrpsel1;
113         u32 core_pm_mpugrpsel3;
114         u32 core_pm_ivagrpsel3;
115         u32 wkup_pm_mpugrpsel;
116         u32 wkup_pm_ivagrpsel;
117         u32 per_pm_mpugrpsel;
118         u32 per_pm_ivagrpsel;
119         u32 wkup_pm_wken;
120 };
121
122 struct omap3_prcm_regs prcm_context;
123
124 u32 omap_prcm_get_reset_sources(void)
125 {
126         /* XXX This presumably needs modification for 34XX */
127         return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
128 }
129 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
130
131 /* Resets clock rates and reboots the system. Only called from system.h */
132 void omap_prcm_arch_reset(char mode)
133 {
134         s16 prcm_offs;
135         omap2_clk_prepare_for_reboot();
136
137         if (cpu_is_omap24xx())
138                 prcm_offs = WKUP_MOD;
139         else if (cpu_is_omap34xx()) {
140                 u32 l;
141
142                 prcm_offs = OMAP3430_GR_MOD;
143                 l = ('B' << 24) | ('M' << 16) | mode;
144                 /* Reserve the first word in scratchpad for communicating
145                  * with the boot ROM. A pointer to a data structure
146                  * describing the boot process can be stored there,
147                  * cf. OMAP34xx TRM, Initialization / Software Booting
148                  * Configuration. */
149                 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
150         } else
151                 WARN_ON(1);
152
153         prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
154 }
155
156 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
157 {
158         BUG_ON(!base);
159         return __raw_readl(base + module + reg);
160 }
161
162 static inline void __omap_prcm_write(u32 value, void __iomem *base,
163                                                 s16 module, u16 reg)
164 {
165         BUG_ON(!base);
166         __raw_writel(value, base + module + reg);
167 }
168
169 /* Read a register in a PRM module */
170 u32 prm_read_mod_reg(s16 module, u16 idx)
171 {
172         return __omap_prcm_read(prm_base, module, idx);
173 }
174
175 /* Write into a register in a PRM module */
176 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
177 {
178         __omap_prcm_write(val, prm_base, module, idx);
179 }
180
181 /* Read-modify-write a register in a PRM module. Caller must lock */
182 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
183 {
184         u32 v;
185
186         v = prm_read_mod_reg(module, idx);
187         v &= ~mask;
188         v |= bits;
189         prm_write_mod_reg(v, module, idx);
190
191         return v;
192 }
193
194 /* Read a register in a CM module */
195 u32 cm_read_mod_reg(s16 module, u16 idx)
196 {
197         return __omap_prcm_read(cm_base, module, idx);
198 }
199
200 /* Write into a register in a CM module */
201 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
202 {
203         __omap_prcm_write(val, cm_base, module, idx);
204 }
205
206 /* Read-modify-write a register in a CM module. Caller must lock */
207 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
208 {
209         u32 v;
210
211         v = cm_read_mod_reg(module, idx);
212         v &= ~mask;
213         v |= bits;
214         cm_write_mod_reg(v, module, idx);
215
216         return v;
217 }
218
219 /**
220  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
221  * @reg: physical address of module IDLEST register
222  * @mask: value to mask against to determine if the module is active
223  * @name: name of the clock (for printk)
224  *
225  * Returns 1 if the module indicated readiness in time, or 0 if it
226  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
227  */
228 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
229 {
230         int i = 0;
231         int ena = 0;
232
233         /*
234          * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
235          * 34xx reverses this, just to keep us on our toes
236          */
237         if (cpu_is_omap24xx())
238                 ena = mask;
239         else if (cpu_is_omap34xx())
240                 ena = 0;
241         else
242                 BUG();
243
244         /* Wait for lock */
245         omap_test_timeout(((__raw_readl(reg) & mask) == ena),
246                           MAX_MODULE_ENABLE_WAIT, i);
247
248         if (i < MAX_MODULE_ENABLE_WAIT)
249                 pr_debug("cm: Module associated with clock %s ready after %d "
250                          "loops\n", name, i);
251         else
252                 pr_err("cm: Module associated with clock %s didn't enable in "
253                        "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
254
255         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
256 };
257
258 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
259 {
260         prm_base = omap2_globals->prm;
261         cm_base = omap2_globals->cm;
262         cm2_base = omap2_globals->cm2;
263 }
264
265 #ifdef CONFIG_ARCH_OMAP3
266 void omap3_prcm_save_context(void)
267 {
268         prcm_context.control_padconf_sys_nirq =
269                          omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
270         prcm_context.iva2_cm_clksel1 =
271                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
272         prcm_context.iva2_cm_clksel2 =
273                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
274         prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
275         prcm_context.sgx_cm_clksel =
276                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
277         prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
278         prcm_context.dss_cm_clksel =
279                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
280         prcm_context.cam_cm_clksel =
281                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
282         prcm_context.per_cm_clksel =
283                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
284         prcm_context.emu_cm_clksel =
285                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
286         prcm_context.emu_cm_clkstctrl =
287                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
288         prcm_context.pll_cm_autoidle2 =
289                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
290         prcm_context.pll_cm_clksel4 =
291                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
292         prcm_context.pll_cm_clksel5 =
293                          cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
294         prcm_context.pll_cm_clken =
295                         cm_read_mod_reg(PLL_MOD, CM_CLKEN);
296         prcm_context.pll_cm_clken2 =
297                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
298         prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
299         prcm_context.iva2_cm_fclken =
300                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
301         prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
302                         OMAP3430_CM_CLKEN_PLL);
303         prcm_context.core_cm_fclken1 =
304                          cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
305         prcm_context.core_cm_fclken3 =
306                          cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
307         prcm_context.sgx_cm_fclken =
308                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
309         prcm_context.wkup_cm_fclken =
310                          cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
311         prcm_context.dss_cm_fclken =
312                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
313         prcm_context.cam_cm_fclken =
314                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
315         prcm_context.per_cm_fclken =
316                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
317         prcm_context.usbhost_cm_fclken =
318                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
319         prcm_context.core_cm_iclken1 =
320                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
321         prcm_context.core_cm_iclken2 =
322                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
323         prcm_context.core_cm_iclken3 =
324                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
325         prcm_context.sgx_cm_iclken =
326                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
327         prcm_context.wkup_cm_iclken =
328                          cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
329         prcm_context.dss_cm_iclken =
330                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
331         prcm_context.cam_cm_iclken =
332                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
333         prcm_context.per_cm_iclken =
334                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
335         prcm_context.usbhost_cm_iclken =
336                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
337         prcm_context.iva2_cm_autiidle2 =
338                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
339         prcm_context.mpu_cm_autoidle2 =
340                          cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
341         prcm_context.pll_cm_autoidle =
342                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
343         prcm_context.iva2_cm_clkstctrl =
344                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
345         prcm_context.mpu_cm_clkstctrl =
346                          cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
347         prcm_context.core_cm_clkstctrl =
348                          cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
349         prcm_context.sgx_cm_clkstctrl =
350                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
351         prcm_context.dss_cm_clkstctrl =
352                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
353         prcm_context.cam_cm_clkstctrl =
354                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
355         prcm_context.per_cm_clkstctrl =
356                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
357         prcm_context.neon_cm_clkstctrl =
358                          cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
359         prcm_context.usbhost_cm_clkstctrl =
360                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
361         prcm_context.core_cm_autoidle1 =
362                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
363         prcm_context.core_cm_autoidle2 =
364                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
365         prcm_context.core_cm_autoidle3 =
366                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
367         prcm_context.wkup_cm_autoidle =
368                          cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
369         prcm_context.dss_cm_autoidle =
370                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
371         prcm_context.cam_cm_autoidle =
372                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
373         prcm_context.per_cm_autoidle =
374                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
375         prcm_context.usbhost_cm_autoidle =
376                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
377         prcm_context.sgx_cm_sleepdep =
378                  cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
379         prcm_context.dss_cm_sleepdep =
380                  cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
381         prcm_context.cam_cm_sleepdep =
382                  cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
383         prcm_context.per_cm_sleepdep =
384                  cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
385         prcm_context.usbhost_cm_sleepdep =
386                  cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
387         prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
388                  OMAP3_CM_CLKOUT_CTRL_OFFSET);
389         prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
390                 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
391         prcm_context.sgx_pm_wkdep =
392                  prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
393         prcm_context.dss_pm_wkdep =
394                  prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
395         prcm_context.cam_pm_wkdep =
396                  prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
397         prcm_context.per_pm_wkdep =
398                  prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
399         prcm_context.neon_pm_wkdep =
400                  prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
401         prcm_context.usbhost_pm_wkdep =
402                  prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
403         prcm_context.core_pm_mpugrpsel1 =
404                  prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
405         prcm_context.iva2_pm_ivagrpsel1 =
406                  prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
407         prcm_context.core_pm_mpugrpsel3 =
408                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
409         prcm_context.core_pm_ivagrpsel3 =
410                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
411         prcm_context.wkup_pm_mpugrpsel =
412                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
413         prcm_context.wkup_pm_ivagrpsel =
414                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
415         prcm_context.per_pm_mpugrpsel =
416                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
417         prcm_context.per_pm_ivagrpsel =
418                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
419         prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
420         return;
421 }
422
423 void omap3_prcm_restore_context(void)
424 {
425         omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
426                                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
427         cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
428                                          CM_CLKSEL1);
429         cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
430                                          CM_CLKSEL2);
431         __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
432         cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
433                                          CM_CLKSEL);
434         cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
435         cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
436                                          CM_CLKSEL);
437         cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
438                                          CM_CLKSEL);
439         cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
440                                          CM_CLKSEL);
441         cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
442                                          CM_CLKSEL1);
443         cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
444                                          CM_CLKSTCTRL);
445         cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
446                                          CM_AUTOIDLE2);
447         cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
448                                         OMAP3430ES2_CM_CLKSEL4);
449         cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
450                                          OMAP3430ES2_CM_CLKSEL5);
451         cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
452         cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
453                                         OMAP3430ES2_CM_CLKEN2);
454         __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
455         cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
456                                          CM_FCLKEN);
457         cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
458                                         OMAP3430_CM_CLKEN_PLL);
459         cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
460         cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
461                                          OMAP3430ES2_CM_FCLKEN3);
462         cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
463                                          CM_FCLKEN);
464         cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
465         cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
466                                          CM_FCLKEN);
467         cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
468                                          CM_FCLKEN);
469         cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
470                                          CM_FCLKEN);
471         cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
472                                          OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
473         cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
474         cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
475         cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
476         cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
477                                         CM_ICLKEN);
478         cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
479         cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
480                                         CM_ICLKEN);
481         cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
482                                         CM_ICLKEN);
483         cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
484                                         CM_ICLKEN);
485         cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
486                                         OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
487         cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
488                                         CM_AUTOIDLE2);
489         cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
490         cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
491         cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
492                                         CM_CLKSTCTRL);
493         cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
494         cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
495                                         CM_CLKSTCTRL);
496         cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
497                                         CM_CLKSTCTRL);
498         cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
499                                         CM_CLKSTCTRL);
500         cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
501                                         CM_CLKSTCTRL);
502         cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
503                                         CM_CLKSTCTRL);
504         cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
505                                         CM_CLKSTCTRL);
506         cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
507                                         OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
508         cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
509                                         CM_AUTOIDLE1);
510         cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
511                                         CM_AUTOIDLE2);
512         cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
513                                         CM_AUTOIDLE3);
514         cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
515         cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
516                                         CM_AUTOIDLE);
517         cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
518                                         CM_AUTOIDLE);
519         cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
520                                         CM_AUTOIDLE);
521         cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
522                                         OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
523         cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
524                                         OMAP3430_CM_SLEEPDEP);
525         cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
526                                         OMAP3430_CM_SLEEPDEP);
527         cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
528                                         OMAP3430_CM_SLEEPDEP);
529         cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
530                                         OMAP3430_CM_SLEEPDEP);
531         cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
532                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
533         cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
534                                         OMAP3_CM_CLKOUT_CTRL_OFFSET);
535         prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
536                                         OMAP3_PRM_CLKOUT_CTRL_OFFSET);
537         prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
538                                         PM_WKDEP);
539         prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
540                                         PM_WKDEP);
541         prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
542                                         PM_WKDEP);
543         prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
544                                         PM_WKDEP);
545         prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
546                                         PM_WKDEP);
547         prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
548                                         OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
549         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
550                                         OMAP3430_PM_MPUGRPSEL1);
551         prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
552                                         OMAP3430_PM_IVAGRPSEL1);
553         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
554                                         OMAP3430ES2_PM_MPUGRPSEL3);
555         prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
556                                         OMAP3430ES2_PM_IVAGRPSEL3);
557         prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
558                                         OMAP3430_PM_MPUGRPSEL);
559         prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
560                                         OMAP3430_PM_IVAGRPSEL);
561         prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
562                                         OMAP3430_PM_MPUGRPSEL);
563         prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
564                                          OMAP3430_PM_IVAGRPSEL);
565         prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
566         return;
567 }
568 #endif