Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / arm / mach-omap2 / powerdomains34xx.h
1 /*
2  * OMAP34XX powerdomain definitions
3  *
4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
5  * Copyright (C) 2007-2008 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  * Debugging and integration fixes by Jouni Högander
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14
15 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
16 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
17
18 /*
19  * N.B. If powerdomains are added or removed from this file, update
20  * the array in mach-omap2/powerdomains.h.
21  */
22
23 #include <plat/powerdomain.h>
24
25 #include "prcm-common.h"
26 #include "prm.h"
27 #include "prm-regbits-34xx.h"
28 #include "cm.h"
29 #include "cm-regbits-34xx.h"
30
31 /*
32  * 34XX-specific powerdomains, dependencies
33  */
34
35 #ifdef CONFIG_ARCH_OMAP34XX
36
37 /*
38  * 3430: PM_WKDEP_{PER,USBHOST}: CORE, IVA2, MPU, WKUP
39  * (USBHOST is ES2 only)
40  */
41 static struct pwrdm_dep per_usbhost_wkdeps[] = {
42         {
43                 .pwrdm_name = "core_pwrdm",
44                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
45         },
46         {
47                 .pwrdm_name = "iva2_pwrdm",
48                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
49         },
50         {
51                 .pwrdm_name = "mpu_pwrdm",
52                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
53         },
54         {
55                 .pwrdm_name = "wkup_pwrdm",
56                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
57         },
58         { NULL },
59 };
60
61 /*
62  * 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER
63  */
64 static struct pwrdm_dep mpu_34xx_wkdeps[] = {
65         {
66                 .pwrdm_name = "core_pwrdm",
67                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
68         },
69         {
70                 .pwrdm_name = "iva2_pwrdm",
71                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
72         },
73         {
74                 .pwrdm_name = "dss_pwrdm",
75                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
76         },
77         {
78                 .pwrdm_name = "per_pwrdm",
79                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
80         },
81         { NULL },
82 };
83
84 /*
85  * 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER
86  */
87 static struct pwrdm_dep iva2_wkdeps[] = {
88         {
89                 .pwrdm_name = "core_pwrdm",
90                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
91         },
92         {
93                 .pwrdm_name = "mpu_pwrdm",
94                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
95         },
96         {
97                 .pwrdm_name = "wkup_pwrdm",
98                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
99         },
100         {
101                 .pwrdm_name = "dss_pwrdm",
102                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
103         },
104         {
105                 .pwrdm_name = "per_pwrdm",
106                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
107         },
108         { NULL },
109 };
110
111
112 /* 3430 PM_WKDEP_{CAM,DSS}: IVA2, MPU, WKUP */
113 static struct pwrdm_dep cam_dss_wkdeps[] = {
114         {
115                 .pwrdm_name = "iva2_pwrdm",
116                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
117         },
118         {
119                 .pwrdm_name = "mpu_pwrdm",
120                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
121         },
122         {
123                 .pwrdm_name = "wkup_pwrdm",
124                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
125         },
126         { NULL },
127 };
128
129 /* 3430: PM_WKDEP_NEON: MPU */
130 static struct pwrdm_dep neon_wkdeps[] = {
131         {
132                 .pwrdm_name = "mpu_pwrdm",
133                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
134         },
135         { NULL },
136 };
137
138
139 /* Sleep dependency source arrays for 34xx-specific pwrdms - 34XX only */
140
141 /*
142  * 3430: CM_SLEEPDEP_{DSS,PER}: MPU, IVA
143  * 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA
144  */
145 static struct pwrdm_dep dss_per_usbhost_sleepdeps[] = {
146         {
147                 .pwrdm_name = "mpu_pwrdm",
148                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
149         },
150         {
151                 .pwrdm_name = "iva2_pwrdm",
152                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
153         },
154         { NULL },
155 };
156
157
158 /*
159  * Powerdomains
160  */
161
162 static struct powerdomain iva2_pwrdm = {
163         .name             = "iva2_pwrdm",
164         .prcm_offs        = OMAP3430_IVA2_MOD,
165         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
166         .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
167         .wkdep_srcs       = iva2_wkdeps,
168         .pwrsts           = PWRSTS_OFF_RET_ON,
169         .pwrsts_logic_ret = PWRSTS_OFF_RET,
170         .banks            = 4,
171         .pwrsts_mem_ret   = {
172                 [0] = PWRSTS_OFF_RET,
173                 [1] = PWRSTS_OFF_RET,
174                 [2] = PWRSTS_OFF_RET,
175                 [3] = PWRSTS_OFF_RET,
176         },
177         .pwrsts_mem_on    = {
178                 [0] = PWRDM_POWER_ON,
179                 [1] = PWRDM_POWER_ON,
180                 [2] = PWRSTS_OFF_ON,
181                 [3] = PWRDM_POWER_ON,
182         },
183 };
184
185 static struct powerdomain mpu_34xx_pwrdm = {
186         .name             = "mpu_pwrdm",
187         .prcm_offs        = MPU_MOD,
188         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
189         .dep_bit          = OMAP3430_EN_MPU_SHIFT,
190         .wkdep_srcs       = mpu_34xx_wkdeps,
191         .pwrsts           = PWRSTS_OFF_RET_ON,
192         .pwrsts_logic_ret = PWRSTS_OFF_RET,
193         .flags            = PWRDM_HAS_MPU_QUIRK,
194         .banks            = 1,
195         .pwrsts_mem_ret   = {
196                 [0] = PWRSTS_OFF_RET,
197         },
198         .pwrsts_mem_on    = {
199                 [0] = PWRSTS_OFF_ON,
200         },
201 };
202
203 /* No wkdeps or sleepdeps for 34xx core apparently */
204 static struct powerdomain core_34xx_pre_es3_1_pwrdm = {
205         .name             = "core_pwrdm",
206         .prcm_offs        = CORE_MOD,
207         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
208                                            CHIP_IS_OMAP3430ES2 |
209                                            CHIP_IS_OMAP3430ES3_0),
210         .pwrsts           = PWRSTS_OFF_RET_ON,
211         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
212         .banks            = 2,
213         .pwrsts_mem_ret   = {
214                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
215                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
216         },
217         .pwrsts_mem_on    = {
218                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
219                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
220         },
221 };
222
223 /* No wkdeps or sleepdeps for 34xx core apparently */
224 static struct powerdomain core_34xx_es3_1_pwrdm = {
225         .name             = "core_pwrdm",
226         .prcm_offs        = CORE_MOD,
227         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
228         .pwrsts           = PWRSTS_OFF_RET_ON,
229         .dep_bit          = OMAP3430_EN_CORE_SHIFT,
230         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
231         .banks            = 2,
232         .pwrsts_mem_ret   = {
233                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
234                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
235         },
236         .pwrsts_mem_on    = {
237                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
238                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
239         },
240 };
241
242 /* Another case of bit name collisions between several registers: EN_DSS */
243 static struct powerdomain dss_pwrdm = {
244         .name             = "dss_pwrdm",
245         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
246         .prcm_offs        = OMAP3430_DSS_MOD,
247         .dep_bit          = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
248         .wkdep_srcs       = cam_dss_wkdeps,
249         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
250         .pwrsts           = PWRSTS_OFF_RET_ON,
251         .pwrsts_logic_ret = PWRDM_POWER_RET,
252         .banks            = 1,
253         .pwrsts_mem_ret   = {
254                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
255         },
256         .pwrsts_mem_on    = {
257                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
258         },
259 };
260
261 /*
262  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
263  * possible SGX powerstate, the SGX device itself does not support
264  * retention.
265  */
266 static struct powerdomain sgx_pwrdm = {
267         .name             = "sgx_pwrdm",
268         .prcm_offs        = OMAP3430ES2_SGX_MOD,
269         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
270         .wkdep_srcs       = gfx_sgx_wkdeps,
271         .sleepdep_srcs    = cam_gfx_sleepdeps,
272         /* XXX This is accurate for 3430 SGX, but what about GFX? */
273         .pwrsts           = PWRSTS_OFF_ON,
274         .pwrsts_logic_ret = PWRDM_POWER_RET,
275         .banks            = 1,
276         .pwrsts_mem_ret   = {
277                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
278         },
279         .pwrsts_mem_on    = {
280                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
281         },
282 };
283
284 static struct powerdomain cam_pwrdm = {
285         .name             = "cam_pwrdm",
286         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
287         .prcm_offs        = OMAP3430_CAM_MOD,
288         .wkdep_srcs       = cam_dss_wkdeps,
289         .sleepdep_srcs    = cam_gfx_sleepdeps,
290         .pwrsts           = PWRSTS_OFF_RET_ON,
291         .pwrsts_logic_ret = PWRDM_POWER_RET,
292         .banks            = 1,
293         .pwrsts_mem_ret   = {
294                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
295         },
296         .pwrsts_mem_on    = {
297                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
298         },
299 };
300
301 static struct powerdomain per_pwrdm = {
302         .name             = "per_pwrdm",
303         .prcm_offs        = OMAP3430_PER_MOD,
304         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
305         .dep_bit          = OMAP3430_EN_PER_SHIFT,
306         .wkdep_srcs       = per_usbhost_wkdeps,
307         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
308         .pwrsts           = PWRSTS_OFF_RET_ON,
309         .pwrsts_logic_ret = PWRSTS_OFF_RET,
310         .banks            = 1,
311         .pwrsts_mem_ret   = {
312                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
313         },
314         .pwrsts_mem_on    = {
315                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
316         },
317 };
318
319 static struct powerdomain emu_pwrdm = {
320         .name           = "emu_pwrdm",
321         .prcm_offs      = OMAP3430_EMU_MOD,
322         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
323 };
324
325 static struct powerdomain neon_pwrdm = {
326         .name             = "neon_pwrdm",
327         .prcm_offs        = OMAP3430_NEON_MOD,
328         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
329         .wkdep_srcs       = neon_wkdeps,
330         .pwrsts           = PWRSTS_OFF_RET_ON,
331         .pwrsts_logic_ret = PWRDM_POWER_RET,
332 };
333
334 static struct powerdomain usbhost_pwrdm = {
335         .name             = "usbhost_pwrdm",
336         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
337         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
338         .wkdep_srcs       = per_usbhost_wkdeps,
339         .sleepdep_srcs    = dss_per_usbhost_sleepdeps,
340         .pwrsts           = PWRSTS_OFF_RET_ON,
341         .pwrsts_logic_ret = PWRDM_POWER_RET,
342         /*
343          * REVISIT: Enabling usb host save and restore mechanism seems to
344          * leave the usb host domain permanently in ACTIVE mode after
345          * changing the usb host power domain state from OFF to active once.
346          * Disabling for now.
347          */
348         /*.flags          = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
349         .banks            = 1,
350         .pwrsts_mem_ret   = {
351                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
352         },
353         .pwrsts_mem_on    = {
354                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
355         },
356 };
357
358 static struct powerdomain dpll1_pwrdm = {
359         .name           = "dpll1_pwrdm",
360         .prcm_offs      = MPU_MOD,
361         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
362 };
363
364 static struct powerdomain dpll2_pwrdm = {
365         .name           = "dpll2_pwrdm",
366         .prcm_offs      = OMAP3430_IVA2_MOD,
367         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
368 };
369
370 static struct powerdomain dpll3_pwrdm = {
371         .name           = "dpll3_pwrdm",
372         .prcm_offs      = PLL_MOD,
373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
374 };
375
376 static struct powerdomain dpll4_pwrdm = {
377         .name           = "dpll4_pwrdm",
378         .prcm_offs      = PLL_MOD,
379         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
380 };
381
382 static struct powerdomain dpll5_pwrdm = {
383         .name           = "dpll5_pwrdm",
384         .prcm_offs      = PLL_MOD,
385         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
386 };
387
388
389 #endif    /* CONFIG_ARCH_OMAP34XX */
390
391
392 #endif