Disintegrate asm/system.h for ARM
[linux-2.6.git] / arch / arm / mach-omap2 / pm44xx.c
1 /*
2  * OMAP4 Power Management Routines
3  *
4  * Copyright (C) 2010-2011 Texas Instruments, Inc.
5  * Rajendra Nayak <rnayak@ti.com>
6  * Santosh Shilimkar <santosh.shilimkar@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/pm.h>
14 #include <linux/suspend.h>
15 #include <linux/module.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19 #include <asm/system_misc.h>
20
21 #include "common.h"
22 #include "clockdomain.h"
23 #include "powerdomain.h"
24 #include "pm.h"
25
26 struct power_state {
27         struct powerdomain *pwrdm;
28         u32 next_state;
29 #ifdef CONFIG_SUSPEND
30         u32 saved_state;
31         u32 saved_logic_state;
32 #endif
33         struct list_head node;
34 };
35
36 static LIST_HEAD(pwrst_list);
37
38 #ifdef CONFIG_SUSPEND
39 static int omap4_pm_suspend(void)
40 {
41         struct power_state *pwrst;
42         int state, ret = 0;
43         u32 cpu_id = smp_processor_id();
44
45         /* Save current powerdomain state */
46         list_for_each_entry(pwrst, &pwrst_list, node) {
47                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
48                 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
49         }
50
51         /* Set targeted power domain states by suspend */
52         list_for_each_entry(pwrst, &pwrst_list, node) {
53                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
54                 pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
55         }
56
57         /*
58          * For MPUSS to hit power domain retention(CSWR or OSWR),
59          * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
60          * since CPU power domain CSWR is not supported by hardware
61          * Only master CPU follows suspend path. All other CPUs follow
62          * CPU hotplug path in system wide suspend. On OMAP4, CPU power
63          * domain CSWR is not supported by hardware.
64          * More details can be found in OMAP4430 TRM section 4.3.4.2.
65          */
66         omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
67
68         /* Restore next powerdomain state */
69         list_for_each_entry(pwrst, &pwrst_list, node) {
70                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
71                 if (state > pwrst->next_state) {
72                         pr_info("Powerdomain (%s) didn't enter "
73                                "target state %d\n",
74                                pwrst->pwrdm->name, pwrst->next_state);
75                         ret = -1;
76                 }
77                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
78                 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
79         }
80         if (ret)
81                 pr_crit("Could not enter target state in pm_suspend\n");
82         else
83                 pr_info("Successfully put all powerdomains to target state\n");
84
85         return 0;
86 }
87
88 static int omap4_pm_enter(suspend_state_t suspend_state)
89 {
90         int ret = 0;
91
92         switch (suspend_state) {
93         case PM_SUSPEND_STANDBY:
94         case PM_SUSPEND_MEM:
95                 ret = omap4_pm_suspend();
96                 break;
97         default:
98                 ret = -EINVAL;
99         }
100
101         return ret;
102 }
103
104 static int omap4_pm_begin(suspend_state_t state)
105 {
106         disable_hlt();
107         return 0;
108 }
109
110 static void omap4_pm_end(void)
111 {
112         enable_hlt();
113         return;
114 }
115
116 static const struct platform_suspend_ops omap_pm_ops = {
117         .begin          = omap4_pm_begin,
118         .end            = omap4_pm_end,
119         .enter          = omap4_pm_enter,
120         .valid          = suspend_valid_only_mem,
121 };
122 #endif /* CONFIG_SUSPEND */
123
124 /*
125  * Enable hardware supervised mode for all clockdomains if it's
126  * supported. Initiate sleep transition for other clockdomains, if
127  * they are not used
128  */
129 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
130 {
131         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
132                 clkdm_allow_idle(clkdm);
133         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
134                         atomic_read(&clkdm->usecount) == 0)
135                 clkdm_sleep(clkdm);
136         return 0;
137 }
138
139
140 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
141 {
142         struct power_state *pwrst;
143
144         if (!pwrdm->pwrsts)
145                 return 0;
146
147         /*
148          * Skip CPU0 and CPU1 power domains. CPU1 is programmed
149          * through hotplug path and CPU0 explicitly programmed
150          * further down in the code path
151          */
152         if (!strncmp(pwrdm->name, "cpu", 3))
153                 return 0;
154
155         /*
156          * FIXME: Remove this check when core retention is supported
157          * Only MPUSS power domain is added in the list.
158          */
159         if (strcmp(pwrdm->name, "mpu_pwrdm"))
160                 return 0;
161
162         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
163         if (!pwrst)
164                 return -ENOMEM;
165
166         pwrst->pwrdm = pwrdm;
167         pwrst->next_state = PWRDM_POWER_RET;
168         list_add(&pwrst->node, &pwrst_list);
169
170         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
171 }
172
173 /**
174  * omap_default_idle - OMAP4 default ilde routine.'
175  *
176  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
177  * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
178  * by secondary CPU with CONFIG_CPUIDLE.
179  */
180 static void omap_default_idle(void)
181 {
182         local_irq_disable();
183         local_fiq_disable();
184
185         omap_do_wfi();
186
187         local_fiq_enable();
188         local_irq_enable();
189 }
190
191 /**
192  * omap4_pm_init - Init routine for OMAP4 PM
193  *
194  * Initializes all powerdomain and clockdomain target states
195  * and all PRCM settings.
196  */
197 static int __init omap4_pm_init(void)
198 {
199         int ret;
200         struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
201         struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
202
203         if (!cpu_is_omap44xx())
204                 return -ENODEV;
205
206         if (omap_rev() == OMAP4430_REV_ES1_0) {
207                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
208                 return -ENODEV;
209         }
210
211         pr_err("Power Management for TI OMAP4.\n");
212
213         ret = pwrdm_for_each(pwrdms_setup, NULL);
214         if (ret) {
215                 pr_err("Failed to setup powerdomains\n");
216                 goto err2;
217         }
218
219         /*
220          * The dynamic dependency between MPUSS -> MEMIF and
221          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
222          * expected. The hardware recommendation is to enable static
223          * dependencies for these to avoid system lock ups or random crashes.
224          */
225         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
226         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
227         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
228         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
229         l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
230         ducati_clkdm = clkdm_lookup("ducati_clkdm");
231         if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
232                 (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
233                 goto err2;
234
235         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
236         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
237         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
238         ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
239         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
240         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
241         if (ret) {
242                 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
243                                 "wakeup dependency\n");
244                 goto err2;
245         }
246
247         ret = omap4_mpuss_init();
248         if (ret) {
249                 pr_err("Failed to initialise OMAP4 MPUSS\n");
250                 goto err2;
251         }
252
253         (void) clkdm_for_each(clkdms_setup, NULL);
254
255 #ifdef CONFIG_SUSPEND
256         suspend_set_ops(&omap_pm_ops);
257 #endif /* CONFIG_SUSPEND */
258
259         /* Overwrite the default arch_idle() */
260         pm_idle = omap_default_idle;
261
262         omap4_idle_init();
263
264 err2:
265         return ret;
266 }
267 late_initcall(omap4_pm_init);