91e0b1c9b76c6c594f4e4d3a200d090f32f5401a
[linux-2.6.git] / arch / arm / mach-omap2 / pm44xx.c
1 /*
2  * OMAP4 Power Management Routines
3  *
4  * Copyright (C) 2010-2011 Texas Instruments, Inc.
5  * Rajendra Nayak <rnayak@ti.com>
6  * Santosh Shilimkar <santosh.shilimkar@ti.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12
13 #include <linux/pm.h>
14 #include <linux/suspend.h>
15 #include <linux/module.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
19
20 #include "common.h"
21 #include "clockdomain.h"
22 #include "powerdomain.h"
23 #include "pm.h"
24
25 struct power_state {
26         struct powerdomain *pwrdm;
27         u32 next_state;
28 #ifdef CONFIG_SUSPEND
29         u32 saved_state;
30         u32 saved_logic_state;
31 #endif
32         struct list_head node;
33 };
34
35 static LIST_HEAD(pwrst_list);
36
37 #ifdef CONFIG_SUSPEND
38 static int omap4_pm_suspend(void)
39 {
40         struct power_state *pwrst;
41         int state, ret = 0;
42         u32 cpu_id = smp_processor_id();
43
44         /* Save current powerdomain state */
45         list_for_each_entry(pwrst, &pwrst_list, node) {
46                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
47                 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
48         }
49
50         /* Set targeted power domain states by suspend */
51         list_for_each_entry(pwrst, &pwrst_list, node) {
52                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
53                 pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
54         }
55
56         /*
57          * For MPUSS to hit power domain retention(CSWR or OSWR),
58          * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
59          * since CPU power domain CSWR is not supported by hardware
60          * Only master CPU follows suspend path. All other CPUs follow
61          * CPU hotplug path in system wide suspend. On OMAP4, CPU power
62          * domain CSWR is not supported by hardware.
63          * More details can be found in OMAP4430 TRM section 4.3.4.2.
64          */
65         omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
66
67         /* Restore next powerdomain state */
68         list_for_each_entry(pwrst, &pwrst_list, node) {
69                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
70                 if (state > pwrst->next_state) {
71                         pr_info("Powerdomain (%s) didn't enter "
72                                "target state %d\n",
73                                pwrst->pwrdm->name, pwrst->next_state);
74                         ret = -1;
75                 }
76                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
77                 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
78         }
79         if (ret)
80                 pr_crit("Could not enter target state in pm_suspend\n");
81         else
82                 pr_info("Successfully put all powerdomains to target state\n");
83
84         return 0;
85 }
86 #endif /* CONFIG_SUSPEND */
87
88 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
89 {
90         struct power_state *pwrst;
91
92         if (!pwrdm->pwrsts)
93                 return 0;
94
95         /*
96          * Skip CPU0 and CPU1 power domains. CPU1 is programmed
97          * through hotplug path and CPU0 explicitly programmed
98          * further down in the code path
99          */
100         if (!strncmp(pwrdm->name, "cpu", 3))
101                 return 0;
102
103         /*
104          * FIXME: Remove this check when core retention is supported
105          * Only MPUSS power domain is added in the list.
106          */
107         if (strcmp(pwrdm->name, "mpu_pwrdm"))
108                 return 0;
109
110         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
111         if (!pwrst)
112                 return -ENOMEM;
113
114         pwrst->pwrdm = pwrdm;
115         pwrst->next_state = PWRDM_POWER_RET;
116         list_add(&pwrst->node, &pwrst_list);
117
118         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
119 }
120
121 /**
122  * omap_default_idle - OMAP4 default ilde routine.'
123  *
124  * Implements OMAP4 memory, IO ordering requirements which can't be addressed
125  * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
126  * by secondary CPU with CONFIG_CPUIDLE.
127  */
128 static void omap_default_idle(void)
129 {
130         local_fiq_disable();
131
132         omap_do_wfi();
133
134         local_fiq_enable();
135 }
136
137 /**
138  * omap4_pm_init - Init routine for OMAP4 PM
139  *
140  * Initializes all powerdomain and clockdomain target states
141  * and all PRCM settings.
142  */
143 static int __init omap4_pm_init(void)
144 {
145         int ret;
146         struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
147         struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
148
149         if (!cpu_is_omap44xx())
150                 return -ENODEV;
151
152         if (omap_rev() == OMAP4430_REV_ES1_0) {
153                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
154                 return -ENODEV;
155         }
156
157         pr_err("Power Management for TI OMAP4.\n");
158
159         ret = pwrdm_for_each(pwrdms_setup, NULL);
160         if (ret) {
161                 pr_err("Failed to setup powerdomains\n");
162                 goto err2;
163         }
164
165         /*
166          * The dynamic dependency between MPUSS -> MEMIF and
167          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
168          * expected. The hardware recommendation is to enable static
169          * dependencies for these to avoid system lock ups or random crashes.
170          */
171         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
172         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
173         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
174         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
175         l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
176         ducati_clkdm = clkdm_lookup("ducati_clkdm");
177         if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
178                 (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
179                 goto err2;
180
181         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
182         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
183         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
184         ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
185         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
186         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
187         if (ret) {
188                 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
189                                 "wakeup dependency\n");
190                 goto err2;
191         }
192
193         ret = omap4_mpuss_init();
194         if (ret) {
195                 pr_err("Failed to initialise OMAP4 MPUSS\n");
196                 goto err2;
197         }
198
199         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
200
201 #ifdef CONFIG_SUSPEND
202         omap_pm_suspend = omap4_pm_suspend;
203 #endif
204
205         /* Overwrite the default cpu_do_idle() */
206         arm_pm_idle = omap_default_idle;
207
208         omap4_idle_init();
209
210 err2:
211         return ret;
212 }
213 late_initcall(omap4_pm_init);