Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm...
[linux-2.6.git] / arch / arm / mach-omap2 / pm34xx.c
1 /*
2  * OMAP3 Power Management Routines
3  *
4  * Copyright (C) 2006-2008 Nokia Corporation
5  * Tony Lindgren <tony@atomide.com>
6  * Jouni Hogander
7  *
8  * Copyright (C) 2007 Texas Instruments, Inc.
9  * Rajendra Nayak <rnayak@ti.com>
10  *
11  * Copyright (C) 2005 Texas Instruments, Inc.
12  * Richard Woodruff <r-woodruff2@ti.com>
13  *
14  * Based on pm.c for omap1
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/pm.h>
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <trace/events/power.h>
32
33 #include <asm/suspend.h>
34 #include <asm/system_misc.h>
35
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/sdrc.h>
40 #include <plat/prcm.h>
41 #include <plat/gpmc.h>
42 #include <plat/dma.h>
43
44 #include "common.h"
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
48
49 #include "prm2xxx_3xxx.h"
50 #include "pm.h"
51 #include "sdrc.h"
52 #include "control.h"
53
54 /* pm34xx errata defined in pm.h */
55 u16 pm34xx_errata;
56
57 struct power_state {
58         struct powerdomain *pwrdm;
59         u32 next_state;
60 #ifdef CONFIG_SUSPEND
61         u32 saved_state;
62 #endif
63         struct list_head node;
64 };
65
66 static LIST_HEAD(pwrst_list);
67
68 static int (*_omap_save_secure_sram)(u32 *addr);
69 void (*omap3_do_wfi_sram)(void);
70
71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72 static struct powerdomain *core_pwrdm, *per_pwrdm;
73 static struct powerdomain *cam_pwrdm;
74
75 static void omap3_enable_io_chain(void)
76 {
77         int timeout = 0;
78
79         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
80                                    PM_WKEN);
81         /* Do a readback to assure write has been done */
82         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
83
84         while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
85                  OMAP3430_ST_IO_CHAIN_MASK)) {
86                 timeout++;
87                 if (timeout > 1000) {
88                         pr_err("Wake up daisy chain activation failed.\n");
89                         return;
90                 }
91                 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
92                                            WKUP_MOD, PM_WKEN);
93         }
94 }
95
96 static void omap3_disable_io_chain(void)
97 {
98         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
99                                      PM_WKEN);
100 }
101
102 static void omap3_core_save_context(void)
103 {
104         omap3_ctrl_save_padconf();
105
106         /*
107          * Force write last pad into memory, as this can fail in some
108          * cases according to errata 1.157, 1.185
109          */
110         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
111                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
112
113         /* Save the Interrupt controller context */
114         omap_intc_save_context();
115         /* Save the GPMC context */
116         omap3_gpmc_save_context();
117         /* Save the system control module context, padconf already save above*/
118         omap3_control_save_context();
119         omap_dma_global_context_save();
120 }
121
122 static void omap3_core_restore_context(void)
123 {
124         /* Restore the control module context, padconf restored by h/w */
125         omap3_control_restore_context();
126         /* Restore the GPMC context */
127         omap3_gpmc_restore_context();
128         /* Restore the interrupt controller context */
129         omap_intc_restore_context();
130         omap_dma_global_context_restore();
131 }
132
133 /*
134  * FIXME: This function should be called before entering off-mode after
135  * OMAP3 secure services have been accessed. Currently it is only called
136  * once during boot sequence, but this works as we are not using secure
137  * services.
138  */
139 static void omap3_save_secure_ram_context(void)
140 {
141         u32 ret;
142         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
143
144         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
145                 /*
146                  * MPU next state must be set to POWER_ON temporarily,
147                  * otherwise the WFI executed inside the ROM code
148                  * will hang the system.
149                  */
150                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
151                 ret = _omap_save_secure_sram((u32 *)
152                                 __pa(omap3_secure_ram_storage));
153                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
154                 /* Following is for error tracking, it should not happen */
155                 if (ret) {
156                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
157                                 ret);
158                         while (1)
159                                 ;
160                 }
161         }
162 }
163
164 /*
165  * PRCM Interrupt Handler Helper Function
166  *
167  * The purpose of this function is to clear any wake-up events latched
168  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
169  * may occur whilst attempting to clear a PM_WKST_x register and thus
170  * set another bit in this register. A while loop is used to ensure
171  * that any peripheral wake-up events occurring while attempting to
172  * clear the PM_WKST_x are detected and cleared.
173  */
174 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
175 {
176         u32 wkst, fclk, iclk, clken;
177         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
178         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
179         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
180         u16 grpsel_off = (regs == 3) ?
181                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
182         int c = 0;
183
184         wkst = omap2_prm_read_mod_reg(module, wkst_off);
185         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
186         wkst &= ~ignore_bits;
187         if (wkst) {
188                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
189                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
190                 while (wkst) {
191                         clken = wkst;
192                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
193                         /*
194                          * For USBHOST, we don't know whether HOST1 or
195                          * HOST2 woke us up, so enable both f-clocks
196                          */
197                         if (module == OMAP3430ES2_USBHOST_MOD)
198                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
199                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
200                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
201                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
202                         wkst &= ~ignore_bits;
203                         c++;
204                 }
205                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
206                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
207         }
208
209         return c;
210 }
211
212 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
213 {
214         int c;
215
216         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
217                 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
218
219         return c ? IRQ_HANDLED : IRQ_NONE;
220 }
221
222 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
223 {
224         int c;
225
226         /*
227          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
228          * these are handled in a separate handler to avoid acking
229          * IO events before parsing in mux code
230          */
231         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
232                 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
233         c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
234         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
235         if (omap_rev() > OMAP3430_REV_ES1_0) {
236                 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
237                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
238         }
239
240         return c ? IRQ_HANDLED : IRQ_NONE;
241 }
242
243 static void omap34xx_save_context(u32 *save)
244 {
245         u32 val;
246
247         /* Read Auxiliary Control Register */
248         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
249         *save++ = 1;
250         *save++ = val;
251
252         /* Read L2 AUX ctrl register */
253         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
254         *save++ = 1;
255         *save++ = val;
256 }
257
258 static int omap34xx_do_sram_idle(unsigned long save_state)
259 {
260         omap34xx_cpu_suspend(save_state);
261         return 0;
262 }
263
264 void omap_sram_idle(void)
265 {
266         /* Variable to tell what needs to be saved and restored
267          * in omap_sram_idle*/
268         /* save_state = 0 => Nothing to save and restored */
269         /* save_state = 1 => Only L1 and logic lost */
270         /* save_state = 2 => Only L2 lost */
271         /* save_state = 3 => L1, L2 and logic lost */
272         int save_state = 0;
273         int mpu_next_state = PWRDM_POWER_ON;
274         int per_next_state = PWRDM_POWER_ON;
275         int core_next_state = PWRDM_POWER_ON;
276         int per_going_off;
277         int core_prev_state, per_prev_state;
278         u32 sdrc_pwr = 0;
279
280         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
281         switch (mpu_next_state) {
282         case PWRDM_POWER_ON:
283         case PWRDM_POWER_RET:
284                 /* No need to save context */
285                 save_state = 0;
286                 break;
287         case PWRDM_POWER_OFF:
288                 save_state = 3;
289                 break;
290         default:
291                 /* Invalid state */
292                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
293                 return;
294         }
295
296         /* NEON control */
297         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
298                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
299
300         /* Enable IO-PAD and IO-CHAIN wakeups */
301         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
302         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
303         if (omap3_has_io_wakeup() &&
304             (per_next_state < PWRDM_POWER_ON ||
305              core_next_state < PWRDM_POWER_ON)) {
306                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
307                 if (omap3_has_io_chain_ctrl())
308                         omap3_enable_io_chain();
309         }
310
311         pwrdm_pre_transition();
312
313         /* PER */
314         if (per_next_state < PWRDM_POWER_ON) {
315                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
316                 omap2_gpio_prepare_for_idle(per_going_off);
317         }
318
319         /* CORE */
320         if (core_next_state < PWRDM_POWER_ON) {
321                 if (core_next_state == PWRDM_POWER_OFF) {
322                         omap3_core_save_context();
323                         omap3_cm_save_context();
324                 }
325         }
326
327         omap3_intc_prepare_idle();
328
329         /*
330          * On EMU/HS devices ROM code restores a SRDC value
331          * from scratchpad which has automatic self refresh on timeout
332          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
333          * Hence store/restore the SDRC_POWER register here.
334          */
335         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
336             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
337              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
338             core_next_state == PWRDM_POWER_OFF)
339                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
340
341         /*
342          * omap3_arm_context is the location where some ARM context
343          * get saved. The rest is placed on the stack, and restored
344          * from there before resuming.
345          */
346         if (save_state)
347                 omap34xx_save_context(omap3_arm_context);
348         if (save_state == 1 || save_state == 3)
349                 cpu_suspend(save_state, omap34xx_do_sram_idle);
350         else
351                 omap34xx_do_sram_idle(save_state);
352
353         /* Restore normal SDRC POWER settings */
354         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
355             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
356              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
357             core_next_state == PWRDM_POWER_OFF)
358                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
359
360         /* CORE */
361         if (core_next_state < PWRDM_POWER_ON) {
362                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
363                 if (core_prev_state == PWRDM_POWER_OFF) {
364                         omap3_core_restore_context();
365                         omap3_cm_restore_context();
366                         omap3_sram_restore_context();
367                         omap2_sms_restore_context();
368                 }
369                 if (core_next_state == PWRDM_POWER_OFF)
370                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
371                                                OMAP3430_GR_MOD,
372                                                OMAP3_PRM_VOLTCTRL_OFFSET);
373         }
374         omap3_intc_resume_idle();
375
376         pwrdm_post_transition();
377
378         /* PER */
379         if (per_next_state < PWRDM_POWER_ON) {
380                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
381                 omap2_gpio_resume_after_idle();
382         }
383
384         /* Disable IO-PAD and IO-CHAIN wakeup */
385         if (omap3_has_io_wakeup() &&
386             (per_next_state < PWRDM_POWER_ON ||
387              core_next_state < PWRDM_POWER_ON)) {
388                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
389                                              PM_WKEN);
390                 if (omap3_has_io_chain_ctrl())
391                         omap3_disable_io_chain();
392         }
393
394         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
395 }
396
397 static void omap3_pm_idle(void)
398 {
399         local_fiq_disable();
400
401         if (omap_irq_pending())
402                 goto out;
403
404         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
405         trace_cpu_idle(1, smp_processor_id());
406
407         omap_sram_idle();
408
409         trace_power_end(smp_processor_id());
410         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
411
412 out:
413         local_fiq_enable();
414 }
415
416 #ifdef CONFIG_SUSPEND
417 static int omap3_pm_suspend(void)
418 {
419         struct power_state *pwrst;
420         int state, ret = 0;
421
422         /* Read current next_pwrsts */
423         list_for_each_entry(pwrst, &pwrst_list, node)
424                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
425         /* Set ones wanted by suspend */
426         list_for_each_entry(pwrst, &pwrst_list, node) {
427                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
428                         goto restore;
429                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
430                         goto restore;
431         }
432
433         omap3_intc_suspend();
434
435         omap_sram_idle();
436
437 restore:
438         /* Restore next_pwrsts */
439         list_for_each_entry(pwrst, &pwrst_list, node) {
440                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
441                 if (state > pwrst->next_state) {
442                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
443                                "target state %d\n",
444                                pwrst->pwrdm->name, pwrst->next_state);
445                         ret = -1;
446                 }
447                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
448         }
449         if (ret)
450                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
451         else
452                 printk(KERN_INFO "Successfully put all powerdomains "
453                        "to target state\n");
454
455         return ret;
456 }
457
458 #endif /* CONFIG_SUSPEND */
459
460
461 /**
462  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
463  *                   retention
464  *
465  * In cases where IVA2 is activated by bootcode, it may prevent
466  * full-chip retention or off-mode because it is not idle.  This
467  * function forces the IVA2 into idle state so it can go
468  * into retention/off and thus allow full-chip retention/off.
469  *
470  **/
471 static void __init omap3_iva_idle(void)
472 {
473         /* ensure IVA2 clock is disabled */
474         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
475
476         /* if no clock activity, nothing else to do */
477         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
478               OMAP3430_CLKACTIVITY_IVA2_MASK))
479                 return;
480
481         /* Reset IVA2 */
482         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
483                           OMAP3430_RST2_IVA2_MASK |
484                           OMAP3430_RST3_IVA2_MASK,
485                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
486
487         /* Enable IVA2 clock */
488         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
489                          OMAP3430_IVA2_MOD, CM_FCLKEN);
490
491         /* Set IVA2 boot mode to 'idle' */
492         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
493                          OMAP343X_CONTROL_IVA2_BOOTMOD);
494
495         /* Un-reset IVA2 */
496         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
497
498         /* Disable IVA2 clock */
499         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
500
501         /* Reset IVA2 */
502         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
503                           OMAP3430_RST2_IVA2_MASK |
504                           OMAP3430_RST3_IVA2_MASK,
505                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
506 }
507
508 static void __init omap3_d2d_idle(void)
509 {
510         u16 mask, padconf;
511
512         /* In a stand alone OMAP3430 where there is not a stacked
513          * modem for the D2D Idle Ack and D2D MStandby must be pulled
514          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
515          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
516         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
517         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
518         padconf |= mask;
519         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
520
521         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
522         padconf |= mask;
523         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
524
525         /* reset modem */
526         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
527                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
528                           CORE_MOD, OMAP2_RM_RSTCTRL);
529         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
530 }
531
532 static void __init prcm_setup_regs(void)
533 {
534         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
535                                         OMAP3630_EN_UART4_MASK : 0;
536         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
537                                         OMAP3630_GRPSEL_UART4_MASK : 0;
538
539         /* XXX This should be handled by hwmod code or SCM init code */
540         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
541
542         /*
543          * Enable control of expternal oscillator through
544          * sys_clkreq. In the long run clock framework should
545          * take care of this.
546          */
547         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
548                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
549                              OMAP3430_GR_MOD,
550                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
551
552         /* setup wakup source */
553         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
554                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
555                           WKUP_MOD, PM_WKEN);
556         /* No need to write EN_IO, that is always enabled */
557         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
558                           OMAP3430_GRPSEL_GPT1_MASK |
559                           OMAP3430_GRPSEL_GPT12_MASK,
560                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
561
562         /* Enable PM_WKEN to support DSS LPR */
563         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
564                                 OMAP3430_DSS_MOD, PM_WKEN);
565
566         /* Enable wakeups in PER */
567         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
568                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
569                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
570                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
571                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
572                           OMAP3430_EN_MCBSP4_MASK,
573                           OMAP3430_PER_MOD, PM_WKEN);
574         /* and allow them to wake up MPU */
575         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
576                           OMAP3430_GRPSEL_GPIO2_MASK |
577                           OMAP3430_GRPSEL_GPIO3_MASK |
578                           OMAP3430_GRPSEL_GPIO4_MASK |
579                           OMAP3430_GRPSEL_GPIO5_MASK |
580                           OMAP3430_GRPSEL_GPIO6_MASK |
581                           OMAP3430_GRPSEL_UART3_MASK |
582                           OMAP3430_GRPSEL_MCBSP2_MASK |
583                           OMAP3430_GRPSEL_MCBSP3_MASK |
584                           OMAP3430_GRPSEL_MCBSP4_MASK,
585                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
586
587         /* Don't attach IVA interrupts */
588         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
589         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
590         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
591         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
592
593         /* Clear any pending 'reset' flags */
594         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
595         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
596         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
597         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
598         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
599         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
600         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
601
602         /* Clear any pending PRCM interrupts */
603         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
604
605         omap3_iva_idle();
606         omap3_d2d_idle();
607 }
608
609 void omap3_pm_off_mode_enable(int enable)
610 {
611         struct power_state *pwrst;
612         u32 state;
613
614         if (enable)
615                 state = PWRDM_POWER_OFF;
616         else
617                 state = PWRDM_POWER_RET;
618
619         list_for_each_entry(pwrst, &pwrst_list, node) {
620                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
621                                 pwrst->pwrdm == core_pwrdm &&
622                                 state == PWRDM_POWER_OFF) {
623                         pwrst->next_state = PWRDM_POWER_RET;
624                         pr_warn("%s: Core OFF disabled due to errata i583\n",
625                                 __func__);
626                 } else {
627                         pwrst->next_state = state;
628                 }
629                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
630         }
631 }
632
633 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
634 {
635         struct power_state *pwrst;
636
637         list_for_each_entry(pwrst, &pwrst_list, node) {
638                 if (pwrst->pwrdm == pwrdm)
639                         return pwrst->next_state;
640         }
641         return -EINVAL;
642 }
643
644 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
645 {
646         struct power_state *pwrst;
647
648         list_for_each_entry(pwrst, &pwrst_list, node) {
649                 if (pwrst->pwrdm == pwrdm) {
650                         pwrst->next_state = state;
651                         return 0;
652                 }
653         }
654         return -EINVAL;
655 }
656
657 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
658 {
659         struct power_state *pwrst;
660
661         if (!pwrdm->pwrsts)
662                 return 0;
663
664         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
665         if (!pwrst)
666                 return -ENOMEM;
667         pwrst->pwrdm = pwrdm;
668         pwrst->next_state = PWRDM_POWER_RET;
669         list_add(&pwrst->node, &pwrst_list);
670
671         if (pwrdm_has_hdwr_sar(pwrdm))
672                 pwrdm_enable_hdwr_sar(pwrdm);
673
674         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
675 }
676
677 /*
678  * Push functions to SRAM
679  *
680  * The minimum set of functions is pushed to SRAM for execution:
681  * - omap3_do_wfi for erratum i581 WA,
682  * - save_secure_ram_context for security extensions.
683  */
684 void omap_push_sram_idle(void)
685 {
686         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
687
688         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
689                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
690                                 save_secure_ram_context_sz);
691 }
692
693 static void __init pm_errata_configure(void)
694 {
695         if (cpu_is_omap3630()) {
696                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
697                 /* Enable the l2 cache toggling in sleep logic */
698                 enable_omap3630_toggle_l2_on_restore();
699                 if (omap_rev() < OMAP3630_REV_ES1_2)
700                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
701         }
702 }
703
704 static int __init omap3_pm_init(void)
705 {
706         struct power_state *pwrst, *tmp;
707         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
708         int ret;
709
710         if (!cpu_is_omap34xx())
711                 return -ENODEV;
712
713         if (!omap3_has_io_chain_ctrl())
714                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
715
716         pm_errata_configure();
717
718         /* XXX prcm_setup_regs needs to be before enabling hw
719          * supervised mode for powerdomains */
720         prcm_setup_regs();
721
722         ret = request_irq(omap_prcm_event_to_irq("wkup"),
723                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
724
725         if (ret) {
726                 pr_err("pm: Failed to request pm_wkup irq\n");
727                 goto err1;
728         }
729
730         /* IO interrupt is shared with mux code */
731         ret = request_irq(omap_prcm_event_to_irq("io"),
732                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
733                 omap3_pm_init);
734
735         if (ret) {
736                 pr_err("pm: Failed to request pm_io irq\n");
737                 goto err1;
738         }
739
740         ret = pwrdm_for_each(pwrdms_setup, NULL);
741         if (ret) {
742                 printk(KERN_ERR "Failed to setup powerdomains\n");
743                 goto err2;
744         }
745
746         (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
747
748         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
749         if (mpu_pwrdm == NULL) {
750                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
751                 goto err2;
752         }
753
754         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
755         per_pwrdm = pwrdm_lookup("per_pwrdm");
756         core_pwrdm = pwrdm_lookup("core_pwrdm");
757         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
758
759         neon_clkdm = clkdm_lookup("neon_clkdm");
760         mpu_clkdm = clkdm_lookup("mpu_clkdm");
761         per_clkdm = clkdm_lookup("per_clkdm");
762         core_clkdm = clkdm_lookup("core_clkdm");
763
764 #ifdef CONFIG_SUSPEND
765         omap_pm_suspend = omap3_pm_suspend;
766 #endif
767
768         arm_pm_idle = omap3_pm_idle;
769         omap3_idle_init();
770
771         /*
772          * RTA is disabled during initialization as per erratum i608
773          * it is safer to disable RTA by the bootloader, but we would like
774          * to be doubly sure here and prevent any mishaps.
775          */
776         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
777                 omap3630_ctrl_disable_rta();
778
779         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
780         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
781                 omap3_secure_ram_storage =
782                         kmalloc(0x803F, GFP_KERNEL);
783                 if (!omap3_secure_ram_storage)
784                         printk(KERN_ERR "Memory allocation failed when"
785                                         "allocating for secure sram context\n");
786
787                 local_irq_disable();
788                 local_fiq_disable();
789
790                 omap_dma_global_context_save();
791                 omap3_save_secure_ram_context();
792                 omap_dma_global_context_restore();
793
794                 local_irq_enable();
795                 local_fiq_enable();
796         }
797
798         omap3_save_scratchpad_contents();
799 err1:
800         return ret;
801 err2:
802         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
803         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
804                 list_del(&pwrst->node);
805                 kfree(pwrst);
806         }
807         return ret;
808 }
809
810 late_initcall(omap3_pm_init);