Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm...
[linux-2.6.git] / arch / arm / mach-omap2 / pm24xx.c
1 /*
2  * OMAP2 Power Management Routines
3  *
4  * Copyright (C) 2005 Texas Instruments, Inc.
5  * Copyright (C) 2006-2008 Nokia Corporation
6  *
7  * Written by:
8  * Richard Woodruff <r-woodruff2@ti.com>
9  * Tony Lindgren
10  * Juha Yrjola
11  * Amit Kucheria <amit.kucheria@nokia.com>
12  * Igor Stoppa <igor.stoppa@nokia.com>
13  *
14  * Based on pm.c for omap1
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
30 #include <linux/time.h>
31 #include <linux/gpio.h>
32
33 #include <asm/mach/time.h>
34 #include <asm/mach/irq.h>
35 #include <asm/mach-types.h>
36 #include <asm/system_misc.h>
37
38 #include <plat/clock.h>
39 #include <plat/sram.h>
40 #include <plat/dma.h>
41 #include <plat/board.h>
42
43 #include <mach/irqs.h>
44
45 #include "common.h"
46 #include "prm2xxx_3xxx.h"
47 #include "prm-regbits-24xx.h"
48 #include "cm2xxx_3xxx.h"
49 #include "cm-regbits-24xx.h"
50 #include "sdrc.h"
51 #include "pm.h"
52 #include "control.h"
53 #include "powerdomain.h"
54 #include "clockdomain.h"
55
56 static void (*omap2_sram_idle)(void);
57 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
58                                   void __iomem *sdrc_power);
59
60 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
61 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
62
63 static struct clk *osc_ck, *emul_ck;
64
65 static int omap2_fclks_active(void)
66 {
67         u32 f1, f2;
68
69         f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
70         f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
71
72         return (f1 | f2) ? 1 : 0;
73 }
74
75 static int omap2_enter_full_retention(void)
76 {
77         u32 l;
78
79         /* There is 1 reference hold for all children of the oscillator
80          * clock, the following will remove it. If no one else uses the
81          * oscillator itself it will be disabled if/when we enter retention
82          * mode.
83          */
84         clk_disable(osc_ck);
85
86         /* Clear old wake-up events */
87         /* REVISIT: These write to reserved bits? */
88         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
89         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
90         omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
91
92         /*
93          * Set MPU powerdomain's next power state to RETENTION;
94          * preserve logic state during retention
95          */
96         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
97         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
98
99         /* Workaround to kill USB */
100         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
101         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
102
103         omap2_gpio_prepare_for_idle(0);
104
105         /* One last check for pending IRQs to avoid extra latency due
106          * to sleeping unnecessarily. */
107         if (omap_irq_pending())
108                 goto no_sleep;
109
110         /* Jump to SRAM suspend code */
111         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
112                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
113                            OMAP_SDRC_REGADDR(SDRC_POWER));
114
115 no_sleep:
116         omap2_gpio_resume_after_idle();
117
118         clk_enable(osc_ck);
119
120         /* clear CORE wake-up events */
121         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
122         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
123
124         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
125         omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
126
127         /* MPU domain wake events */
128         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
129         if (l & 0x01)
130                 omap2_prm_write_mod_reg(0x01, OCP_MOD,
131                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
132         if (l & 0x20)
133                 omap2_prm_write_mod_reg(0x20, OCP_MOD,
134                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
135
136         /* Mask future PRCM-to-MPU interrupts */
137         omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
138
139         return 0;
140 }
141
142 static int omap2_i2c_active(void)
143 {
144         u32 l;
145
146         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
147         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
148 }
149
150 static int sti_console_enabled;
151
152 static int omap2_allow_mpu_retention(void)
153 {
154         u32 l;
155
156         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
157         l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
158         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
159                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
160                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
161                 return 0;
162         /* Check for UART3. */
163         l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
164         if (l & OMAP24XX_EN_UART3_MASK)
165                 return 0;
166         if (sti_console_enabled)
167                 return 0;
168
169         return 1;
170 }
171
172 static void omap2_enter_mpu_retention(void)
173 {
174         int only_idle = 0;
175
176         /* Putting MPU into the WFI state while a transfer is active
177          * seems to cause the I2C block to timeout. Why? Good question. */
178         if (omap2_i2c_active())
179                 return;
180
181         /* The peripherals seem not to be able to wake up the MPU when
182          * it is in retention mode. */
183         if (omap2_allow_mpu_retention()) {
184                 /* REVISIT: These write to reserved bits? */
185                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
186                 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
187                 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
188
189                 /* Try to enter MPU retention */
190                 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
191                                   OMAP_LOGICRETSTATE_MASK,
192                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
193         } else {
194                 /* Block MPU retention */
195
196                 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
197                                                  OMAP2_PM_PWSTCTRL);
198                 only_idle = 1;
199         }
200
201         omap2_sram_idle();
202 }
203
204 static int omap2_can_sleep(void)
205 {
206         if (omap2_fclks_active())
207                 return 0;
208         if (osc_ck->usecount > 1)
209                 return 0;
210         if (omap_dma_running())
211                 return 0;
212
213         return 1;
214 }
215
216 static void omap2_pm_idle(void)
217 {
218         local_fiq_disable();
219
220         if (!omap2_can_sleep()) {
221                 if (omap_irq_pending())
222                         goto out;
223                 omap2_enter_mpu_retention();
224                 goto out;
225         }
226
227         if (omap_irq_pending())
228                 goto out;
229
230         omap2_enter_full_retention();
231
232 out:
233         local_fiq_enable();
234 }
235
236 static void __init prcm_setup_regs(void)
237 {
238         int i, num_mem_banks;
239         struct powerdomain *pwrdm;
240
241         /*
242          * Enable autoidle
243          * XXX This should be handled by hwmod code or PRCM init code
244          */
245         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
246                           OMAP2_PRCM_SYSCONFIG_OFFSET);
247
248         /*
249          * Set CORE powerdomain memory banks to retain their contents
250          * during RETENTION
251          */
252         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
253         for (i = 0; i < num_mem_banks; i++)
254                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
255
256         /* Set CORE powerdomain's next power state to RETENTION */
257         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
258
259         /*
260          * Set MPU powerdomain's next power state to RETENTION;
261          * preserve logic state during retention
262          */
263         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
264         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
265
266         /* Force-power down DSP, GFX powerdomains */
267
268         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
269         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
270         clkdm_sleep(dsp_clkdm);
271
272         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
273         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
274         clkdm_sleep(gfx_clkdm);
275
276         /* Enable hardware-supervised idle for all clkdms */
277         clkdm_for_each(omap_pm_clkdms_setup, NULL);
278         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
279
280 #ifdef CONFIG_SUSPEND
281         omap_pm_suspend = omap2_enter_full_retention;
282 #endif
283
284         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
285          * stabilisation */
286         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
287                                 OMAP2_PRCM_CLKSSETUP_OFFSET);
288
289         /* Configure automatic voltage transition */
290         omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
291                                 OMAP2_PRCM_VOLTSETUP_OFFSET);
292         omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
293                                 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
294                                 OMAP24XX_MEMRETCTRL_MASK |
295                                 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
296                                 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
297                                 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
298
299         /* Enable wake-up events */
300         omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
301                                 WKUP_MOD, PM_WKEN);
302 }
303
304 static int __init omap2_pm_init(void)
305 {
306         u32 l;
307
308         if (!cpu_is_omap24xx())
309                 return -ENODEV;
310
311         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
312         l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
313         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
314
315         /* Look up important powerdomains */
316
317         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
318         if (!mpu_pwrdm)
319                 pr_err("PM: mpu_pwrdm not found\n");
320
321         core_pwrdm = pwrdm_lookup("core_pwrdm");
322         if (!core_pwrdm)
323                 pr_err("PM: core_pwrdm not found\n");
324
325         /* Look up important clockdomains */
326
327         mpu_clkdm = clkdm_lookup("mpu_clkdm");
328         if (!mpu_clkdm)
329                 pr_err("PM: mpu_clkdm not found\n");
330
331         wkup_clkdm = clkdm_lookup("wkup_clkdm");
332         if (!wkup_clkdm)
333                 pr_err("PM: wkup_clkdm not found\n");
334
335         dsp_clkdm = clkdm_lookup("dsp_clkdm");
336         if (!dsp_clkdm)
337                 pr_err("PM: dsp_clkdm not found\n");
338
339         gfx_clkdm = clkdm_lookup("gfx_clkdm");
340         if (!gfx_clkdm)
341                 pr_err("PM: gfx_clkdm not found\n");
342
343
344         osc_ck = clk_get(NULL, "osc_ck");
345         if (IS_ERR(osc_ck)) {
346                 printk(KERN_ERR "could not get osc_ck\n");
347                 return -ENODEV;
348         }
349
350         if (cpu_is_omap242x()) {
351                 emul_ck = clk_get(NULL, "emul_ck");
352                 if (IS_ERR(emul_ck)) {
353                         printk(KERN_ERR "could not get emul_ck\n");
354                         clk_put(osc_ck);
355                         return -ENODEV;
356                 }
357         }
358
359         prcm_setup_regs();
360
361         /* Hack to prevent MPU retention when STI console is enabled. */
362         {
363                 const struct omap_sti_console_config *sti;
364
365                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
366                                       struct omap_sti_console_config);
367                 if (sti != NULL && sti->enable)
368                         sti_console_enabled = 1;
369         }
370
371         /*
372          * We copy the assembler sleep/wakeup routines to SRAM.
373          * These routines need to be in SRAM as that's the only
374          * memory the MPU can see when it wakes up.
375          */
376         if (cpu_is_omap24xx()) {
377                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
378                                                  omap24xx_idle_loop_suspend_sz);
379
380                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
381                                                     omap24xx_cpu_suspend_sz);
382         }
383
384         arm_pm_idle = omap2_pm_idle;
385
386         return 0;
387 }
388
389 late_initcall(omap2_pm_init);