kmemleak: Initialise kmemleak after debug_objects_mem_init()
[linux-2.6.git] / arch / arm / mach-omap2 / cm2xxx_3xxx.c
1 /*
2  * OMAP2/3 CM module functions
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Paul Walmsley
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/delay.h>
15 #include <linux/spinlock.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20
21 #include <plat/common.h>
22
23 #include "cm.h"
24 #include "cm2xxx_3xxx.h"
25 #include "cm-regbits-24xx.h"
26 #include "cm-regbits-34xx.h"
27
28 /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
29 #define DPLL_AUTOIDLE_DISABLE                           0x0
30 #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
31
32 /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
33 #define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
34 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
35
36 static const u8 cm_idlest_offs[] = {
37         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
38 };
39
40 u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
41 {
42         return __raw_readl(cm_base + module + idx);
43 }
44
45 void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
46 {
47         __raw_writel(val, cm_base + module + idx);
48 }
49
50 /* Read-modify-write a register in a CM module. Caller must lock */
51 u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
52 {
53         u32 v;
54
55         v = omap2_cm_read_mod_reg(module, idx);
56         v &= ~mask;
57         v |= bits;
58         omap2_cm_write_mod_reg(v, module, idx);
59
60         return v;
61 }
62
63 u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
64 {
65         return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx);
66 }
67
68 u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
69 {
70         return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
71 }
72
73 /*
74  *
75  */
76
77 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
78 {
79         u32 v;
80
81         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
82         v &= ~mask;
83         v |= c << __ffs(mask);
84         omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
85 }
86
87 bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
88 {
89         u32 v;
90         bool ret = 0;
91
92         BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx());
93
94         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
95         v &= mask;
96         v >>= __ffs(mask);
97
98         if (cpu_is_omap24xx())
99                 ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
100         else
101                 ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
102
103         return ret;
104 }
105
106 void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
107 {
108         _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
109 }
110
111 void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
112 {
113         _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
114 }
115
116 void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
117 {
118         _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
119 }
120
121 void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
122 {
123         _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
124 }
125
126 void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
127 {
128         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
129 }
130
131 void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
132 {
133         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
134 }
135
136 /*
137  * DPLL autoidle control
138  */
139
140 static void _omap2xxx_set_dpll_autoidle(u8 m)
141 {
142         u32 v;
143
144         v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
145         v &= ~OMAP24XX_AUTO_DPLL_MASK;
146         v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
147         omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
148 }
149
150 void omap2xxx_cm_set_dpll_disable_autoidle(void)
151 {
152         _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
153 }
154
155 void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
156 {
157         _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
158 }
159
160 /*
161  * APLL autoidle control
162  */
163
164 static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
165 {
166         u32 v;
167
168         v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
169         v &= ~mask;
170         v |= m << __ffs(mask);
171         omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
172 }
173
174 void omap2xxx_cm_set_apll54_disable_autoidle(void)
175 {
176         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
177                                     OMAP24XX_AUTO_54M_MASK);
178 }
179
180 void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
181 {
182         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
183                                     OMAP24XX_AUTO_54M_MASK);
184 }
185
186 void omap2xxx_cm_set_apll96_disable_autoidle(void)
187 {
188         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
189                                     OMAP24XX_AUTO_96M_MASK);
190 }
191
192 void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
193 {
194         _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
195                                     OMAP24XX_AUTO_96M_MASK);
196 }
197
198 /*
199  *
200  */
201
202 /**
203  * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby
204  * @prcm_mod: PRCM module offset
205  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
206  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
207  *
208  * XXX document
209  */
210 int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
211 {
212         int ena = 0, i = 0;
213         u8 cm_idlest_reg;
214         u32 mask;
215
216         if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs)))
217                 return -EINVAL;
218
219         cm_idlest_reg = cm_idlest_offs[idlest_id - 1];
220
221         mask = 1 << idlest_shift;
222
223         if (cpu_is_omap24xx())
224                 ena = mask;
225         else if (cpu_is_omap34xx())
226                 ena = 0;
227         else
228                 BUG();
229
230         omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
231                           MAX_MODULE_READY_TIME, i);
232
233         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
234 }
235
236 /*
237  * Context save/restore code - OMAP3 only
238  */
239 #ifdef CONFIG_ARCH_OMAP3
240 struct omap3_cm_regs {
241         u32 iva2_cm_clksel1;
242         u32 iva2_cm_clksel2;
243         u32 cm_sysconfig;
244         u32 sgx_cm_clksel;
245         u32 dss_cm_clksel;
246         u32 cam_cm_clksel;
247         u32 per_cm_clksel;
248         u32 emu_cm_clksel;
249         u32 emu_cm_clkstctrl;
250         u32 pll_cm_autoidle2;
251         u32 pll_cm_clksel4;
252         u32 pll_cm_clksel5;
253         u32 pll_cm_clken2;
254         u32 cm_polctrl;
255         u32 iva2_cm_fclken;
256         u32 iva2_cm_clken_pll;
257         u32 core_cm_fclken1;
258         u32 core_cm_fclken3;
259         u32 sgx_cm_fclken;
260         u32 wkup_cm_fclken;
261         u32 dss_cm_fclken;
262         u32 cam_cm_fclken;
263         u32 per_cm_fclken;
264         u32 usbhost_cm_fclken;
265         u32 core_cm_iclken1;
266         u32 core_cm_iclken2;
267         u32 core_cm_iclken3;
268         u32 sgx_cm_iclken;
269         u32 wkup_cm_iclken;
270         u32 dss_cm_iclken;
271         u32 cam_cm_iclken;
272         u32 per_cm_iclken;
273         u32 usbhost_cm_iclken;
274         u32 iva2_cm_autoidle2;
275         u32 mpu_cm_autoidle2;
276         u32 iva2_cm_clkstctrl;
277         u32 mpu_cm_clkstctrl;
278         u32 core_cm_clkstctrl;
279         u32 sgx_cm_clkstctrl;
280         u32 dss_cm_clkstctrl;
281         u32 cam_cm_clkstctrl;
282         u32 per_cm_clkstctrl;
283         u32 neon_cm_clkstctrl;
284         u32 usbhost_cm_clkstctrl;
285         u32 core_cm_autoidle1;
286         u32 core_cm_autoidle2;
287         u32 core_cm_autoidle3;
288         u32 wkup_cm_autoidle;
289         u32 dss_cm_autoidle;
290         u32 cam_cm_autoidle;
291         u32 per_cm_autoidle;
292         u32 usbhost_cm_autoidle;
293         u32 sgx_cm_sleepdep;
294         u32 dss_cm_sleepdep;
295         u32 cam_cm_sleepdep;
296         u32 per_cm_sleepdep;
297         u32 usbhost_cm_sleepdep;
298         u32 cm_clkout_ctrl;
299 };
300
301 static struct omap3_cm_regs cm_context;
302
303 void omap3_cm_save_context(void)
304 {
305         cm_context.iva2_cm_clksel1 =
306                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
307         cm_context.iva2_cm_clksel2 =
308                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
309         cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
310         cm_context.sgx_cm_clksel =
311                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
312         cm_context.dss_cm_clksel =
313                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
314         cm_context.cam_cm_clksel =
315                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
316         cm_context.per_cm_clksel =
317                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
318         cm_context.emu_cm_clksel =
319                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
320         cm_context.emu_cm_clkstctrl =
321                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
322         cm_context.pll_cm_autoidle2 =
323                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
324         cm_context.pll_cm_clksel4 =
325                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
326         cm_context.pll_cm_clksel5 =
327                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
328         cm_context.pll_cm_clken2 =
329                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
330         cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
331         cm_context.iva2_cm_fclken =
332                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
333         cm_context.iva2_cm_clken_pll =
334                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
335         cm_context.core_cm_fclken1 =
336                 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
337         cm_context.core_cm_fclken3 =
338                 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
339         cm_context.sgx_cm_fclken =
340                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
341         cm_context.wkup_cm_fclken =
342                 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
343         cm_context.dss_cm_fclken =
344                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
345         cm_context.cam_cm_fclken =
346                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
347         cm_context.per_cm_fclken =
348                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
349         cm_context.usbhost_cm_fclken =
350                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
351         cm_context.core_cm_iclken1 =
352                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
353         cm_context.core_cm_iclken2 =
354                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
355         cm_context.core_cm_iclken3 =
356                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
357         cm_context.sgx_cm_iclken =
358                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
359         cm_context.wkup_cm_iclken =
360                 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
361         cm_context.dss_cm_iclken =
362                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
363         cm_context.cam_cm_iclken =
364                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
365         cm_context.per_cm_iclken =
366                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
367         cm_context.usbhost_cm_iclken =
368                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
369         cm_context.iva2_cm_autoidle2 =
370                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
371         cm_context.mpu_cm_autoidle2 =
372                 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
373         cm_context.iva2_cm_clkstctrl =
374                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
375         cm_context.mpu_cm_clkstctrl =
376                 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
377         cm_context.core_cm_clkstctrl =
378                 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
379         cm_context.sgx_cm_clkstctrl =
380                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
381         cm_context.dss_cm_clkstctrl =
382                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
383         cm_context.cam_cm_clkstctrl =
384                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
385         cm_context.per_cm_clkstctrl =
386                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
387         cm_context.neon_cm_clkstctrl =
388                 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
389         cm_context.usbhost_cm_clkstctrl =
390                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
391                                       OMAP2_CM_CLKSTCTRL);
392         cm_context.core_cm_autoidle1 =
393                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
394         cm_context.core_cm_autoidle2 =
395                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
396         cm_context.core_cm_autoidle3 =
397                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
398         cm_context.wkup_cm_autoidle =
399                 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
400         cm_context.dss_cm_autoidle =
401                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
402         cm_context.cam_cm_autoidle =
403                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
404         cm_context.per_cm_autoidle =
405                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
406         cm_context.usbhost_cm_autoidle =
407                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
408         cm_context.sgx_cm_sleepdep =
409                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
410                                       OMAP3430_CM_SLEEPDEP);
411         cm_context.dss_cm_sleepdep =
412                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
413         cm_context.cam_cm_sleepdep =
414                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
415         cm_context.per_cm_sleepdep =
416                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
417         cm_context.usbhost_cm_sleepdep =
418                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
419                                       OMAP3430_CM_SLEEPDEP);
420         cm_context.cm_clkout_ctrl =
421                 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
422                                       OMAP3_CM_CLKOUT_CTRL_OFFSET);
423 }
424
425 void omap3_cm_restore_context(void)
426 {
427         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
428                                CM_CLKSEL1);
429         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
430                                CM_CLKSEL2);
431         __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
432         omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
433                                CM_CLKSEL);
434         omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
435                                CM_CLKSEL);
436         omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
437                                CM_CLKSEL);
438         omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
439                                CM_CLKSEL);
440         omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
441                                CM_CLKSEL1);
442         omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
443                                OMAP2_CM_CLKSTCTRL);
444         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
445                                CM_AUTOIDLE2);
446         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
447                                OMAP3430ES2_CM_CLKSEL4);
448         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
449                                OMAP3430ES2_CM_CLKSEL5);
450         omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
451                                OMAP3430ES2_CM_CLKEN2);
452         __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
453         omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
454                                CM_FCLKEN);
455         omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
456                                OMAP3430_CM_CLKEN_PLL);
457         omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
458                                CM_FCLKEN1);
459         omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
460                                OMAP3430ES2_CM_FCLKEN3);
461         omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
462                                CM_FCLKEN);
463         omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
464         omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
465                                CM_FCLKEN);
466         omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
467                                CM_FCLKEN);
468         omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
469                                CM_FCLKEN);
470         omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
471                                OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
472         omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
473                                CM_ICLKEN1);
474         omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
475                                CM_ICLKEN2);
476         omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
477                                CM_ICLKEN3);
478         omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
479                                CM_ICLKEN);
480         omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
481         omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
482                                CM_ICLKEN);
483         omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
484                                CM_ICLKEN);
485         omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
486                                CM_ICLKEN);
487         omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
488                                OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
489         omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
490                                CM_AUTOIDLE2);
491         omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
492                                CM_AUTOIDLE2);
493         omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
494                                OMAP2_CM_CLKSTCTRL);
495         omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
496                                OMAP2_CM_CLKSTCTRL);
497         omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
498                                OMAP2_CM_CLKSTCTRL);
499         omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
500                                OMAP2_CM_CLKSTCTRL);
501         omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
502                                OMAP2_CM_CLKSTCTRL);
503         omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
504                                OMAP2_CM_CLKSTCTRL);
505         omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
506                                OMAP2_CM_CLKSTCTRL);
507         omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
508                                OMAP2_CM_CLKSTCTRL);
509         omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
510                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
511         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
512                                CM_AUTOIDLE1);
513         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
514                                CM_AUTOIDLE2);
515         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
516                                CM_AUTOIDLE3);
517         omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
518                                CM_AUTOIDLE);
519         omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
520                                CM_AUTOIDLE);
521         omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
522                                CM_AUTOIDLE);
523         omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
524                                CM_AUTOIDLE);
525         omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
526                                OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
527         omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
528                                OMAP3430_CM_SLEEPDEP);
529         omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
530                                OMAP3430_CM_SLEEPDEP);
531         omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
532                                OMAP3430_CM_SLEEPDEP);
533         omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
534                                OMAP3430_CM_SLEEPDEP);
535         omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
536                                OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
537         omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
538                                OMAP3_CM_CLKOUT_CTRL_OFFSET);
539 }
540 #endif