kmemleak: Initialise kmemleak after debug_objects_mem_init()
[linux-2.6.git] / arch / arm / mach-omap2 / clkt34xx_dpll3m2.c
1 /*
2  * OMAP34xx M2 divider clock code
3  *
4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
5  * Copyright (C) 2007-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Jouni Högander
9  *
10  * Parts of this code are based on code written by
11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License version 2 as
15  * published by the Free Software Foundation.
16  */
17 #undef DEBUG
18
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23
24 #include <plat/clock.h>
25 #include <plat/sram.h>
26 #include <plat/sdrc.h>
27
28 #include "clock.h"
29 #include "clock3xxx.h"
30 #include "clock34xx.h"
31 #include "sdrc.h"
32
33 #define CYCLES_PER_MHZ                  1000000
34
35 /*
36  * CORE DPLL (DPLL3) M2 divider rate programming functions
37  *
38  * These call into SRAM code to do the actual CM writes, since the SDRAM
39  * is clocked from DPLL3.
40  */
41
42 /**
43  * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
44  * @clk: struct clk * of DPLL to set
45  * @rate: rounded target rate
46  *
47  * Program the DPLL M2 divider with the rounded target rate.  Returns
48  * -EINVAL upon error, or 0 upon success.
49  */
50 int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
51 {
52         u32 new_div = 0;
53         u32 unlock_dll = 0;
54         u32 c;
55         unsigned long validrate, sdrcrate, _mpurate;
56         struct omap_sdrc_params *sdrc_cs0;
57         struct omap_sdrc_params *sdrc_cs1;
58         int ret;
59
60         if (!clk || !rate)
61                 return -EINVAL;
62
63         validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
64         if (validrate != rate)
65                 return -EINVAL;
66
67         sdrcrate = sdrc_ick_p->rate;
68         if (rate > clk->rate)
69                 sdrcrate <<= ((rate / clk->rate) >> 1);
70         else
71                 sdrcrate >>= ((clk->rate / rate) >> 1);
72
73         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
74         if (ret)
75                 return -EINVAL;
76
77         if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
78                 pr_debug("clock: will unlock SDRC DLL\n");
79                 unlock_dll = 1;
80         }
81
82         /*
83          * XXX This only needs to be done when the CPU frequency changes
84          */
85         _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
86         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
87         c += 1;  /* for safety */
88         c *= SDRC_MPURATE_LOOPS;
89         c >>= SDRC_MPURATE_SCALE;
90         if (c == 0)
91                 c = 1;
92
93         pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
94                  validrate);
95         pr_debug("clock: SDRC CS0 timing params used:"
96                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
97                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
98                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
99         if (sdrc_cs1)
100                 pr_debug("clock: SDRC CS1 timing params used: "
101                  " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
102                  sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
103                  sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
104
105         if (sdrc_cs1)
106                 omap3_configure_core_dpll(
107                                   new_div, unlock_dll, c, rate > clk->rate,
108                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
109                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
110                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
111                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
112         else
113                 omap3_configure_core_dpll(
114                                   new_div, unlock_dll, c, rate > clk->rate,
115                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
116                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
117                                   0, 0, 0, 0);
118
119         return 0;
120 }
121