omap: headers: Move remaining headers from include/mach to include/plat
[linux-2.6.git] / arch / arm / mach-omap1 / pm.c
1 /*
2  * linux/arch/arm/mach-omap1/pm.c
3  *
4  * OMAP Power Management Routines
5  *
6  * Original code for the SA11x0:
7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8  *
9  * Modified for the PXA250 by Nicolas Pitre:
10  * Copyright (c) 2002 Monta Vista Software, Inc.
11  *
12  * Modified for the OMAP1510 by David Singleton:
13  * Copyright (c) 2002 Monta Vista Software, Inc.
14  *
15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16  *
17  * This program is free software; you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation; either version 2 of the License, or (at your
20  * option) any later version.
21  *
22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * You should have received a copy of the GNU General Public License along
34  * with this program; if not, write to the Free Software Foundation, Inc.,
35  * 675 Mass Ave, Cambridge, MA 02139, USA.
36  */
37
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/interrupt.h>
42 #include <linux/sysfs.h>
43 #include <linux/module.h>
44 #include <linux/io.h>
45
46 #include <asm/irq.h>
47 #include <asm/atomic.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/irq.h>
50
51 #include <plat/cpu.h>
52 #include <mach/irqs.h>
53 #include <plat/clock.h>
54 #include <plat/sram.h>
55 #include <plat/tc.h>
56 #include <plat/mux.h>
57 #include <plat/dma.h>
58 #include <plat/dmtimer.h>
59
60 #include "pm.h"
61
62 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
63 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
64 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
65 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
66 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
67 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
68
69 #ifdef CONFIG_OMAP_32K_TIMER
70
71 static unsigned short enable_dyn_sleep = 1;
72
73 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
74                          char *buf)
75 {
76         return sprintf(buf, "%hu\n", enable_dyn_sleep);
77 }
78
79 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
80                           const char * buf, size_t n)
81 {
82         unsigned short value;
83         if (sscanf(buf, "%hu", &value) != 1 ||
84             (value != 0 && value != 1)) {
85                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
86                 return -EINVAL;
87         }
88         enable_dyn_sleep = value;
89         return n;
90 }
91
92 static struct kobj_attribute sleep_while_idle_attr =
93         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
94
95 #endif
96
97 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
98
99 /*
100  * Let's power down on idle, but only if we are really
101  * idle, because once we start down the path of
102  * going idle we continue to do idle even if we get
103  * a clock tick interrupt . .
104  */
105 void omap1_pm_idle(void)
106 {
107         extern __u32 arm_idlect1_mask;
108         __u32 use_idlect1 = arm_idlect1_mask;
109         int do_sleep = 0;
110
111         local_irq_disable();
112         local_fiq_disable();
113         if (need_resched()) {
114                 local_fiq_enable();
115                 local_irq_enable();
116                 return;
117         }
118
119 #ifdef CONFIG_OMAP_MPU_TIMER
120 #warning Enable 32kHz OS timer in order to allow sleep states in idle
121         use_idlect1 = use_idlect1 & ~(1 << 9);
122 #else
123
124         while (enable_dyn_sleep) {
125
126 #ifdef CONFIG_CBUS_TAHVO_USB
127                 extern int vbus_active;
128                 /* Clock requirements? */
129                 if (vbus_active)
130                         break;
131 #endif
132                 do_sleep = 1;
133                 break;
134         }
135
136 #endif
137
138 #ifdef CONFIG_OMAP_DM_TIMER
139         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
140 #endif
141
142         if (omap_dma_running())
143                 use_idlect1 &= ~(1 << 6);
144
145         /* We should be able to remove the do_sleep variable and multiple
146          * tests above as soon as drivers, timer and DMA code have been fixed.
147          * Even the sleep block count should become obsolete. */
148         if ((use_idlect1 != ~0) || !do_sleep) {
149
150                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
151                 if (cpu_is_omap15xx())
152                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
153                 else
154                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
155                 omap_writel(use_idlect1, ARM_IDLECT1);
156                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
157                 omap_writel(saved_idlect1, ARM_IDLECT1);
158
159                 local_fiq_enable();
160                 local_irq_enable();
161                 return;
162         }
163         omap_sram_suspend(omap_readl(ARM_IDLECT1),
164                           omap_readl(ARM_IDLECT2));
165
166         local_fiq_enable();
167         local_irq_enable();
168 }
169
170 /*
171  * Configuration of the wakeup event is board specific. For the
172  * moment we put it into this helper function. Later it may move
173  * to board specific files.
174  */
175 static void omap_pm_wakeup_setup(void)
176 {
177         u32 level1_wake = 0;
178         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
179
180         /*
181          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
182          * and the L2 wakeup interrupts: keypad and UART2. Note that the
183          * drivers must still separately call omap_set_gpio_wakeup() to
184          * wake up to a GPIO interrupt.
185          */
186         if (cpu_is_omap7xx())
187                 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
188                         OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
189         else if (cpu_is_omap15xx())
190                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
191                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
192         else if (cpu_is_omap16xx())
193                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
194                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
195
196         omap_writel(~level1_wake, OMAP_IH1_MIR);
197
198         if (cpu_is_omap7xx()) {
199                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
200                 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
201                                 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
202                                 OMAP_IH2_1_MIR);
203         } else if (cpu_is_omap15xx()) {
204                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
205                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
206         } else if (cpu_is_omap16xx()) {
207                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
208                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
209
210                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
211                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
212                             OMAP_IH2_1_MIR);
213                 omap_writel(~0x0, OMAP_IH2_2_MIR);
214                 omap_writel(~0x0, OMAP_IH2_3_MIR);
215         }
216
217         /*  New IRQ agreement, recalculate in cascade order */
218         omap_writel(1, OMAP_IH2_CONTROL);
219         omap_writel(1, OMAP_IH1_CONTROL);
220 }
221
222 #define EN_DSPCK        13      /* ARM_CKCTL */
223 #define EN_APICK        6       /* ARM_IDLECT2 */
224 #define DSP_EN          1       /* ARM_RSTCT1 */
225
226 void omap1_pm_suspend(void)
227 {
228         unsigned long arg0 = 0, arg1 = 0;
229
230         printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
231                 omap_rev());
232
233         omap_serial_wake_trigger(1);
234
235         if (!cpu_is_omap15xx())
236                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
237
238         /*
239          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
240          */
241
242         local_irq_disable();
243         local_fiq_disable();
244
245         /*
246          * Step 2: save registers
247          *
248          * The omap is a strange/beautiful device. The caches, memory
249          * and register state are preserved across power saves.
250          * We have to save and restore very little register state to
251          * idle the omap.
252          *
253          * Save interrupt, MPUI, ARM and UPLD control registers.
254          */
255
256         if (cpu_is_omap7xx()) {
257                 MPUI7XX_SAVE(OMAP_IH1_MIR);
258                 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
259                 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
260                 MPUI7XX_SAVE(MPUI_CTRL);
261                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
262                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
263                 MPUI7XX_SAVE(EMIFS_CONFIG);
264                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
265
266         } else if (cpu_is_omap15xx()) {
267                 MPUI1510_SAVE(OMAP_IH1_MIR);
268                 MPUI1510_SAVE(OMAP_IH2_MIR);
269                 MPUI1510_SAVE(MPUI_CTRL);
270                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
271                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
272                 MPUI1510_SAVE(EMIFS_CONFIG);
273                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
274         } else if (cpu_is_omap16xx()) {
275                 MPUI1610_SAVE(OMAP_IH1_MIR);
276                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
277                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
278                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
279                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
280                 MPUI1610_SAVE(MPUI_CTRL);
281                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
282                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
283                 MPUI1610_SAVE(EMIFS_CONFIG);
284                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
285         }
286
287         ARM_SAVE(ARM_CKCTL);
288         ARM_SAVE(ARM_IDLECT1);
289         ARM_SAVE(ARM_IDLECT2);
290         if (!(cpu_is_omap15xx()))
291                 ARM_SAVE(ARM_IDLECT3);
292         ARM_SAVE(ARM_EWUPCT);
293         ARM_SAVE(ARM_RSTCT1);
294         ARM_SAVE(ARM_RSTCT2);
295         ARM_SAVE(ARM_SYSST);
296         ULPD_SAVE(ULPD_CLOCK_CTRL);
297         ULPD_SAVE(ULPD_STATUS_REQ);
298
299         /* (Step 3 removed - we now allow deep sleep by default) */
300
301         /*
302          * Step 4: OMAP DSP Shutdown
303          */
304
305         /* stop DSP */
306         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
307
308                 /* shut down dsp_ck */
309         if (!cpu_is_omap7xx())
310                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
311
312         /* temporarily enabling api_ck to access DSP registers */
313         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
314
315         /* save DSP registers */
316         DSP_SAVE(DSP_IDLECT2);
317
318         /* Stop all DSP domain clocks */
319         __raw_writew(0, DSP_IDLECT2);
320
321         /*
322          * Step 5: Wakeup Event Setup
323          */
324
325         omap_pm_wakeup_setup();
326
327         /*
328          * Step 6: ARM and Traffic controller shutdown
329          */
330
331         /* disable ARM watchdog */
332         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
333         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
334
335         /*
336          * Step 6b: ARM and Traffic controller shutdown
337          *
338          * Step 6 continues here. Prepare jump to power management
339          * assembly code in internal SRAM.
340          *
341          * Since the omap_cpu_suspend routine has been copied to
342          * SRAM, we'll do an indirect procedure call to it and pass the
343          * contents of arm_idlect1 and arm_idlect2 so it can restore
344          * them when it wakes up and it will return.
345          */
346
347         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
348         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
349
350         /*
351          * Step 6c: ARM and Traffic controller shutdown
352          *
353          * Jump to assembly code. The processor will stay there
354          * until wake up.
355          */
356         omap_sram_suspend(arg0, arg1);
357
358         /*
359          * If we are here, processor is woken up!
360          */
361
362         /*
363          * Restore DSP clocks
364          */
365
366         /* again temporarily enabling api_ck to access DSP registers */
367         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
368
369         /* Restore DSP domain clocks */
370         DSP_RESTORE(DSP_IDLECT2);
371
372         /*
373          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
374          */
375
376         if (!(cpu_is_omap15xx()))
377                 ARM_RESTORE(ARM_IDLECT3);
378         ARM_RESTORE(ARM_CKCTL);
379         ARM_RESTORE(ARM_EWUPCT);
380         ARM_RESTORE(ARM_RSTCT1);
381         ARM_RESTORE(ARM_RSTCT2);
382         ARM_RESTORE(ARM_SYSST);
383         ULPD_RESTORE(ULPD_CLOCK_CTRL);
384         ULPD_RESTORE(ULPD_STATUS_REQ);
385
386         if (cpu_is_omap7xx()) {
387                 MPUI7XX_RESTORE(EMIFS_CONFIG);
388                 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
389                 MPUI7XX_RESTORE(OMAP_IH1_MIR);
390                 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
391                 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
392         } else if (cpu_is_omap15xx()) {
393                 MPUI1510_RESTORE(MPUI_CTRL);
394                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
395                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
396                 MPUI1510_RESTORE(EMIFS_CONFIG);
397                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
398                 MPUI1510_RESTORE(OMAP_IH1_MIR);
399                 MPUI1510_RESTORE(OMAP_IH2_MIR);
400         } else if (cpu_is_omap16xx()) {
401                 MPUI1610_RESTORE(MPUI_CTRL);
402                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
403                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
404                 MPUI1610_RESTORE(EMIFS_CONFIG);
405                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
406
407                 MPUI1610_RESTORE(OMAP_IH1_MIR);
408                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
409                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
410                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
411                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
412         }
413
414         if (!cpu_is_omap15xx())
415                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
416
417         /*
418          * Re-enable interrupts
419          */
420
421         local_irq_enable();
422         local_fiq_enable();
423
424         omap_serial_wake_trigger(0);
425
426         printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
427                 omap_rev());
428 }
429
430 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
431 static int g_read_completed;
432
433 /*
434  * Read system PM registers for debugging
435  */
436 static int omap_pm_read_proc(
437         char *page_buffer,
438         char **my_first_byte,
439         off_t virtual_start,
440         int length,
441         int *eof,
442         void *data)
443 {
444         int my_buffer_offset = 0;
445         char * const my_base = page_buffer;
446
447         ARM_SAVE(ARM_CKCTL);
448         ARM_SAVE(ARM_IDLECT1);
449         ARM_SAVE(ARM_IDLECT2);
450         if (!(cpu_is_omap15xx()))
451                 ARM_SAVE(ARM_IDLECT3);
452         ARM_SAVE(ARM_EWUPCT);
453         ARM_SAVE(ARM_RSTCT1);
454         ARM_SAVE(ARM_RSTCT2);
455         ARM_SAVE(ARM_SYSST);
456
457         ULPD_SAVE(ULPD_IT_STATUS);
458         ULPD_SAVE(ULPD_CLOCK_CTRL);
459         ULPD_SAVE(ULPD_SOFT_REQ);
460         ULPD_SAVE(ULPD_STATUS_REQ);
461         ULPD_SAVE(ULPD_DPLL_CTRL);
462         ULPD_SAVE(ULPD_POWER_CTRL);
463
464         if (cpu_is_omap7xx()) {
465                 MPUI7XX_SAVE(MPUI_CTRL);
466                 MPUI7XX_SAVE(MPUI_DSP_STATUS);
467                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
468                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
469                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
470                 MPUI7XX_SAVE(EMIFS_CONFIG);
471         } else if (cpu_is_omap15xx()) {
472                 MPUI1510_SAVE(MPUI_CTRL);
473                 MPUI1510_SAVE(MPUI_DSP_STATUS);
474                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
475                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
476                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
477                 MPUI1510_SAVE(EMIFS_CONFIG);
478         } else if (cpu_is_omap16xx()) {
479                 MPUI1610_SAVE(MPUI_CTRL);
480                 MPUI1610_SAVE(MPUI_DSP_STATUS);
481                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
482                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
483                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
484                 MPUI1610_SAVE(EMIFS_CONFIG);
485         }
486
487         if (virtual_start == 0) {
488                 g_read_completed = 0;
489
490                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
491                    "ARM_CKCTL_REG:            0x%-8x     \n"
492                    "ARM_IDLECT1_REG:          0x%-8x     \n"
493                    "ARM_IDLECT2_REG:          0x%-8x     \n"
494                    "ARM_IDLECT3_REG:          0x%-8x     \n"
495                    "ARM_EWUPCT_REG:           0x%-8x     \n"
496                    "ARM_RSTCT1_REG:           0x%-8x     \n"
497                    "ARM_RSTCT2_REG:           0x%-8x     \n"
498                    "ARM_SYSST_REG:            0x%-8x     \n"
499                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
500                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
501                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
502                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
503                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
504                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
505                    ARM_SHOW(ARM_CKCTL),
506                    ARM_SHOW(ARM_IDLECT1),
507                    ARM_SHOW(ARM_IDLECT2),
508                    ARM_SHOW(ARM_IDLECT3),
509                    ARM_SHOW(ARM_EWUPCT),
510                    ARM_SHOW(ARM_RSTCT1),
511                    ARM_SHOW(ARM_RSTCT2),
512                    ARM_SHOW(ARM_SYSST),
513                    ULPD_SHOW(ULPD_IT_STATUS),
514                    ULPD_SHOW(ULPD_CLOCK_CTRL),
515                    ULPD_SHOW(ULPD_SOFT_REQ),
516                    ULPD_SHOW(ULPD_DPLL_CTRL),
517                    ULPD_SHOW(ULPD_STATUS_REQ),
518                    ULPD_SHOW(ULPD_POWER_CTRL));
519
520                 if (cpu_is_omap7xx()) {
521                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
522                            "MPUI7XX_CTRL_REG         0x%-8x \n"
523                            "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
524                            "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
525                            "MPUI7XX_DSP_API_CONFIG_REG:  0x%-8x \n"
526                            "MPUI7XX_SDRAM_CONFIG_REG:    0x%-8x \n"
527                            "MPUI7XX_EMIFS_CONFIG_REG:    0x%-8x \n",
528                            MPUI7XX_SHOW(MPUI_CTRL),
529                            MPUI7XX_SHOW(MPUI_DSP_STATUS),
530                            MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
531                            MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
532                            MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
533                            MPUI7XX_SHOW(EMIFS_CONFIG));
534                 } else if (cpu_is_omap15xx()) {
535                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
536                            "MPUI1510_CTRL_REG             0x%-8x \n"
537                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
538                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
539                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
540                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
541                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
542                            MPUI1510_SHOW(MPUI_CTRL),
543                            MPUI1510_SHOW(MPUI_DSP_STATUS),
544                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
545                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
546                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
547                            MPUI1510_SHOW(EMIFS_CONFIG));
548                 } else if (cpu_is_omap16xx()) {
549                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
550                            "MPUI1610_CTRL_REG             0x%-8x \n"
551                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
552                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
553                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
554                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
555                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
556                            MPUI1610_SHOW(MPUI_CTRL),
557                            MPUI1610_SHOW(MPUI_DSP_STATUS),
558                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
559                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
560                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
561                            MPUI1610_SHOW(EMIFS_CONFIG));
562                 }
563
564                 g_read_completed++;
565         } else if (g_read_completed >= 1) {
566                  *eof = 1;
567                  return 0;
568         }
569         g_read_completed++;
570
571         *my_first_byte = page_buffer;
572         return  my_buffer_offset;
573 }
574
575 static void omap_pm_init_proc(void)
576 {
577         struct proc_dir_entry *entry;
578
579         entry = create_proc_read_entry("driver/omap_pm",
580                                        S_IWUSR | S_IRUGO, NULL,
581                                        omap_pm_read_proc, NULL);
582 }
583
584 #endif /* DEBUG && CONFIG_PROC_FS */
585
586 static void (*saved_idle)(void) = NULL;
587
588 /*
589  *      omap_pm_prepare - Do preliminary suspend work.
590  *
591  */
592 static int omap_pm_prepare(void)
593 {
594         /* We cannot sleep in idle until we have resumed */
595         saved_idle = pm_idle;
596         pm_idle = NULL;
597
598         return 0;
599 }
600
601
602 /*
603  *      omap_pm_enter - Actually enter a sleep state.
604  *      @state:         State we're entering.
605  *
606  */
607
608 static int omap_pm_enter(suspend_state_t state)
609 {
610         switch (state)
611         {
612         case PM_SUSPEND_STANDBY:
613         case PM_SUSPEND_MEM:
614                 omap1_pm_suspend();
615                 break;
616         default:
617                 return -EINVAL;
618         }
619
620         return 0;
621 }
622
623
624 /**
625  *      omap_pm_finish - Finish up suspend sequence.
626  *
627  *      This is called after we wake back up (or if entering the sleep state
628  *      failed).
629  */
630
631 static void omap_pm_finish(void)
632 {
633         pm_idle = saved_idle;
634 }
635
636
637 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
638 {
639         return IRQ_HANDLED;
640 }
641
642 static struct irqaction omap_wakeup_irq = {
643         .name           = "peripheral wakeup",
644         .flags          = IRQF_DISABLED,
645         .handler        = omap_wakeup_interrupt
646 };
647
648
649
650 static struct platform_suspend_ops omap_pm_ops ={
651         .prepare        = omap_pm_prepare,
652         .enter          = omap_pm_enter,
653         .finish         = omap_pm_finish,
654         .valid          = suspend_valid_only_mem,
655 };
656
657 static int __init omap_pm_init(void)
658 {
659
660 #ifdef CONFIG_OMAP_32K_TIMER
661         int error;
662 #endif
663
664         printk("Power Management for TI OMAP.\n");
665
666         /*
667          * We copy the assembler sleep/wakeup routines to SRAM.
668          * These routines need to be in SRAM as that's the only
669          * memory the MPU can see when it wakes up.
670          */
671         if (cpu_is_omap7xx()) {
672                 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
673                                                    omap7xx_cpu_suspend_sz);
674         } else if (cpu_is_omap15xx()) {
675                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
676                                                    omap1510_cpu_suspend_sz);
677         } else if (cpu_is_omap16xx()) {
678                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
679                                                    omap1610_cpu_suspend_sz);
680         }
681
682         if (omap_sram_suspend == NULL) {
683                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
684                 return -ENODEV;
685         }
686
687         pm_idle = omap1_pm_idle;
688
689         if (cpu_is_omap7xx())
690                 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
691         else if (cpu_is_omap16xx())
692                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
693
694         /* Program new power ramp-up time
695          * (0 for most boards since we don't lower voltage when in deep sleep)
696          */
697         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
698
699         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
700         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
701
702         /* Configure IDLECT3 */
703         if (cpu_is_omap7xx())
704                 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
705         else if (cpu_is_omap16xx())
706                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
707
708         suspend_set_ops(&omap_pm_ops);
709
710 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
711         omap_pm_init_proc();
712 #endif
713
714 #ifdef CONFIG_OMAP_32K_TIMER
715         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
716         if (error)
717                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
718 #endif
719
720         if (cpu_is_omap16xx()) {
721                 /* configure LOW_PWR pin */
722                 omap_cfg_reg(T20_1610_LOW_PWR);
723         }
724
725         return 0;
726 }
727 __initcall(omap_pm_init);