kset: convert /sys/power to use kset_create
[linux-2.6.git] / arch / arm / mach-omap1 / pm.c
1 /*
2  * linux/arch/arm/mach-omap1/pm.c
3  *
4  * OMAP Power Management Routines
5  *
6  * Original code for the SA11x0:
7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8  *
9  * Modified for the PXA250 by Nicolas Pitre:
10  * Copyright (c) 2002 Monta Vista Software, Inc.
11  *
12  * Modified for the OMAP1510 by David Singleton:
13  * Copyright (c) 2002 Monta Vista Software, Inc.
14  *
15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16  *
17  * This program is free software; you can redistribute it and/or modify it
18  * under the terms of the GNU General Public License as published by the
19  * Free Software Foundation; either version 2 of the License, or (at your
20  * option) any later version.
21  *
22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * You should have received a copy of the GNU General Public License along
34  * with this program; if not, write to the Free Software Foundation, Inc.,
35  * 675 Mass Ave, Cambridge, MA 02139, USA.
36  */
37
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/interrupt.h>
42 #include <linux/sysfs.h>
43 #include <linux/module.h>
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47 #include <asm/atomic.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach-types.h>
51
52 #include <asm/arch/cpu.h>
53 #include <asm/arch/irqs.h>
54 #include <asm/arch/clock.h>
55 #include <asm/arch/sram.h>
56 #include <asm/arch/tc.h>
57 #include <asm/arch/pm.h>
58 #include <asm/arch/mux.h>
59 #include <asm/arch/dma.h>
60 #include <asm/arch/dsp_common.h>
61 #include <asm/arch/dmtimer.h>
62
63 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
64 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
65 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
66 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
67 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
68 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
69
70 static unsigned short enable_dyn_sleep = 1;
71
72 static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf)
73 {
74         return sprintf(buf, "%hu\n", enable_dyn_sleep);
75 }
76
77 static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset,
78                                               const char * buf,
79                                               size_t n)
80 {
81         unsigned short value;
82         if (sscanf(buf, "%hu", &value) != 1 ||
83             (value != 0 && value != 1)) {
84                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
85                 return -EINVAL;
86         }
87         enable_dyn_sleep = value;
88         return n;
89 }
90
91 static struct subsys_attribute sleep_while_idle_attr = {
92         .attr   = {
93                 .name = __stringify(sleep_while_idle),
94                 .mode = 0644,
95         },
96         .show   = omap_pm_sleep_while_idle_show,
97         .store  = omap_pm_sleep_while_idle_store,
98 };
99
100 static void (*omap_sram_idle)(void) = NULL;
101 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
102
103 /*
104  * Let's power down on idle, but only if we are really
105  * idle, because once we start down the path of
106  * going idle we continue to do idle even if we get
107  * a clock tick interrupt . .
108  */
109 void omap_pm_idle(void)
110 {
111         extern __u32 arm_idlect1_mask;
112         __u32 use_idlect1 = arm_idlect1_mask;
113 #ifndef CONFIG_OMAP_MPU_TIMER
114         int do_sleep;
115 #endif
116
117         local_irq_disable();
118         local_fiq_disable();
119         if (need_resched()) {
120                 local_fiq_enable();
121                 local_irq_enable();
122                 return;
123         }
124
125         /*
126          * Since an interrupt may set up a timer, we don't want to
127          * reprogram the hardware timer with interrupts enabled.
128          * Re-enable interrupts only after returning from idle.
129          */
130         timer_dyn_reprogram();
131
132 #ifdef CONFIG_OMAP_MPU_TIMER
133 #warning Enable 32kHz OS timer in order to allow sleep states in idle
134         use_idlect1 = use_idlect1 & ~(1 << 9);
135 #else
136
137         do_sleep = 0;
138         while (enable_dyn_sleep) {
139
140 #ifdef CONFIG_CBUS_TAHVO_USB
141                 extern int vbus_active;
142                 /* Clock requirements? */
143                 if (vbus_active)
144                         break;
145 #endif
146                 do_sleep = 1;
147                 break;
148         }
149
150 #ifdef CONFIG_OMAP_DM_TIMER
151         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
152 #endif
153
154         if (omap_dma_running())
155                 use_idlect1 &= ~(1 << 6);
156
157         /* We should be able to remove the do_sleep variable and multiple
158          * tests above as soon as drivers, timer and DMA code have been fixed.
159          * Even the sleep block count should become obsolete. */
160         if ((use_idlect1 != ~0) || !do_sleep) {
161
162                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
163                 if (cpu_is_omap15xx())
164                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
165                 else
166                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
167                 omap_writel(use_idlect1, ARM_IDLECT1);
168                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
169                 omap_writel(saved_idlect1, ARM_IDLECT1);
170
171                 local_fiq_enable();
172                 local_irq_enable();
173                 return;
174         }
175         omap_sram_suspend(omap_readl(ARM_IDLECT1),
176                           omap_readl(ARM_IDLECT2));
177 #endif
178
179         local_fiq_enable();
180         local_irq_enable();
181 }
182
183 /*
184  * Configuration of the wakeup event is board specific. For the
185  * moment we put it into this helper function. Later it may move
186  * to board specific files.
187  */
188 static void omap_pm_wakeup_setup(void)
189 {
190         u32 level1_wake = 0;
191         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
192
193         /*
194          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
195          * and the L2 wakeup interrupts: keypad and UART2. Note that the
196          * drivers must still separately call omap_set_gpio_wakeup() to
197          * wake up to a GPIO interrupt.
198          */
199         if (cpu_is_omap730())
200                 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
201                         OMAP_IRQ_BIT(INT_730_IH2_IRQ);
202         else if (cpu_is_omap15xx())
203                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
204                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
205         else if (cpu_is_omap16xx())
206                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
207                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
208
209         omap_writel(~level1_wake, OMAP_IH1_MIR);
210
211         if (cpu_is_omap730()) {
212                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
213                 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
214                                 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
215                                 OMAP_IH2_1_MIR);
216         } else if (cpu_is_omap15xx()) {
217                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
218                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
219         } else if (cpu_is_omap16xx()) {
220                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
221                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
222
223                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
224                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
225                             OMAP_IH2_1_MIR);
226                 omap_writel(~0x0, OMAP_IH2_2_MIR);
227                 omap_writel(~0x0, OMAP_IH2_3_MIR);
228         }
229
230         /*  New IRQ agreement, recalculate in cascade order */
231         omap_writel(1, OMAP_IH2_CONTROL);
232         omap_writel(1, OMAP_IH1_CONTROL);
233 }
234
235 #define EN_DSPCK        13      /* ARM_CKCTL */
236 #define EN_APICK        6       /* ARM_IDLECT2 */
237 #define DSP_EN          1       /* ARM_RSTCT1 */
238
239 void omap_pm_suspend(void)
240 {
241         unsigned long arg0 = 0, arg1 = 0;
242
243         printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
244
245         omap_serial_wake_trigger(1);
246
247         if (!cpu_is_omap15xx())
248                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
249
250         /*
251          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
252          */
253
254         local_irq_disable();
255         local_fiq_disable();
256
257         /*
258          * Step 2: save registers
259          *
260          * The omap is a strange/beautiful device. The caches, memory
261          * and register state are preserved across power saves.
262          * We have to save and restore very little register state to
263          * idle the omap.
264          *
265          * Save interrupt, MPUI, ARM and UPLD control registers.
266          */
267
268         if (cpu_is_omap730()) {
269                 MPUI730_SAVE(OMAP_IH1_MIR);
270                 MPUI730_SAVE(OMAP_IH2_0_MIR);
271                 MPUI730_SAVE(OMAP_IH2_1_MIR);
272                 MPUI730_SAVE(MPUI_CTRL);
273                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
274                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
275                 MPUI730_SAVE(EMIFS_CONFIG);
276                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
277
278         } else if (cpu_is_omap15xx()) {
279                 MPUI1510_SAVE(OMAP_IH1_MIR);
280                 MPUI1510_SAVE(OMAP_IH2_MIR);
281                 MPUI1510_SAVE(MPUI_CTRL);
282                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
283                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
284                 MPUI1510_SAVE(EMIFS_CONFIG);
285                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
286         } else if (cpu_is_omap16xx()) {
287                 MPUI1610_SAVE(OMAP_IH1_MIR);
288                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
289                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
290                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
291                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
292                 MPUI1610_SAVE(MPUI_CTRL);
293                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
294                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
295                 MPUI1610_SAVE(EMIFS_CONFIG);
296                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
297         }
298
299         ARM_SAVE(ARM_CKCTL);
300         ARM_SAVE(ARM_IDLECT1);
301         ARM_SAVE(ARM_IDLECT2);
302         if (!(cpu_is_omap15xx()))
303                 ARM_SAVE(ARM_IDLECT3);
304         ARM_SAVE(ARM_EWUPCT);
305         ARM_SAVE(ARM_RSTCT1);
306         ARM_SAVE(ARM_RSTCT2);
307         ARM_SAVE(ARM_SYSST);
308         ULPD_SAVE(ULPD_CLOCK_CTRL);
309         ULPD_SAVE(ULPD_STATUS_REQ);
310
311         /* (Step 3 removed - we now allow deep sleep by default) */
312
313         /*
314          * Step 4: OMAP DSP Shutdown
315          */
316
317         /* stop DSP */
318         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
319
320                 /* shut down dsp_ck */
321         if (!cpu_is_omap730())
322                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
323
324         /* temporarily enabling api_ck to access DSP registers */
325         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
326
327         /* save DSP registers */
328         DSP_SAVE(DSP_IDLECT2);
329
330         /* Stop all DSP domain clocks */
331         __raw_writew(0, DSP_IDLECT2);
332
333         /*
334          * Step 5: Wakeup Event Setup
335          */
336
337         omap_pm_wakeup_setup();
338
339         /*
340          * Step 6: ARM and Traffic controller shutdown
341          */
342
343         /* disable ARM watchdog */
344         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
345         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
346
347         /*
348          * Step 6b: ARM and Traffic controller shutdown
349          *
350          * Step 6 continues here. Prepare jump to power management
351          * assembly code in internal SRAM.
352          *
353          * Since the omap_cpu_suspend routine has been copied to
354          * SRAM, we'll do an indirect procedure call to it and pass the
355          * contents of arm_idlect1 and arm_idlect2 so it can restore
356          * them when it wakes up and it will return.
357          */
358
359         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
360         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
361
362         /*
363          * Step 6c: ARM and Traffic controller shutdown
364          *
365          * Jump to assembly code. The processor will stay there
366          * until wake up.
367          */
368         omap_sram_suspend(arg0, arg1);
369
370         /*
371          * If we are here, processor is woken up!
372          */
373
374         /*
375          * Restore DSP clocks
376          */
377
378         /* again temporarily enabling api_ck to access DSP registers */
379         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
380
381         /* Restore DSP domain clocks */
382         DSP_RESTORE(DSP_IDLECT2);
383
384         /*
385          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
386          */
387
388         if (!(cpu_is_omap15xx()))
389                 ARM_RESTORE(ARM_IDLECT3);
390         ARM_RESTORE(ARM_CKCTL);
391         ARM_RESTORE(ARM_EWUPCT);
392         ARM_RESTORE(ARM_RSTCT1);
393         ARM_RESTORE(ARM_RSTCT2);
394         ARM_RESTORE(ARM_SYSST);
395         ULPD_RESTORE(ULPD_CLOCK_CTRL);
396         ULPD_RESTORE(ULPD_STATUS_REQ);
397
398         if (cpu_is_omap730()) {
399                 MPUI730_RESTORE(EMIFS_CONFIG);
400                 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
401                 MPUI730_RESTORE(OMAP_IH1_MIR);
402                 MPUI730_RESTORE(OMAP_IH2_0_MIR);
403                 MPUI730_RESTORE(OMAP_IH2_1_MIR);
404         } else if (cpu_is_omap15xx()) {
405                 MPUI1510_RESTORE(MPUI_CTRL);
406                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
407                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
408                 MPUI1510_RESTORE(EMIFS_CONFIG);
409                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
410                 MPUI1510_RESTORE(OMAP_IH1_MIR);
411                 MPUI1510_RESTORE(OMAP_IH2_MIR);
412         } else if (cpu_is_omap16xx()) {
413                 MPUI1610_RESTORE(MPUI_CTRL);
414                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
415                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
416                 MPUI1610_RESTORE(EMIFS_CONFIG);
417                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
418
419                 MPUI1610_RESTORE(OMAP_IH1_MIR);
420                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
421                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
422                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
423                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
424         }
425
426         if (!cpu_is_omap15xx())
427                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
428
429         /*
430          * Re-enable interrupts
431          */
432
433         local_irq_enable();
434         local_fiq_enable();
435
436         omap_serial_wake_trigger(0);
437
438         printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
439 }
440
441 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
442 static int g_read_completed;
443
444 /*
445  * Read system PM registers for debugging
446  */
447 static int omap_pm_read_proc(
448         char *page_buffer,
449         char **my_first_byte,
450         off_t virtual_start,
451         int length,
452         int *eof,
453         void *data)
454 {
455         int my_buffer_offset = 0;
456         char * const my_base = page_buffer;
457
458         ARM_SAVE(ARM_CKCTL);
459         ARM_SAVE(ARM_IDLECT1);
460         ARM_SAVE(ARM_IDLECT2);
461         if (!(cpu_is_omap15xx()))
462                 ARM_SAVE(ARM_IDLECT3);
463         ARM_SAVE(ARM_EWUPCT);
464         ARM_SAVE(ARM_RSTCT1);
465         ARM_SAVE(ARM_RSTCT2);
466         ARM_SAVE(ARM_SYSST);
467
468         ULPD_SAVE(ULPD_IT_STATUS);
469         ULPD_SAVE(ULPD_CLOCK_CTRL);
470         ULPD_SAVE(ULPD_SOFT_REQ);
471         ULPD_SAVE(ULPD_STATUS_REQ);
472         ULPD_SAVE(ULPD_DPLL_CTRL);
473         ULPD_SAVE(ULPD_POWER_CTRL);
474
475         if (cpu_is_omap730()) {
476                 MPUI730_SAVE(MPUI_CTRL);
477                 MPUI730_SAVE(MPUI_DSP_STATUS);
478                 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
479                 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
480                 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
481                 MPUI730_SAVE(EMIFS_CONFIG);
482         } else if (cpu_is_omap15xx()) {
483                 MPUI1510_SAVE(MPUI_CTRL);
484                 MPUI1510_SAVE(MPUI_DSP_STATUS);
485                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
486                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
487                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
488                 MPUI1510_SAVE(EMIFS_CONFIG);
489         } else if (cpu_is_omap16xx()) {
490                 MPUI1610_SAVE(MPUI_CTRL);
491                 MPUI1610_SAVE(MPUI_DSP_STATUS);
492                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
493                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
494                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
495                 MPUI1610_SAVE(EMIFS_CONFIG);
496         }
497
498         if (virtual_start == 0) {
499                 g_read_completed = 0;
500
501                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
502                    "ARM_CKCTL_REG:            0x%-8x     \n"
503                    "ARM_IDLECT1_REG:          0x%-8x     \n"
504                    "ARM_IDLECT2_REG:          0x%-8x     \n"
505                    "ARM_IDLECT3_REG:          0x%-8x     \n"
506                    "ARM_EWUPCT_REG:           0x%-8x     \n"
507                    "ARM_RSTCT1_REG:           0x%-8x     \n"
508                    "ARM_RSTCT2_REG:           0x%-8x     \n"
509                    "ARM_SYSST_REG:            0x%-8x     \n"
510                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
511                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
512                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
513                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
514                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
515                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
516                    ARM_SHOW(ARM_CKCTL),
517                    ARM_SHOW(ARM_IDLECT1),
518                    ARM_SHOW(ARM_IDLECT2),
519                    ARM_SHOW(ARM_IDLECT3),
520                    ARM_SHOW(ARM_EWUPCT),
521                    ARM_SHOW(ARM_RSTCT1),
522                    ARM_SHOW(ARM_RSTCT2),
523                    ARM_SHOW(ARM_SYSST),
524                    ULPD_SHOW(ULPD_IT_STATUS),
525                    ULPD_SHOW(ULPD_CLOCK_CTRL),
526                    ULPD_SHOW(ULPD_SOFT_REQ),
527                    ULPD_SHOW(ULPD_DPLL_CTRL),
528                    ULPD_SHOW(ULPD_STATUS_REQ),
529                    ULPD_SHOW(ULPD_POWER_CTRL));
530
531                 if (cpu_is_omap730()) {
532                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
533                            "MPUI730_CTRL_REG         0x%-8x \n"
534                            "MPUI730_DSP_STATUS_REG:      0x%-8x \n"
535                            "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
536                            "MPUI730_DSP_API_CONFIG_REG:  0x%-8x \n"
537                            "MPUI730_SDRAM_CONFIG_REG:    0x%-8x \n"
538                            "MPUI730_EMIFS_CONFIG_REG:    0x%-8x \n",
539                            MPUI730_SHOW(MPUI_CTRL),
540                            MPUI730_SHOW(MPUI_DSP_STATUS),
541                            MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
542                            MPUI730_SHOW(MPUI_DSP_API_CONFIG),
543                            MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
544                            MPUI730_SHOW(EMIFS_CONFIG));
545                 } else if (cpu_is_omap15xx()) {
546                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
547                            "MPUI1510_CTRL_REG             0x%-8x \n"
548                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
549                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
550                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
551                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
552                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
553                            MPUI1510_SHOW(MPUI_CTRL),
554                            MPUI1510_SHOW(MPUI_DSP_STATUS),
555                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
556                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
557                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
558                            MPUI1510_SHOW(EMIFS_CONFIG));
559                 } else if (cpu_is_omap16xx()) {
560                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
561                            "MPUI1610_CTRL_REG             0x%-8x \n"
562                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
563                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
564                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
565                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
566                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
567                            MPUI1610_SHOW(MPUI_CTRL),
568                            MPUI1610_SHOW(MPUI_DSP_STATUS),
569                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
570                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
571                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
572                            MPUI1610_SHOW(EMIFS_CONFIG));
573                 }
574
575                 g_read_completed++;
576         } else if (g_read_completed >= 1) {
577                  *eof = 1;
578                  return 0;
579         }
580         g_read_completed++;
581
582         *my_first_byte = page_buffer;
583         return  my_buffer_offset;
584 }
585
586 static void omap_pm_init_proc(void)
587 {
588         struct proc_dir_entry *entry;
589
590         entry = create_proc_read_entry("driver/omap_pm",
591                                        S_IWUSR | S_IRUGO, NULL,
592                                        omap_pm_read_proc, NULL);
593 }
594
595 #endif /* DEBUG && CONFIG_PROC_FS */
596
597 static void (*saved_idle)(void) = NULL;
598
599 /*
600  *      omap_pm_prepare - Do preliminary suspend work.
601  *
602  */
603 static int omap_pm_prepare(void)
604 {
605         /* We cannot sleep in idle until we have resumed */
606         saved_idle = pm_idle;
607         pm_idle = NULL;
608
609         return 0;
610 }
611
612
613 /*
614  *      omap_pm_enter - Actually enter a sleep state.
615  *      @state:         State we're entering.
616  *
617  */
618
619 static int omap_pm_enter(suspend_state_t state)
620 {
621         switch (state)
622         {
623         case PM_SUSPEND_STANDBY:
624         case PM_SUSPEND_MEM:
625                 omap_pm_suspend();
626                 break;
627         default:
628                 return -EINVAL;
629         }
630
631         return 0;
632 }
633
634
635 /**
636  *      omap_pm_finish - Finish up suspend sequence.
637  *
638  *      This is called after we wake back up (or if entering the sleep state
639  *      failed).
640  */
641
642 static void omap_pm_finish(void)
643 {
644         pm_idle = saved_idle;
645 }
646
647
648 static irqreturn_t  omap_wakeup_interrupt(int irq, void *dev)
649 {
650         return IRQ_HANDLED;
651 }
652
653 static struct irqaction omap_wakeup_irq = {
654         .name           = "peripheral wakeup",
655         .flags          = IRQF_DISABLED,
656         .handler        = omap_wakeup_interrupt
657 };
658
659
660
661 static struct platform_suspend_ops omap_pm_ops ={
662         .prepare        = omap_pm_prepare,
663         .enter          = omap_pm_enter,
664         .finish         = omap_pm_finish,
665         .valid          = suspend_valid_only_mem,
666 };
667
668 static int __init omap_pm_init(void)
669 {
670         int error;
671
672         printk("Power Management for TI OMAP.\n");
673
674         /*
675          * We copy the assembler sleep/wakeup routines to SRAM.
676          * These routines need to be in SRAM as that's the only
677          * memory the MPU can see when it wakes up.
678          */
679         if (cpu_is_omap730()) {
680                 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
681                                                 omap730_idle_loop_suspend_sz);
682                 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
683                                                    omap730_cpu_suspend_sz);
684         } else if (cpu_is_omap15xx()) {
685                 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
686                                                 omap1510_idle_loop_suspend_sz);
687                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
688                                                    omap1510_cpu_suspend_sz);
689         } else if (cpu_is_omap16xx()) {
690                 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
691                                                 omap1610_idle_loop_suspend_sz);
692                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
693                                                    omap1610_cpu_suspend_sz);
694         }
695
696         if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
697                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
698                 return -ENODEV;
699         }
700
701         pm_idle = omap_pm_idle;
702
703         if (cpu_is_omap730())
704                 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
705         else if (cpu_is_omap16xx())
706                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
707
708         /* Program new power ramp-up time
709          * (0 for most boards since we don't lower voltage when in deep sleep)
710          */
711         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
712
713         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
714         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
715
716         /* Configure IDLECT3 */
717         if (cpu_is_omap730())
718                 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
719         else if (cpu_is_omap16xx())
720                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
721
722         suspend_set_ops(&omap_pm_ops);
723
724 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
725         omap_pm_init_proc();
726 #endif
727
728         error = subsys_create_file(power_kset, &sleep_while_idle_attr);
729         if (error)
730                 printk(KERN_ERR "subsys_create_file failed: %d\n", error);
731
732         if (cpu_is_omap16xx()) {
733                 /* configure LOW_PWR pin */
734                 omap_cfg_reg(T20_1610_LOW_PWR);
735         }
736
737         return 0;
738 }
739 __initcall(omap_pm_init);