ARM: Consolidate clks_register() and similar
[linux-2.6.git] / arch / arm / mach-mx2 / clock_imx27.c
1 /*
2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4  * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version 2
9  * of the License, or (at your option) any later version.
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18  * MA 02110-1301, USA.
19  */
20
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/module.h>
24
25 #include <asm/clkdev.h>
26 #include <asm/div64.h>
27
28 #include <mach/clock.h>
29 #include <mach/common.h>
30 #include <mach/hardware.h>
31
32 /* Register offsets */
33 #define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
34 #define CCM_MPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
35 #define CCM_MPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
36 #define CCM_SPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
37 #define CCM_SPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
38 #define CCM_OSC26MCTL           (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
39 #define CCM_PCDR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
40 #define CCM_PCDR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
41 #define CCM_PCCR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
42 #define CCM_PCCR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
43 #define CCM_CCSR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
44 #define CCM_PMCTL               (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
45 #define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
46 #define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
47
48 #define CCM_CSCR_UPDATE_DIS     (1 << 31)
49 #define CCM_CSCR_SSI2           (1 << 23)
50 #define CCM_CSCR_SSI1           (1 << 22)
51 #define CCM_CSCR_VPU            (1 << 21)
52 #define CCM_CSCR_MSHC           (1 << 20)
53 #define CCM_CSCR_SPLLRES        (1 << 19)
54 #define CCM_CSCR_MPLLRES        (1 << 18)
55 #define CCM_CSCR_SP             (1 << 17)
56 #define CCM_CSCR_MCU            (1 << 16)
57 #define CCM_CSCR_OSC26MDIV      (1 << 4)
58 #define CCM_CSCR_OSC26M         (1 << 3)
59 #define CCM_CSCR_FPM            (1 << 2)
60 #define CCM_CSCR_SPEN           (1 << 1)
61 #define CCM_CSCR_MPEN           (1 << 0)
62
63 /* i.MX27 TO 2+ */
64 #define CCM_CSCR_ARM_SRC        (1 << 15)
65
66 #define CCM_SPCTL1_LF           (1 << 15)
67 #define CCM_SPCTL1_BRMO         (1 << 6)
68
69 static struct clk mpll_main1_clk, mpll_main2_clk;
70
71 static int clk_pccr_enable(struct clk *clk)
72 {
73         unsigned long reg;
74
75         if (!clk->enable_reg)
76                 return 0;
77
78         reg = __raw_readl(clk->enable_reg);
79         reg |= 1 << clk->enable_shift;
80         __raw_writel(reg, clk->enable_reg);
81
82         return 0;
83 }
84
85 static void clk_pccr_disable(struct clk *clk)
86 {
87         unsigned long reg;
88
89         if (!clk->enable_reg)
90                 return;
91
92         reg = __raw_readl(clk->enable_reg);
93         reg &= ~(1 << clk->enable_shift);
94         __raw_writel(reg, clk->enable_reg);
95 }
96
97 static int clk_spll_enable(struct clk *clk)
98 {
99         unsigned long reg;
100
101         reg = __raw_readl(CCM_CSCR);
102         reg |= CCM_CSCR_SPEN;
103         __raw_writel(reg, CCM_CSCR);
104
105         while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
106
107         return 0;
108 }
109
110 static void clk_spll_disable(struct clk *clk)
111 {
112         unsigned long reg;
113
114         reg = __raw_readl(CCM_CSCR);
115         reg &= ~CCM_CSCR_SPEN;
116         __raw_writel(reg, CCM_CSCR);
117 }
118
119 static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
120 {
121         int cscr = __raw_readl(CCM_CSCR);
122
123         if (clk->parent == parent)
124                 return 0;
125
126         if (mx27_revision() >= CHIP_REV_2_0) {
127                 if (parent == &mpll_main1_clk) {
128                         cscr |= CCM_CSCR_ARM_SRC;
129                 } else {
130                         if (parent == &mpll_main2_clk)
131                                 cscr &= ~CCM_CSCR_ARM_SRC;
132                         else
133                                 return -EINVAL;
134                 }
135                 __raw_writel(cscr, CCM_CSCR);
136                 clk->parent = parent;
137                 return 0;
138         }
139         return -ENODEV;
140 }
141
142 static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
143 {
144         int div;
145         unsigned long parent_rate;
146
147         parent_rate = clk_get_rate(clk->parent);
148
149         div = parent_rate / rate;
150         if (parent_rate % rate)
151                 div++;
152
153         if (div > 4)
154                 div = 4;
155
156         return parent_rate / div;
157 }
158
159 static int set_rate_cpu(struct clk *clk, unsigned long rate)
160 {
161         unsigned int div;
162         uint32_t reg;
163         unsigned long parent_rate;
164
165         parent_rate = clk_get_rate(clk->parent);
166
167         div = parent_rate / rate;
168
169         if (div > 4 || div < 1 || ((parent_rate / div) != rate))
170                 return -EINVAL;
171
172         div--;
173
174         reg = __raw_readl(CCM_CSCR);
175         if (mx27_revision() >= CHIP_REV_2_0) {
176                 reg &= ~(3 << 12);
177                 reg |= div << 12;
178                 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
179                 __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
180         } else {
181                 printk(KERN_ERR "Can't set CPU frequency!\n");
182         }
183
184         return 0;
185 }
186
187 static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
188 {
189         u32 div;
190         unsigned long parent_rate;
191
192         parent_rate = clk_get_rate(clk->parent);
193
194         div = parent_rate / rate;
195         if (parent_rate % rate)
196                 div++;
197
198         if (div > 64)
199                 div = 64;
200
201         return parent_rate / div;
202 }
203
204 static int set_rate_per(struct clk *clk, unsigned long rate)
205 {
206         u32 reg;
207         u32 div;
208         unsigned long parent_rate;
209
210         parent_rate = clk_get_rate(clk->parent);
211
212         if (clk->id < 0 || clk->id > 3)
213                 return -EINVAL;
214
215         div = parent_rate / rate;
216         if (div > 64 || div < 1 || ((parent_rate / div) != rate))
217                 return -EINVAL;
218         div--;
219
220         reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
221         reg |= div << (clk->id << 3);
222         __raw_writel(reg, CCM_PCDR1);
223
224         return 0;
225 }
226
227 static unsigned long get_rate_usb(struct clk *clk)
228 {
229         unsigned long usb_pdf;
230         unsigned long parent_rate;
231
232         parent_rate = clk_get_rate(clk->parent);
233
234         usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
235
236         return parent_rate / (usb_pdf + 1U);
237 }
238
239 static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
240 {
241         unsigned long parent_rate;
242
243         parent_rate = clk_get_rate(clk->parent);
244
245         if (mx27_revision() >= CHIP_REV_2_0)
246                 pdf += 4;  /* MX27 TO2+ */
247         else
248                 pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
249
250         return 2UL * parent_rate / pdf;
251 }
252
253 static unsigned long get_rate_ssi1(struct clk *clk)
254 {
255         return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
256 }
257
258 static unsigned long get_rate_ssi2(struct clk *clk)
259 {
260         return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
261 }
262
263 static unsigned long get_rate_nfc(struct clk *clk)
264 {
265         unsigned long nfc_pdf;
266         unsigned long parent_rate;
267
268         parent_rate = clk_get_rate(clk->parent);
269
270         if (mx27_revision() >= CHIP_REV_2_0)
271                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
272         else
273                 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
274
275         return parent_rate / (nfc_pdf + 1);
276 }
277
278 static unsigned long get_rate_vpu(struct clk *clk)
279 {
280         unsigned long vpu_pdf;
281         unsigned long parent_rate;
282
283         parent_rate = clk_get_rate(clk->parent);
284
285         if (mx27_revision() >= CHIP_REV_2_0) {
286                 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
287                 vpu_pdf += 4;
288         } else {
289                 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
290                 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
291         }
292
293         return 2UL * parent_rate / vpu_pdf;
294 }
295
296 static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
297 {
298         return clk->parent->round_rate(clk->parent, rate);
299 }
300
301 static unsigned long get_rate_parent(struct clk *clk)
302 {
303         return clk_get_rate(clk->parent);
304 }
305
306 static int set_rate_parent(struct clk *clk, unsigned long rate)
307 {
308         return clk->parent->set_rate(clk->parent, rate);
309 }
310
311 /* in Hz */
312 static unsigned long external_high_reference = 26000000;
313
314 static unsigned long get_rate_high_reference(struct clk *clk)
315 {
316         return external_high_reference;
317 }
318
319 /* in Hz */
320 static unsigned long external_low_reference = 32768;
321
322 static unsigned long get_rate_low_reference(struct clk *clk)
323 {
324         return external_low_reference;
325 }
326
327 static unsigned long get_rate_fpm(struct clk *clk)
328 {
329         return clk_get_rate(clk->parent) * 1024;
330 }
331
332 static unsigned long get_rate_mpll(struct clk *clk)
333 {
334         return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
335                         clk_get_rate(clk->parent));
336 }
337
338 static unsigned long get_rate_mpll_main(struct clk *clk)
339 {
340         unsigned long parent_rate;
341
342         parent_rate = clk_get_rate(clk->parent);
343
344         /* i.MX27 TO2:
345          * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
346          * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
347          */
348         if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
349                 return 2UL * parent_rate / 3UL;
350
351         return parent_rate;
352 }
353
354 static unsigned long get_rate_spll(struct clk *clk)
355 {
356         uint32_t reg;
357         unsigned long rate;
358
359         rate = clk_get_rate(clk->parent);
360
361         reg = __raw_readl(CCM_SPCTL0);
362
363         /* On TO2 we have to write the value back. Otherwise we
364          * read 0 from this register the next time.
365          */
366         if (mx27_revision() >= CHIP_REV_2_0)
367                 __raw_writel(reg, CCM_SPCTL0);
368
369         return mxc_decode_pll(reg, rate);
370 }
371
372 static unsigned long get_rate_cpu(struct clk *clk)
373 {
374         u32 div;
375         unsigned long rate;
376
377         if (mx27_revision() >= CHIP_REV_2_0)
378                 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
379         else
380                 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
381
382         rate = clk_get_rate(clk->parent);
383         return rate / (div + 1);
384 }
385
386 static unsigned long get_rate_ahb(struct clk *clk)
387 {
388         unsigned long rate, bclk_pdf;
389
390         if (mx27_revision() >= CHIP_REV_2_0)
391                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
392         else
393                 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
394
395         rate = clk_get_rate(clk->parent);
396         return rate / (bclk_pdf + 1);
397 }
398
399 static unsigned long get_rate_ipg(struct clk *clk)
400 {
401         unsigned long rate, ipg_pdf;
402
403         if (mx27_revision() >= CHIP_REV_2_0)
404                 return clk_get_rate(clk->parent);
405         else
406                 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
407
408         rate = clk_get_rate(clk->parent);
409         return rate / (ipg_pdf + 1);
410 }
411
412 static unsigned long get_rate_per(struct clk *clk)
413 {
414         unsigned long perclk_pdf, parent_rate;
415
416         parent_rate = clk_get_rate(clk->parent);
417
418         if (clk->id < 0 || clk->id > 3)
419                 return 0;
420
421         perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
422
423         return parent_rate / (perclk_pdf + 1);
424 }
425
426 /*
427  * the high frequency external clock reference
428  * Default case is 26MHz. Could be changed at runtime
429  * with a call to change_external_high_reference()
430  */
431 static struct clk ckih_clk = {
432         .get_rate       = get_rate_high_reference,
433 };
434
435 static struct clk mpll_clk = {
436         .parent         = &ckih_clk,
437         .get_rate       = get_rate_mpll,
438 };
439
440 /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
441  * It provides the clock source whose rate is same as MPLL
442  */
443 static struct clk mpll_main1_clk = {
444         .id             = 0,
445         .parent         = &mpll_clk,
446         .get_rate       = get_rate_mpll_main,
447 };
448
449 /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
450  * It provides the clock source whose rate is same MPLL * 2 / 3
451  */
452 static struct clk mpll_main2_clk = {
453         .id             = 1,
454         .parent         = &mpll_clk,
455         .get_rate       = get_rate_mpll_main,
456 };
457
458 static struct clk ahb_clk = {
459         .parent         = &mpll_main2_clk,
460         .get_rate       = get_rate_ahb,
461 };
462
463 static struct clk ipg_clk = {
464         .parent         = &ahb_clk,
465         .get_rate       = get_rate_ipg,
466 };
467
468 static struct clk cpu_clk = {
469         .parent = &mpll_main2_clk,
470         .set_parent = clk_cpu_set_parent,
471         .round_rate = round_rate_cpu,
472         .get_rate = get_rate_cpu,
473         .set_rate = set_rate_cpu,
474 };
475
476 static struct clk spll_clk = {
477         .parent = &ckih_clk,
478         .get_rate = get_rate_spll,
479         .enable = clk_spll_enable,
480         .disable = clk_spll_disable,
481 };
482
483 /*
484  * the low frequency external clock reference
485  * Default case is 32.768kHz.
486  */
487 static struct clk ckil_clk = {
488         .get_rate = get_rate_low_reference,
489 };
490
491 /* Output of frequency pre multiplier */
492 static struct clk fpm_clk = {
493         .parent = &ckil_clk,
494         .get_rate = get_rate_fpm,
495 };
496
497 #define PCCR0 CCM_PCCR0
498 #define PCCR1 CCM_PCCR1
499
500 #define DEFINE_CLOCK(name, i, er, es, gr, s, p)         \
501         static struct clk name = {                      \
502                 .id             = i,                    \
503                 .enable_reg     = er,                   \
504                 .enable_shift   = es,                   \
505                 .get_rate       = gr,                   \
506                 .enable         = clk_pccr_enable,      \
507                 .disable        = clk_pccr_disable,     \
508                 .secondary      = s,                    \
509                 .parent         = p,                    \
510         }
511
512 #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p)       \
513         static struct clk name = {                              \
514                 .id             = i,                            \
515                 .enable_reg     = er,                           \
516                 .enable_shift   = es,                           \
517                 .get_rate       = get_rate_##getsetround,       \
518                 .set_rate       = set_rate_##getsetround,       \
519                 .round_rate     = round_rate_##getsetround,     \
520                 .enable         = clk_pccr_enable,              \
521                 .disable        = clk_pccr_disable,             \
522                 .secondary      = s,                            \
523                 .parent         = p,                            \
524         }
525
526 /* Forward declaration to keep the following list in order */
527 static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
528                   dma_clk1, lcdc_clk2, vpu_clk1;
529
530 /* All clocks we can gate through PCCRx in the order of PCCRx bits */
531 DEFINE_CLOCK(ssi2_clk1,    1, PCCR0,  0, NULL, NULL, &ipg_clk);
532 DEFINE_CLOCK(ssi1_clk1,    0, PCCR0,  1, NULL, NULL, &ipg_clk);
533 DEFINE_CLOCK(slcdc_clk,    0, PCCR0,  2, NULL, &slcdc_clk1, &ahb_clk);
534 DEFINE_CLOCK(sdhc3_clk1,   0, PCCR0,  3, NULL, NULL, &ipg_clk);
535 DEFINE_CLOCK(sdhc2_clk1,   0, PCCR0,  4, NULL, NULL, &ipg_clk);
536 DEFINE_CLOCK(sdhc1_clk1,   0, PCCR0,  5, NULL, NULL, &ipg_clk);
537 DEFINE_CLOCK(scc_clk,      0, PCCR0,  6, NULL, NULL, &ipg_clk);
538 DEFINE_CLOCK(sahara2_clk,  0, PCCR0,  7, NULL, &sahara2_clk1, &ahb_clk);
539 DEFINE_CLOCK(rtic_clk,     0, PCCR0,  8, NULL, &rtic_clk1, &ahb_clk);
540 DEFINE_CLOCK(rtc_clk,      0, PCCR0,  9, NULL, NULL, &ipg_clk);
541 DEFINE_CLOCK(pwm_clk1,     0, PCCR0, 11, NULL, NULL, &ipg_clk);
542 DEFINE_CLOCK(owire_clk,    0, PCCR0, 12, NULL, NULL, &ipg_clk);
543 DEFINE_CLOCK(mstick_clk1,  0, PCCR0, 13, NULL, NULL, &ipg_clk);
544 DEFINE_CLOCK(lcdc_clk1,    0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
545 DEFINE_CLOCK(kpp_clk,      0, PCCR0, 15, NULL, NULL, &ipg_clk);
546 DEFINE_CLOCK(iim_clk,      0, PCCR0, 16, NULL, NULL, &ipg_clk);
547 DEFINE_CLOCK(i2c2_clk,     1, PCCR0, 17, NULL, NULL, &ipg_clk);
548 DEFINE_CLOCK(i2c1_clk,     0, PCCR0, 18, NULL, NULL, &ipg_clk);
549 DEFINE_CLOCK(gpt6_clk1,    0, PCCR0, 29, NULL, NULL, &ipg_clk);
550 DEFINE_CLOCK(gpt5_clk1,    0, PCCR0, 20, NULL, NULL, &ipg_clk);
551 DEFINE_CLOCK(gpt4_clk1,    0, PCCR0, 21, NULL, NULL, &ipg_clk);
552 DEFINE_CLOCK(gpt3_clk1,    0, PCCR0, 22, NULL, NULL, &ipg_clk);
553 DEFINE_CLOCK(gpt2_clk1,    0, PCCR0, 23, NULL, NULL, &ipg_clk);
554 DEFINE_CLOCK(gpt1_clk1,    0, PCCR0, 24, NULL, NULL, &ipg_clk);
555 DEFINE_CLOCK(gpio_clk,     0, PCCR0, 25, NULL, NULL, &ipg_clk);
556 DEFINE_CLOCK(fec_clk,      0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
557 DEFINE_CLOCK(emma_clk,     0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
558 DEFINE_CLOCK(dma_clk,      0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
559 DEFINE_CLOCK(cspi13_clk1,  0, PCCR0, 29, NULL, NULL, &ipg_clk);
560 DEFINE_CLOCK(cspi2_clk1,   0, PCCR0, 30, NULL, NULL, &ipg_clk);
561 DEFINE_CLOCK(cspi1_clk1,   0, PCCR0, 31, NULL, NULL, &ipg_clk);
562
563 DEFINE_CLOCK(mstick_clk,   0, PCCR1,  2, NULL, &mstick_clk1, &ipg_clk);
564 DEFINE_CLOCK(nfc_clk,      0, PCCR1,  3, get_rate_nfc, NULL, &cpu_clk);
565 DEFINE_CLOCK(ssi2_clk,     1, PCCR1,  4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
566 DEFINE_CLOCK(ssi1_clk,     0, PCCR1,  5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
567 DEFINE_CLOCK(vpu_clk,      0, PCCR1,  6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
568 DEFINE_CLOCK1(per4_clk,    3, PCCR1,  7, per, NULL, &mpll_main2_clk);
569 DEFINE_CLOCK1(per3_clk,    2, PCCR1,  8, per, NULL, &mpll_main2_clk);
570 DEFINE_CLOCK1(per2_clk,    1, PCCR1,  9, per, NULL, &mpll_main2_clk);
571 DEFINE_CLOCK1(per1_clk,    0, PCCR1, 10, per, NULL, &mpll_main2_clk);
572 DEFINE_CLOCK(usb_clk1,     0, PCCR1, 11, NULL, NULL, &ahb_clk);
573 DEFINE_CLOCK(slcdc_clk1,   0, PCCR1, 12, NULL, NULL, &ahb_clk);
574 DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
575 DEFINE_CLOCK(rtic_clk1,    0, PCCR1, 14, NULL, NULL, &ahb_clk);
576 DEFINE_CLOCK(lcdc_clk2,    0, PCCR1, 15, NULL, NULL, &ahb_clk);
577 DEFINE_CLOCK(vpu_clk1,     0, PCCR1, 16, NULL, NULL, &ahb_clk);
578 DEFINE_CLOCK(fec_clk1,     0, PCCR1, 17, NULL, NULL, &ahb_clk);
579 DEFINE_CLOCK(emma_clk1,    0, PCCR1, 18, NULL, NULL, &ahb_clk);
580 DEFINE_CLOCK(emi_clk,      0, PCCR1, 19, NULL, NULL, &ahb_clk);
581 DEFINE_CLOCK(dma_clk1,     0, PCCR1, 20, NULL, NULL, &ahb_clk);
582 DEFINE_CLOCK(csi_clk1,     0, PCCR1, 21, NULL, NULL, &ahb_clk);
583 DEFINE_CLOCK(brom_clk,     0, PCCR1, 22, NULL, NULL, &ahb_clk);
584 DEFINE_CLOCK(ata_clk,      0, PCCR1, 23, NULL, NULL, &ahb_clk);
585 DEFINE_CLOCK(wdog_clk,     0, PCCR1, 24, NULL, NULL, &ipg_clk);
586 DEFINE_CLOCK(usb_clk,      0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
587 DEFINE_CLOCK(uart6_clk1,   0, PCCR1, 26, NULL, NULL, &ipg_clk);
588 DEFINE_CLOCK(uart5_clk1,   0, PCCR1, 27, NULL, NULL, &ipg_clk);
589 DEFINE_CLOCK(uart4_clk1,   0, PCCR1, 28, NULL, NULL, &ipg_clk);
590 DEFINE_CLOCK(uart3_clk1,   0, PCCR1, 29, NULL, NULL, &ipg_clk);
591 DEFINE_CLOCK(uart2_clk1,   0, PCCR1, 30, NULL, NULL, &ipg_clk);
592 DEFINE_CLOCK(uart1_clk1,   0, PCCR1, 31, NULL, NULL, &ipg_clk);
593
594 /* Clocks we cannot directly gate, but drivers need their rates */
595 DEFINE_CLOCK(cspi1_clk,    0, 0,      0, NULL, &cspi1_clk1, &per2_clk);
596 DEFINE_CLOCK(cspi2_clk,    1, 0,      0, NULL, &cspi2_clk1, &per2_clk);
597 DEFINE_CLOCK(cspi3_clk,    2, 0,      0, NULL, &cspi13_clk1, &per2_clk);
598 DEFINE_CLOCK(sdhc1_clk,    0, 0,      0, NULL, &sdhc1_clk1, &per2_clk);
599 DEFINE_CLOCK(sdhc2_clk,    1, 0,      0, NULL, &sdhc2_clk1, &per2_clk);
600 DEFINE_CLOCK(sdhc3_clk,    2, 0,      0, NULL, &sdhc3_clk1, &per2_clk);
601 DEFINE_CLOCK(pwm_clk,      0, 0,      0, NULL, &pwm_clk1, &per1_clk);
602 DEFINE_CLOCK(gpt1_clk,     0, 0,      0, NULL, &gpt1_clk1, &per1_clk);
603 DEFINE_CLOCK(gpt2_clk,     1, 0,      0, NULL, &gpt2_clk1, &per1_clk);
604 DEFINE_CLOCK(gpt3_clk,     2, 0,      0, NULL, &gpt3_clk1, &per1_clk);
605 DEFINE_CLOCK(gpt4_clk,     3, 0,      0, NULL, &gpt4_clk1, &per1_clk);
606 DEFINE_CLOCK(gpt5_clk,     4, 0,      0, NULL, &gpt5_clk1, &per1_clk);
607 DEFINE_CLOCK(gpt6_clk,     5, 0,      0, NULL, &gpt6_clk1, &per1_clk);
608 DEFINE_CLOCK(uart1_clk,    0, 0,      0, NULL, &uart1_clk1, &per1_clk);
609 DEFINE_CLOCK(uart2_clk,    1, 0,      0, NULL, &uart2_clk1, &per1_clk);
610 DEFINE_CLOCK(uart3_clk,    2, 0,      0, NULL, &uart3_clk1, &per1_clk);
611 DEFINE_CLOCK(uart4_clk,    3, 0,      0, NULL, &uart4_clk1, &per1_clk);
612 DEFINE_CLOCK(uart5_clk,    4, 0,      0, NULL, &uart5_clk1, &per1_clk);
613 DEFINE_CLOCK(uart6_clk,    5, 0,      0, NULL, &uart6_clk1, &per1_clk);
614 DEFINE_CLOCK1(lcdc_clk,    0, 0,      0, parent, &lcdc_clk1, &per3_clk);
615 DEFINE_CLOCK1(csi_clk,     0, 0,      0, parent, &csi_clk1, &per4_clk);
616
617 #define _REGISTER_CLOCK(d, n, c) \
618         { \
619                 .dev_id = d, \
620                 .con_id = n, \
621                 .clk = &c, \
622         },
623
624 static struct clk_lookup lookups[] = {
625         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
626         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
627         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
628         _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
629         _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
630         _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
631         _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
632         _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
633         _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
634         _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
635         _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
636         _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
637         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
638         _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
639         _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
640         _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
641         _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
642         _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
643         _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
644         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
645         _REGISTER_CLOCK(NULL, "csi", csi_clk)
646         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
647         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
648         _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
649         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
650         _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
651         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
652         _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
653         _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
654         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
655         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
656         _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
657         _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
658         _REGISTER_CLOCK(NULL, "dma", dma_clk)
659         _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
660         _REGISTER_CLOCK(NULL, "brom", brom_clk)
661         _REGISTER_CLOCK(NULL, "emma", emma_clk)
662         _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
663         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
664         _REGISTER_CLOCK(NULL, "emi", emi_clk)
665         _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
666         _REGISTER_CLOCK(NULL, "ata", ata_clk)
667         _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
668         _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
669         _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
670         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
671         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
672         _REGISTER_CLOCK(NULL, "iim", iim_clk)
673         _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
674         _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
675         _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
676         _REGISTER_CLOCK(NULL, "scc", scc_clk)
677 };
678
679 /* Adjust the clock path for TO2 and later */
680 static void __init to2_adjust_clocks(void)
681 {
682         unsigned long cscr = __raw_readl(CCM_CSCR);
683
684         if (mx27_revision() >= CHIP_REV_2_0) {
685                 if (cscr & CCM_CSCR_ARM_SRC)
686                         cpu_clk.parent = &mpll_main1_clk;
687
688                 if (!(cscr & CCM_CSCR_SSI2))
689                         ssi1_clk.parent = &spll_clk;
690
691                 if (!(cscr & CCM_CSCR_SSI1))
692                         ssi1_clk.parent = &spll_clk;
693
694                 if (!(cscr & CCM_CSCR_VPU))
695                         vpu_clk.parent = &spll_clk;
696         } else {
697                 cpu_clk.parent = &mpll_clk;
698                 cpu_clk.set_parent = NULL;
699                 cpu_clk.round_rate = NULL;
700                 cpu_clk.set_rate = NULL;
701                 ahb_clk.parent = &mpll_clk;
702
703                 per1_clk.parent = &mpll_clk;
704                 per2_clk.parent = &mpll_clk;
705                 per3_clk.parent = &mpll_clk;
706                 per4_clk.parent = &mpll_clk;
707
708                 ssi1_clk.parent = &mpll_clk;
709                 ssi2_clk.parent = &mpll_clk;
710
711                 vpu_clk.parent = &mpll_clk;
712         }
713 }
714
715 /*
716  * must be called very early to get information about the
717  * available clock rate when the timer framework starts
718  */
719 int __init mx27_clocks_init(unsigned long fref)
720 {
721         u32 cscr = __raw_readl(CCM_CSCR);
722
723         external_high_reference = fref;
724
725         /* detect clock reference for both system PLLs */
726         if (cscr & CCM_CSCR_MCU)
727                 mpll_clk.parent = &ckih_clk;
728         else
729                 mpll_clk.parent = &fpm_clk;
730
731         if (cscr & CCM_CSCR_SP)
732                 spll_clk.parent = &ckih_clk;
733         else
734                 spll_clk.parent = &fpm_clk;
735
736         to2_adjust_clocks();
737
738         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
739
740         /* Turn off all clocks we do not need */
741         __raw_writel(0, CCM_PCCR0);
742         __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
743
744         spll_clk.disable(&spll_clk);
745
746         /* enable basic clocks */
747         clk_enable(&per1_clk);
748         clk_enable(&gpio_clk);
749         clk_enable(&emi_clk);
750         clk_enable(&iim_clk);
751
752 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
753         clk_enable(&uart1_clk);
754 #endif
755
756         mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
757
758         return 0;
759 }
760