[ARM] mmp2: add handling on PMIC IRQ
[linux-2.6.git] / arch / arm / mach-mmp / irq-mmp2.c
1 /*
2  *  linux/arch/arm/mach-mmp/irq-mmp2.c
3  *
4  *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5  *
6  *  Author:     Haojian Zhuang <haojian.zhuang@marvell.com>
7  *  Copyright:  Marvell International Ltd.
8  *
9  *  This program is free software; you can redistribute it and/or modify
10  *  it under the terms of the GNU General Public License version 2 as
11  *  published by the Free Software Foundation.
12  */
13
14 #include <linux/init.h>
15 #include <linux/irq.h>
16 #include <linux/io.h>
17
18 #include <mach/regs-icu.h>
19
20 #include "common.h"
21
22 static void icu_mask_irq(unsigned int irq)
23 {
24         uint32_t r = __raw_readl(ICU_INT_CONF(irq));
25
26         r &= ~ICU_INT_ROUTE_PJ4_IRQ;
27         __raw_writel(r, ICU_INT_CONF(irq));
28 }
29
30 static void icu_unmask_irq(unsigned int irq)
31 {
32         uint32_t r = __raw_readl(ICU_INT_CONF(irq));
33
34         r |= ICU_INT_ROUTE_PJ4_IRQ;
35         __raw_writel(r, ICU_INT_CONF(irq));
36 }
37
38 static struct irq_chip icu_irq_chip = {
39         .name           = "icu_irq",
40         .mask           = icu_mask_irq,
41         .mask_ack       = icu_mask_irq,
42         .unmask         = icu_unmask_irq,
43 };
44
45 static void pmic_irq_ack(unsigned int irq)
46 {
47         if (irq == IRQ_MMP2_PMIC)
48                 mmp2_clear_pmic_int();
49 }
50
51 #define SECOND_IRQ_MASK(_name_, irq_base, prefix)                       \
52 static void _name_##_mask_irq(unsigned int irq)                         \
53 {                                                                       \
54         uint32_t r;                                                     \
55         r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base));       \
56         __raw_writel(r, prefix##_MASK);                                 \
57 }
58
59 #define SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                     \
60 static void _name_##_unmask_irq(unsigned int irq)                       \
61 {                                                                       \
62         uint32_t r;                                                     \
63         r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base));      \
64         __raw_writel(r, prefix##_MASK);                                 \
65 }
66
67 #define SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                      \
68 static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
69 {                                                                       \
70         unsigned long status, mask, n;                                  \
71         mask = __raw_readl(prefix##_MASK);                              \
72         while (1) {                                                     \
73                 status = __raw_readl(prefix##_STATUS) & ~mask;          \
74                 if (status == 0)                                        \
75                         break;                                          \
76                 n = find_first_bit(&status, BITS_PER_LONG);             \
77                 while (n < BITS_PER_LONG) {                             \
78                         generic_handle_irq(irq_base + n);               \
79                         n = find_next_bit(&status, BITS_PER_LONG, n+1); \
80                 }                                                       \
81         }                                                               \
82 }
83
84 #define SECOND_IRQ_CHIP(_name_, irq_base, prefix)                       \
85 SECOND_IRQ_MASK(_name_, irq_base, prefix)                               \
86 SECOND_IRQ_UNMASK(_name_, irq_base, prefix)                             \
87 SECOND_IRQ_DEMUX(_name_, irq_base, prefix)                              \
88 static struct irq_chip _name_##_irq_chip = {                            \
89         .name           = #_name_,                                      \
90         .mask           = _name_##_mask_irq,                            \
91         .unmask         = _name_##_unmask_irq,                          \
92 }
93
94 SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
95 SECOND_IRQ_CHIP(rtc,  IRQ_MMP2_RTC_BASE,  MMP2_ICU_INT5);
96 SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
97 SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
98 SECOND_IRQ_CHIP(ssp,  IRQ_MMP2_SSP_BASE,  MMP2_ICU_INT51);
99
100 static void init_mux_irq(struct irq_chip *chip, int start, int num)
101 {
102         int irq;
103
104         for (irq = start; num > 0; irq++, num--) {
105                 chip->mask_ack(irq);
106                 set_irq_chip(irq, chip);
107                 set_irq_flags(irq, IRQF_VALID);
108                 set_irq_handler(irq, handle_level_irq);
109         }
110 }
111
112 void __init mmp2_init_icu(void)
113 {
114         int irq;
115
116         for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
117                 icu_mask_irq(irq);
118                 set_irq_chip(irq, &icu_irq_chip);
119                 set_irq_flags(irq, IRQF_VALID);
120
121                 switch (irq) {
122                 case IRQ_MMP2_PMIC_MUX:
123                 case IRQ_MMP2_RTC_MUX:
124                 case IRQ_MMP2_TWSI_MUX:
125                 case IRQ_MMP2_MISC_MUX:
126                 case IRQ_MMP2_SSP_MUX:
127                         break;
128                 default:
129                         set_irq_handler(irq, handle_level_irq);
130                         break;
131                 }
132         }
133
134         /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
135          * to be written to clear the interrupt
136          */
137         pmic_irq_chip.ack = pmic_irq_ack;
138
139         init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
140         init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
141         init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
142         init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
143         init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
144
145         set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
146         set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
147         set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
148         set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
149         set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
150 }