f20ff64604855ddc8ba723cf460319bfdee5001e
[linux-2.6.git] / arch / arm / mach-kirkwood / include / mach / kirkwood.h
1 /*
2  * arch/arm/mach-kirkwood/include/mach/kirkwood.h
3  *
4  * Generic definitions for Marvell Kirkwood SoC flavors:
5  *  88F6180, 88F6192 and 88F6281.
6  *
7  * This file is licensed under the terms of the GNU General Public
8  * License version 2.  This program is licensed "as is" without any
9  * warranty of any kind, whether express or implied.
10  */
11
12 #ifndef __ASM_ARCH_KIRKWOOD_H
13 #define __ASM_ARCH_KIRKWOOD_H
14
15 /*
16  * Marvell Kirkwood address maps.
17  *
18  * phys
19  * e0000000     PCIe Memory space
20  * f1000000     on-chip peripheral registers
21  * f2000000     PCIe I/O space
22  * f3000000     NAND controller address window
23  *
24  * virt         phys            size
25  * fee00000     f1000000        1M      on-chip peripheral registers
26  * fef00000     f2000000        1M      PCIe I/O space
27  */
28
29 #define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
30 #define KIRKWOOD_NAND_MEM_SIZE          SZ_64K /* 1K is sufficient, but 64K
31                                                 * is the minimal window size
32                                                 */
33
34 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
35 #define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
36 #define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
37 #define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
38
39 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
40 #define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
41 #define KIRKWOOD_REGS_SIZE              SZ_1M
42
43 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
44 #define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
45
46 /*
47  * Register Map
48  */
49 #define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
50 #define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
51 #define DDR_OPERATION_BASE      (DDR_VIRT_BASE | 0x1418)
52
53 #define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
54 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
55 #define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
56 #define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
57 #define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
58 #define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
59 #define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
60 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
61 #define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
62 #define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
63 #define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
64
65 #define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
66
67 #define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
68
69 #define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
70
71 #define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
72 #define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
73 #define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
74 #define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
75 #define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
76 #define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
77 #define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
78 #define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
79
80 #define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
81 #define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
82
83 #define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
84
85 #define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
86
87 /*
88  * Supported devices and revisions.
89  */
90 #define MV88F6281_DEV_ID        0x6281
91 #define MV88F6281_REV_Z0        0
92 #define MV88F6281_REV_A0        2
93
94 #define MV88F6192_DEV_ID        0x6192
95 #define MV88F6192_REV_Z0        0
96 #define MV88F6192_REV_A0        2
97
98 #define MV88F6180_DEV_ID        0x6180
99 #define MV88F6180_REV_A0        2
100
101 #endif