[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
[linux-2.6.git] / arch / arm / mach-ixp23xx / core.c
1 /*
2  * arch/arm/mach-ixp23xx/core.c
3  *
4  * Core routines for IXP23xx chips
5  *
6  * Author: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2005 (c) MontaVista Software, Inc.
9  *
10  * Based on 2.4 code Copyright 2004 (c) Intel Corporation
11  *
12  * This file is licensed under the terms of the GNU General Public
13  * License version 2. This program is licensed "as is" without any
14  * warranty of any kind, whether express or implied.
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/bitops.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/device.h>
28 #include <linux/mm.h>
29 #include <linux/time.h>
30 #include <linux/timex.h>
31
32 #include <asm/types.h>
33 #include <asm/setup.h>
34 #include <asm/memory.h>
35 #include <mach/hardware.h>
36 #include <asm/irq.h>
37 #include <asm/system.h>
38 #include <asm/tlbflush.h>
39 #include <asm/pgtable.h>
40
41 #include <asm/mach/map.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/arch.h>
45
46
47 /*************************************************************************
48  * Chip specific mappings shared by all IXP23xx systems
49  *************************************************************************/
50 static struct map_desc ixp23xx_io_desc[] __initdata = {
51         { /* XSI-CPP CSRs */
52                 .virtual        = IXP23XX_XSI2CPP_CSR_VIRT,
53                 .pfn            = __phys_to_pfn(IXP23XX_XSI2CPP_CSR_PHYS),
54                 .length         = IXP23XX_XSI2CPP_CSR_SIZE,
55                 .type           = MT_DEVICE,
56         }, { /* Expansion Bus Config */
57                 .virtual        = IXP23XX_EXP_CFG_VIRT,
58                 .pfn            = __phys_to_pfn(IXP23XX_EXP_CFG_PHYS),
59                 .length         = IXP23XX_EXP_CFG_SIZE,
60                 .type           = MT_DEVICE,
61         }, { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACS,.... */
62                 .virtual        = IXP23XX_PERIPHERAL_VIRT,
63                 .pfn            = __phys_to_pfn(IXP23XX_PERIPHERAL_PHYS),
64                 .length         = IXP23XX_PERIPHERAL_SIZE,
65                 .type           = MT_DEVICE,
66         }, { /* CAP CSRs */
67                 .virtual        = IXP23XX_CAP_CSR_VIRT,
68                 .pfn            = __phys_to_pfn(IXP23XX_CAP_CSR_PHYS),
69                 .length         = IXP23XX_CAP_CSR_SIZE,
70                 .type           = MT_DEVICE,
71         }, { /* MSF CSRs */
72                 .virtual        = IXP23XX_MSF_CSR_VIRT,
73                 .pfn            = __phys_to_pfn(IXP23XX_MSF_CSR_PHYS),
74                 .length         = IXP23XX_MSF_CSR_SIZE,
75                 .type           = MT_DEVICE,
76         }, { /* PCI I/O Space */
77                 .virtual        = IXP23XX_PCI_IO_VIRT,
78                 .pfn            = __phys_to_pfn(IXP23XX_PCI_IO_PHYS),
79                 .length         = IXP23XX_PCI_IO_SIZE,
80                 .type           = MT_DEVICE,
81         }, { /* PCI Config Space */
82                 .virtual        = IXP23XX_PCI_CFG_VIRT,
83                 .pfn            = __phys_to_pfn(IXP23XX_PCI_CFG_PHYS),
84                 .length         = IXP23XX_PCI_CFG_SIZE,
85                 .type           = MT_DEVICE,
86         }, { /* PCI local CFG CSRs */
87                 .virtual        = IXP23XX_PCI_CREG_VIRT,
88                 .pfn            = __phys_to_pfn(IXP23XX_PCI_CREG_PHYS),
89                 .length         = IXP23XX_PCI_CREG_SIZE,
90                 .type           = MT_DEVICE,
91         }, { /* PCI MEM Space */
92                 .virtual        = IXP23XX_PCI_MEM_VIRT,
93                 .pfn            = __phys_to_pfn(IXP23XX_PCI_MEM_PHYS),
94                 .length         = IXP23XX_PCI_MEM_SIZE,
95                 .type           = MT_DEVICE,
96         }
97 };
98
99 void __init ixp23xx_map_io(void)
100 {
101         iotable_init(ixp23xx_io_desc, ARRAY_SIZE(ixp23xx_io_desc));
102 }
103
104
105 /***************************************************************************
106  * IXP23xx Interrupt Handling
107  ***************************************************************************/
108 enum ixp23xx_irq_type {
109         IXP23XX_IRQ_LEVEL, IXP23XX_IRQ_EDGE
110 };
111
112 static void ixp23xx_config_irq(unsigned int, enum ixp23xx_irq_type);
113
114 static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
115 {
116         int line = irq - IRQ_IXP23XX_GPIO6 + 6;
117         u32 int_style;
118         enum ixp23xx_irq_type irq_type;
119         volatile u32 *int_reg;
120
121         /*
122          * Only GPIOs 6-15 are wired to interrupts on IXP23xx
123          */
124         if (line < 6 || line > 15)
125                 return -EINVAL;
126
127         switch (type) {
128         case IRQ_TYPE_EDGE_BOTH:
129                 int_style = IXP23XX_GPIO_STYLE_TRANSITIONAL;
130                 irq_type = IXP23XX_IRQ_EDGE;
131                 break;
132         case IRQ_TYPE_EDGE_RISING:
133                 int_style = IXP23XX_GPIO_STYLE_RISING_EDGE;
134                 irq_type = IXP23XX_IRQ_EDGE;
135                 break;
136         case IRQ_TYPE_EDGE_FALLING:
137                 int_style = IXP23XX_GPIO_STYLE_FALLING_EDGE;
138                 irq_type = IXP23XX_IRQ_EDGE;
139                 break;
140         case IRQ_TYPE_LEVEL_HIGH:
141                 int_style = IXP23XX_GPIO_STYLE_ACTIVE_HIGH;
142                 irq_type = IXP23XX_IRQ_LEVEL;
143                 break;
144         case IRQ_TYPE_LEVEL_LOW:
145                 int_style = IXP23XX_GPIO_STYLE_ACTIVE_LOW;
146                 irq_type = IXP23XX_IRQ_LEVEL;
147                 break;
148         default:
149                 return -EINVAL;
150         }
151
152         ixp23xx_config_irq(irq, irq_type);
153
154         if (line >= 8) {        /* pins 8-15 */
155                 line -= 8;
156                 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT2R;
157         } else {                /* pins 0-7 */
158                 int_reg = (volatile u32 *)IXP23XX_GPIO_GPIT1R;
159         }
160
161         /*
162          * Clear pending interrupts
163          */
164         *IXP23XX_GPIO_GPISR = (1 << line);
165
166         /* Clear the style for the appropriate pin */
167         *int_reg &= ~(IXP23XX_GPIO_STYLE_MASK <<
168                         (line * IXP23XX_GPIO_STYLE_SIZE));
169
170         /* Set the new style */
171         *int_reg |= (int_style << (line * IXP23XX_GPIO_STYLE_SIZE));
172
173         return 0;
174 }
175
176 static void ixp23xx_irq_mask(unsigned int irq)
177 {
178         volatile unsigned long *intr_reg;
179
180         if (irq >= 56)
181                 irq += 8;
182
183         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
184         *intr_reg &= ~(1 << (irq % 32));
185 }
186
187 static void ixp23xx_irq_ack(unsigned int irq)
188 {
189         int line = irq - IRQ_IXP23XX_GPIO6 + 6;
190
191         if ((line < 6) || (line > 15))
192                 return;
193
194         *IXP23XX_GPIO_GPISR = (1 << line);
195 }
196
197 /*
198  * Level triggered interrupts on GPIO lines can only be cleared when the
199  * interrupt condition disappears.
200  */
201 static void ixp23xx_irq_level_unmask(unsigned int irq)
202 {
203         volatile unsigned long *intr_reg;
204
205         ixp23xx_irq_ack(irq);
206
207         if (irq >= 56)
208                 irq += 8;
209
210         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
211         *intr_reg |= (1 << (irq % 32));
212 }
213
214 static void ixp23xx_irq_edge_unmask(unsigned int irq)
215 {
216         volatile unsigned long *intr_reg;
217
218         if (irq >= 56)
219                 irq += 8;
220
221         intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
222         *intr_reg |= (1 << (irq % 32));
223 }
224
225 static struct irq_chip ixp23xx_irq_level_chip = {
226         .ack            = ixp23xx_irq_mask,
227         .mask           = ixp23xx_irq_mask,
228         .unmask         = ixp23xx_irq_level_unmask,
229         .set_type       = ixp23xx_irq_set_type
230 };
231
232 static struct irq_chip ixp23xx_irq_edge_chip = {
233         .ack            = ixp23xx_irq_ack,
234         .mask           = ixp23xx_irq_mask,
235         .unmask         = ixp23xx_irq_edge_unmask,
236         .set_type       = ixp23xx_irq_set_type
237 };
238
239 static void ixp23xx_pci_irq_mask(unsigned int irq)
240 {
241         *IXP23XX_PCI_XSCALE_INT_ENABLE &= ~(1 << (IRQ_IXP23XX_INTA + 27 - irq));
242 }
243
244 static void ixp23xx_pci_irq_unmask(unsigned int irq)
245 {
246         *IXP23XX_PCI_XSCALE_INT_ENABLE |= (1 << (IRQ_IXP23XX_INTA + 27 - irq));
247 }
248
249 /*
250  * TODO: Should this just be done at ASM level?
251  */
252 static void pci_handler(unsigned int irq, struct irq_desc *desc)
253 {
254         u32 pci_interrupt;
255         unsigned int irqno;
256         struct irq_desc *int_desc;
257
258         pci_interrupt = *IXP23XX_PCI_XSCALE_INT_STATUS;
259
260         desc->chip->ack(irq);
261
262         /* See which PCI_INTA, or PCI_INTB interrupted */
263         if (pci_interrupt & (1 << 26)) {
264                 irqno = IRQ_IXP23XX_INTB;
265         } else if (pci_interrupt & (1 << 27)) {
266                 irqno = IRQ_IXP23XX_INTA;
267         } else {
268                 BUG();
269         }
270
271         int_desc = irq_desc + irqno;
272         desc_handle_irq(irqno, int_desc);
273
274         desc->chip->unmask(irq);
275 }
276
277 static struct irq_chip ixp23xx_pci_irq_chip = {
278         .ack    = ixp23xx_pci_irq_mask,
279         .mask   = ixp23xx_pci_irq_mask,
280         .unmask = ixp23xx_pci_irq_unmask
281 };
282
283 static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
284 {
285         switch (type) {
286         case IXP23XX_IRQ_LEVEL:
287                 set_irq_chip(irq, &ixp23xx_irq_level_chip);
288                 set_irq_handler(irq, handle_level_irq);
289                 break;
290         case IXP23XX_IRQ_EDGE:
291                 set_irq_chip(irq, &ixp23xx_irq_edge_chip);
292                 set_irq_handler(irq, handle_edge_irq);
293                 break;
294         }
295         set_irq_flags(irq, IRQF_VALID);
296 }
297
298 void __init ixp23xx_init_irq(void)
299 {
300         int irq;
301
302         /* Route everything to IRQ */
303         *IXP23XX_INTR_SEL1 = 0x0;
304         *IXP23XX_INTR_SEL2 = 0x0;
305         *IXP23XX_INTR_SEL3 = 0x0;
306         *IXP23XX_INTR_SEL4 = 0x0;
307
308         /* Mask all sources */
309         *IXP23XX_INTR_EN1 = 0x0;
310         *IXP23XX_INTR_EN2 = 0x0;
311         *IXP23XX_INTR_EN3 = 0x0;
312         *IXP23XX_INTR_EN4 = 0x0;
313
314         /*
315          * Configure all IRQs for level-sensitive operation
316          */
317         for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) {
318                 ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL);
319         }
320
321         for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
322                 set_irq_chip(irq, &ixp23xx_pci_irq_chip);
323                 set_irq_handler(irq, handle_level_irq);
324                 set_irq_flags(irq, IRQF_VALID);
325         }
326
327         set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
328 }
329
330
331 /*************************************************************************
332  * Timer-tick functions for IXP23xx
333  *************************************************************************/
334 #define CLOCK_TICKS_PER_USEC    (CLOCK_TICK_RATE / USEC_PER_SEC)
335
336 static unsigned long next_jiffy_time;
337
338 static unsigned long
339 ixp23xx_gettimeoffset(void)
340 {
341         unsigned long elapsed;
342
343         elapsed = *IXP23XX_TIMER_CONT - (next_jiffy_time - LATCH);
344
345         return elapsed / CLOCK_TICKS_PER_USEC;
346 }
347
348 static irqreturn_t
349 ixp23xx_timer_interrupt(int irq, void *dev_id)
350 {
351         /* Clear Pending Interrupt by writing '1' to it */
352         *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
353         while ((signed long)(*IXP23XX_TIMER_CONT - next_jiffy_time) >= LATCH) {
354                 timer_tick();
355                 next_jiffy_time += LATCH;
356         }
357
358         return IRQ_HANDLED;
359 }
360
361 static struct irqaction ixp23xx_timer_irq = {
362         .name           = "IXP23xx Timer Tick",
363         .handler        = ixp23xx_timer_interrupt,
364         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
365 };
366
367 void __init ixp23xx_init_timer(void)
368 {
369         /* Clear Pending Interrupt by writing '1' to it */
370         *IXP23XX_TIMER_STATUS = IXP23XX_TIMER1_INT_PEND;
371
372         /* Setup the Timer counter value */
373         *IXP23XX_TIMER1_RELOAD =
374                 (LATCH & ~IXP23XX_TIMER_RELOAD_MASK) | IXP23XX_TIMER_ENABLE;
375
376         *IXP23XX_TIMER_CONT = 0;
377         next_jiffy_time = LATCH;
378
379         /* Connect the interrupt handler and enable the interrupt */
380         setup_irq(IRQ_IXP23XX_TIMER1, &ixp23xx_timer_irq);
381 }
382
383 struct sys_timer ixp23xx_timer = {
384         .init           = ixp23xx_init_timer,
385         .offset         = ixp23xx_gettimeoffset,
386 };
387
388
389 /*************************************************************************
390  * IXP23xx Platform Initialization
391  *************************************************************************/
392 static struct resource ixp23xx_uart_resources[] = {
393         {
394                 .start          = IXP23XX_UART1_PHYS,
395                 .end            = IXP23XX_UART1_PHYS + 0x0fff,
396                 .flags          = IORESOURCE_MEM
397         }, {
398                 .start          = IXP23XX_UART2_PHYS,
399                 .end            = IXP23XX_UART2_PHYS + 0x0fff,
400                 .flags          = IORESOURCE_MEM
401         }
402 };
403
404 static struct plat_serial8250_port ixp23xx_uart_data[] = {
405         {
406                 .mapbase        = IXP23XX_UART1_PHYS,
407                 .membase        = (char *)(IXP23XX_UART1_VIRT + 3),
408                 .irq            = IRQ_IXP23XX_UART1,
409                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
410                 .iotype         = UPIO_MEM,
411                 .regshift       = 2,
412                 .uartclk        = IXP23XX_UART_XTAL,
413         }, {
414                 .mapbase        = IXP23XX_UART2_PHYS,
415                 .membase        = (char *)(IXP23XX_UART2_VIRT + 3),
416                 .irq            = IRQ_IXP23XX_UART2,
417                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
418                 .iotype         = UPIO_MEM,
419                 .regshift       = 2,
420                 .uartclk        = IXP23XX_UART_XTAL,
421         },
422         { },
423 };
424
425 static struct platform_device ixp23xx_uart = {
426         .name                   = "serial8250",
427         .id                     = 0,
428         .dev.platform_data      = ixp23xx_uart_data,
429         .num_resources          = 2,
430         .resource               = ixp23xx_uart_resources,
431 };
432
433 static struct platform_device *ixp23xx_devices[] __initdata = {
434         &ixp23xx_uart,
435 };
436
437 void __init ixp23xx_sys_init(void)
438 {
439         *IXP23XX_EXP_UNIT_FUSE |= 0xf;
440         platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
441 }