4b9d841e04c15395a50488c52b1f1ca86daa9bd7
[linux-2.6.git] / arch / arm / mach-ixp2000 / core.c
1 /*
2  * arch/arm/mach-ixp2000/common.c
3  *
4  * Common routines used by all IXP2400/2800 based platforms.
5  *
6  * Author: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2004 (C) MontaVista Software, Inc. 
9  *
10  * Based on work Copyright (C) 2002-2003 Intel Corporation
11  * 
12  * This file is licensed under the terms of the GNU General Public
13  * License version 2. This program is licensed "as is" without any 
14  * warranty of any kind, whether express or implied.
15  */
16
17 #include <linux/config.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/sched.h>
22 #include <linux/interrupt.h>
23 #include <linux/serial.h>
24 #include <linux/tty.h>
25 #include <linux/bitops.h>
26 #include <linux/serial_core.h>
27 #include <linux/mm.h>
28
29 #include <asm/types.h>
30 #include <asm/setup.h>
31 #include <asm/memory.h>
32 #include <asm/hardware.h>
33 #include <asm/mach-types.h>
34 #include <asm/irq.h>
35 #include <asm/system.h>
36 #include <asm/tlbflush.h>
37 #include <asm/pgtable.h>
38
39 #include <asm/mach/map.h>
40 #include <asm/mach/time.h>
41 #include <asm/mach/irq.h>
42
43 #include <asm/arch/gpio.h>
44
45 static DEFINE_SPINLOCK(ixp2000_slowport_lock);
46 static unsigned long ixp2000_slowport_irq_flags;
47
48 /*************************************************************************
49  * Slowport access routines
50  *************************************************************************/
51 void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg)
52 {
53
54         spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags);
55
56         old_cfg->CCR = *IXP2000_SLOWPORT_CCR;
57         old_cfg->WTC = *IXP2000_SLOWPORT_WTC2;
58         old_cfg->RTC = *IXP2000_SLOWPORT_RTC2;
59         old_cfg->PCR = *IXP2000_SLOWPORT_PCR;
60         old_cfg->ADC = *IXP2000_SLOWPORT_ADC;
61
62         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR);
63         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC);
64         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC);
65         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR);
66         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, new_cfg->ADC);
67 }
68
69 void ixp2000_release_slowport(struct slowport_cfg *old_cfg)
70 {
71         ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR);
72         ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC);
73         ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC);
74         ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR);
75         ixp2000_reg_write(IXP2000_SLOWPORT_ADC, old_cfg->ADC);
76
77         spin_unlock_irqrestore(&ixp2000_slowport_lock, 
78                                         ixp2000_slowport_irq_flags);
79 }
80
81 /*************************************************************************
82  * Chip specific mappings shared by all IXP2000 systems
83  *************************************************************************/
84 static struct map_desc ixp2000_io_desc[] __initdata = {
85         {
86                 .virtual        = IXP2000_CAP_VIRT_BASE,
87                 .physical       = IXP2000_CAP_PHYS_BASE,
88                 .length         = IXP2000_CAP_SIZE,
89                 .type           = MT_DEVICE
90         }, {
91                 .virtual        = IXP2000_INTCTL_VIRT_BASE,
92                 .physical       = IXP2000_INTCTL_PHYS_BASE,
93                 .length         = IXP2000_INTCTL_SIZE,
94                 .type           = MT_DEVICE
95         }, {
96                 .virtual        = IXP2000_PCI_CREG_VIRT_BASE,
97                 .physical       = IXP2000_PCI_CREG_PHYS_BASE,
98                 .length         = IXP2000_PCI_CREG_SIZE,
99                 .type           = MT_DEVICE
100         }, {
101                 .virtual        = IXP2000_PCI_CSR_VIRT_BASE,
102                 .physical       = IXP2000_PCI_CSR_PHYS_BASE,
103                 .length         = IXP2000_PCI_CSR_SIZE,
104                 .type           = MT_DEVICE
105         }, {
106                 .virtual        = IXP2000_MSF_VIRT_BASE,
107                 .physical       = IXP2000_MSF_PHYS_BASE,
108                 .length         = IXP2000_MSF_SIZE,
109                 .type           = MT_DEVICE
110         }, {
111                 .virtual        = IXP2000_PCI_IO_VIRT_BASE,
112                 .physical       = IXP2000_PCI_IO_PHYS_BASE,
113                 .length         = IXP2000_PCI_IO_SIZE,
114                 .type           = MT_DEVICE
115         }, {
116                 .virtual        = IXP2000_PCI_CFG0_VIRT_BASE,
117                 .physical       = IXP2000_PCI_CFG0_PHYS_BASE,
118                 .length         = IXP2000_PCI_CFG0_SIZE,
119                 .type           = MT_DEVICE
120         }, {
121                 .virtual        = IXP2000_PCI_CFG1_VIRT_BASE,
122                 .physical       = IXP2000_PCI_CFG1_PHYS_BASE,
123                 .length         = IXP2000_PCI_CFG1_SIZE,
124                 .type           = MT_DEVICE
125         }
126 };
127
128 static struct uart_port ixp2000_serial_port = {
129         .membase        = (char *)(IXP2000_UART_VIRT_BASE + 3),
130         .mapbase        = IXP2000_UART_PHYS_BASE + 3,
131         .irq            = IRQ_IXP2000_UART,
132         .flags          = UPF_SKIP_TEST,
133         .iotype         = UPIO_MEM,
134         .regshift       = 2,
135         .uartclk        = 50000000,
136         .line           = 0,
137         .type           = PORT_XSCALE,
138         .fifosize       = 16
139 };
140
141 void __init ixp2000_map_io(void)
142 {
143         extern unsigned int processor_id;
144
145         /*
146          * On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
147          * tweaking the PMDs so XCB=101. On IXP2800s we use the normal
148          * PMD flags.
149          */
150         if ((processor_id & 0xfffffff0) == 0x69054190) {
151                 int i;
152
153                 printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
154
155                 for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
156                         ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
157         }
158
159         iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
160         early_serial_setup(&ixp2000_serial_port);
161
162         /* Set slowport to 8-bit mode.  */
163         ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
164 }
165
166 /*************************************************************************
167  * Timer-tick functions for IXP2000
168  *************************************************************************/
169 static unsigned ticks_per_jiffy;
170 static unsigned ticks_per_usec;
171 static unsigned next_jiffy_time;
172 static volatile unsigned long *missing_jiffy_timer_csr;
173
174 unsigned long ixp2000_gettimeoffset (void)
175 {
176         unsigned long offset;
177
178         offset = next_jiffy_time - *missing_jiffy_timer_csr;
179
180         return offset / ticks_per_usec;
181 }
182
183 static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
184 {
185         write_seqlock(&xtime_lock);
186
187         /* clear timer 1 */
188         ixp2000_reg_write(IXP2000_T1_CLR, 1);
189
190         while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
191                 timer_tick(regs);
192                 next_jiffy_time -= ticks_per_jiffy;
193         }
194
195         write_sequnlock(&xtime_lock);
196
197         return IRQ_HANDLED;
198 }
199
200 static struct irqaction ixp2000_timer_irq = {
201         .name           = "IXP2000 Timer Tick",
202         .flags          = SA_INTERRUPT | SA_TIMER,
203         .handler        = ixp2000_timer_interrupt,
204 };
205
206 void __init ixp2000_init_time(unsigned long tick_rate)
207 {
208         ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
209         ticks_per_usec = tick_rate / 1000000;
210
211         /*
212          * We use timer 1 as our timer interrupt.
213          */
214         ixp2000_reg_write(IXP2000_T1_CLR, 0);
215         ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
216         ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
217
218         /*
219          * We use a second timer as a monotonic counter for tracking
220          * missed jiffies.  The IXP2000 has four timers, but if we're
221          * on an A-step IXP2800, timer 2 and 3 don't work, so on those
222          * chips we use timer 4.  Timer 4 is the only timer that can
223          * be used for the watchdog, so we use timer 2 if we're on a
224          * non-buggy chip.
225          */
226         if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
227                 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
228
229                 ixp2000_reg_write(IXP2000_T4_CLR, 0);
230                 ixp2000_reg_write(IXP2000_T4_CLD, -1);
231                 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
232                 missing_jiffy_timer_csr = IXP2000_T4_CSR;
233         } else {
234                 ixp2000_reg_write(IXP2000_T2_CLR, 0);
235                 ixp2000_reg_write(IXP2000_T2_CLD, -1);
236                 ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
237                 missing_jiffy_timer_csr = IXP2000_T2_CSR;
238         }
239         next_jiffy_time = 0xffffffff;
240
241         /* register for interrupt */
242         setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq);
243 }
244
245 /*************************************************************************
246  * GPIO helpers
247  *************************************************************************/
248 static unsigned long GPIO_IRQ_falling_edge;
249 static unsigned long GPIO_IRQ_rising_edge;
250 static unsigned long GPIO_IRQ_level_low;
251 static unsigned long GPIO_IRQ_level_high;
252
253 static void update_gpio_int_csrs(void)
254 {
255         ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge);
256         ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge);
257         ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low);
258         ixp2000_reg_write(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high);
259 }
260
261 void gpio_line_config(int line, int direction)
262 {
263         unsigned long flags;
264
265         local_irq_save(flags);
266         if (direction == GPIO_OUT) {
267                 irq_desc[line + IRQ_IXP2000_GPIO0].valid = 0;
268
269                 /* if it's an output, it ain't an interrupt anymore */
270                 GPIO_IRQ_falling_edge &= ~(1 << line);
271                 GPIO_IRQ_rising_edge &= ~(1 << line);
272                 GPIO_IRQ_level_low &= ~(1 << line);
273                 GPIO_IRQ_level_high &= ~(1 << line);
274                 update_gpio_int_csrs();
275
276                 ixp2000_reg_write(IXP2000_GPIO_PDSR, 1 << line);
277         } else if (direction == GPIO_IN) {
278                 ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
279         }
280         local_irq_restore(flags);
281 }
282
283
284 /*************************************************************************
285  * IRQ handling IXP2000
286  *************************************************************************/
287 static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
288 {                               
289         int i;
290         unsigned long status = *IXP2000_GPIO_INST;
291                    
292         for (i = 0; i <= 7; i++) {
293                 if (status & (1<<i)) {
294                         desc = irq_desc + i + IRQ_IXP2000_GPIO0;
295                         desc->handle(i + IRQ_IXP2000_GPIO0, desc, regs);
296                 }
297         }
298 }
299
300 static int ixp2000_GPIO_irq_type(unsigned int irq, unsigned int type)
301 {
302         int line = irq - IRQ_IXP2000_GPIO0;
303
304         /*
305          * First, configure this GPIO line as an input.
306          */
307         ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line);
308
309         /*
310          * Then, set the proper trigger type.
311          */
312         if (type & IRQT_FALLING)
313                 GPIO_IRQ_falling_edge |= 1 << line;
314         else
315                 GPIO_IRQ_falling_edge &= ~(1 << line);
316         if (type & IRQT_RISING)
317                 GPIO_IRQ_rising_edge |= 1 << line;
318         else
319                 GPIO_IRQ_rising_edge &= ~(1 << line);
320         if (type & IRQT_LOW)
321                 GPIO_IRQ_level_low |= 1 << line;
322         else
323                 GPIO_IRQ_level_low &= ~(1 << line);
324         if (type & IRQT_HIGH)
325                 GPIO_IRQ_level_high |= 1 << line;
326         else
327                 GPIO_IRQ_level_high &= ~(1 << line);
328         update_gpio_int_csrs();
329
330         /*
331          * Finally, mark the corresponding IRQ as valid.
332          */
333         irq_desc[irq].valid = 1;
334
335         return 0;
336 }
337
338 static void ixp2000_GPIO_irq_mask_ack(unsigned int irq)
339 {
340         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
341
342         ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
343         ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
344         ixp2000_reg_write(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0)));
345 }
346
347 static void ixp2000_GPIO_irq_mask(unsigned int irq)
348 {
349         ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0)));
350 }
351
352 static void ixp2000_GPIO_irq_unmask(unsigned int irq)
353 {
354         ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0)));
355 }
356
357 static struct irqchip ixp2000_GPIO_irq_chip = {
358         .type   = ixp2000_GPIO_irq_type,
359         .ack    = ixp2000_GPIO_irq_mask_ack,
360         .mask   = ixp2000_GPIO_irq_mask,
361         .unmask = ixp2000_GPIO_irq_unmask
362 };
363
364 static void ixp2000_pci_irq_mask(unsigned int irq)
365 {
366         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
367         if (irq == IRQ_IXP2000_PCIA)
368                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26)));
369         else if (irq == IRQ_IXP2000_PCIB)
370                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27)));
371 }
372
373 static void ixp2000_pci_irq_unmask(unsigned int irq)
374 {
375         unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE;
376         if (irq == IRQ_IXP2000_PCIA)
377                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26)));
378         else if (irq == IRQ_IXP2000_PCIB)
379                 ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27)));
380 }
381
382 static struct irqchip ixp2000_pci_irq_chip = {
383         .ack    = ixp2000_pci_irq_mask,
384         .mask   = ixp2000_pci_irq_mask,
385         .unmask = ixp2000_pci_irq_unmask
386 };
387
388 static void ixp2000_irq_mask(unsigned int irq)
389 {
390         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, (1 << irq));
391 }
392
393 static void ixp2000_irq_unmask(unsigned int irq)
394 {
395         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << irq));
396 }
397
398 static struct irqchip ixp2000_irq_chip = {
399         .ack    = ixp2000_irq_mask,
400         .mask   = ixp2000_irq_mask,
401         .unmask = ixp2000_irq_unmask
402 };
403
404 void __init ixp2000_init_irq(void)
405 {
406         int irq;
407
408         /*
409          * Mask all sources
410          */
411         ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff);
412         ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff);
413
414         /* clear all GPIO edge/level detects */
415         ixp2000_reg_write(IXP2000_GPIO_REDR, 0);
416         ixp2000_reg_write(IXP2000_GPIO_FEDR, 0);
417         ixp2000_reg_write(IXP2000_GPIO_LSHR, 0);
418         ixp2000_reg_write(IXP2000_GPIO_LSLR, 0);
419         ixp2000_reg_write(IXP2000_GPIO_INCR, -1);
420
421         /* clear PCI interrupt sources */
422         ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, 0);
423
424         /*
425          * Certain bits in the IRQ status register of the 
426          * IXP2000 are reserved. Instead of trying to map
427          * things non 1:1 from bit position to IRQ number,
428          * we mark the reserved IRQs as invalid. This makes
429          * our mask/unmask code much simpler.
430          */
431         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
432                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
433                         set_irq_chip(irq, &ixp2000_irq_chip);
434                         set_irq_handler(irq, do_level_IRQ);
435                         set_irq_flags(irq, IRQF_VALID);
436                 } else set_irq_flags(irq, 0);
437         }
438
439         /*
440          * GPIO IRQs are invalid until someone sets the interrupt mode
441          * by calling set_irq_type().
442          */
443         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
444                 set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
445                 set_irq_handler(irq, do_level_IRQ);
446                 set_irq_flags(irq, 0);
447         }
448         set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
449
450         /*
451          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
452          * entry-macro.S, so we don't need a chained handler for the
453          * PCI interrupt source.
454          */
455         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
456         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
457                 set_irq_chip(irq, &ixp2000_pci_irq_chip);
458                 set_irq_handler(irq, do_level_IRQ);
459                 set_irq_flags(irq, IRQF_VALID);
460         }
461 }
462