ARM: Integrator: convert to generic clockevent support
[linux-2.6.git] / arch / arm / mach-integrator / integrator_ap.c
1 /*
2  *  linux/arch/arm/mach-integrator/integrator_ap.c
3  *
4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19  */
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/sysdev.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/io.h>
31
32 #include <mach/hardware.h>
33 #include <mach/platform.h>
34 #include <asm/irq.h>
35 #include <asm/setup.h>
36 #include <asm/param.h>          /* HZ */
37 #include <asm/mach-types.h>
38
39 #include <mach/lm.h>
40
41 #include <asm/mach/arch.h>
42 #include <asm/mach/flash.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/map.h>
45 #include <asm/mach/time.h>
46
47 #include "common.h"
48
49 /* 
50  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
51  * is the (PA >> 12).
52  *
53  * Setup a VA for the Integrator interrupt controller (for header #0,
54  * just for now).
55  */
56 #define VA_IC_BASE      IO_ADDRESS(INTEGRATOR_IC_BASE) 
57 #define VA_SC_BASE      IO_ADDRESS(INTEGRATOR_SC_BASE)
58 #define VA_EBI_BASE     IO_ADDRESS(INTEGRATOR_EBI_BASE)
59 #define VA_CMIC_BASE    IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_IC_OFFSET
60
61 /*
62  * Logical      Physical
63  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
64  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
65  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
66  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
67  * ef000000                     Cache flush
68  * f1000000     10000000        Core module registers
69  * f1100000     11000000        System controller registers
70  * f1200000     12000000        EBI registers
71  * f1300000     13000000        Counter/Timer
72  * f1400000     14000000        Interrupt controller
73  * f1600000     16000000        UART 0
74  * f1700000     17000000        UART 1
75  * f1a00000     1a000000        Debug LEDs
76  * f1b00000     1b000000        GPIO
77  */
78
79 static struct map_desc ap_io_desc[] __initdata = {
80         {
81                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
82                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
83                 .length         = SZ_4K,
84                 .type           = MT_DEVICE
85         }, {
86                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
87                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
88                 .length         = SZ_4K,
89                 .type           = MT_DEVICE
90         }, {
91                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
92                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
93                 .length         = SZ_4K,
94                 .type           = MT_DEVICE
95         }, {
96                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
97                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
98                 .length         = SZ_4K,
99                 .type           = MT_DEVICE
100         }, {
101                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
102                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
103                 .length         = SZ_4K,
104                 .type           = MT_DEVICE
105         }, {
106                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
107                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
108                 .length         = SZ_4K,
109                 .type           = MT_DEVICE
110         }, {
111                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
112                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
113                 .length         = SZ_4K,
114                 .type           = MT_DEVICE
115         }, {
116                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
117                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
118                 .length         = SZ_4K,
119                 .type           = MT_DEVICE
120         }, {
121                 .virtual        = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
122                 .pfn            = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
123                 .length         = SZ_4K,
124                 .type           = MT_DEVICE
125         }, {
126                 .virtual        = PCI_MEMORY_VADDR,
127                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
128                 .length         = SZ_16M,
129                 .type           = MT_DEVICE
130         }, {
131                 .virtual        = PCI_CONFIG_VADDR,
132                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
133                 .length         = SZ_16M,
134                 .type           = MT_DEVICE
135         }, {
136                 .virtual        = PCI_V3_VADDR,
137                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
138                 .length         = SZ_64K,
139                 .type           = MT_DEVICE
140         }, {
141                 .virtual        = PCI_IO_VADDR,
142                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
143                 .length         = SZ_64K,
144                 .type           = MT_DEVICE
145         }
146 };
147
148 static void __init ap_map_io(void)
149 {
150         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
151 }
152
153 #define INTEGRATOR_SC_VALID_INT 0x003fffff
154
155 static void sc_mask_irq(unsigned int irq)
156 {
157         writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
158 }
159
160 static void sc_unmask_irq(unsigned int irq)
161 {
162         writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
163 }
164
165 static struct irq_chip sc_chip = {
166         .name   = "SC",
167         .ack    = sc_mask_irq,
168         .mask   = sc_mask_irq,
169         .unmask = sc_unmask_irq,
170 };
171
172 static void __init ap_init_irq(void)
173 {
174         unsigned int i;
175
176         /* Disable all interrupts initially. */
177         /* Do the core module ones */
178         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
179
180         /* do the header card stuff next */
181         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
182         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
183
184         for (i = 0; i < NR_IRQS; i++) {
185                 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
186                         set_irq_chip(i, &sc_chip);
187                         set_irq_handler(i, handle_level_irq);
188                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
189                 }
190         }
191 }
192
193 #ifdef CONFIG_PM
194 static unsigned long ic_irq_enable;
195
196 static int irq_suspend(struct sys_device *dev, pm_message_t state)
197 {
198         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
199         return 0;
200 }
201
202 static int irq_resume(struct sys_device *dev)
203 {
204         /* disable all irq sources */
205         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
206         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
207         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
208
209         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
210         return 0;
211 }
212 #else
213 #define irq_suspend NULL
214 #define irq_resume NULL
215 #endif
216
217 static struct sysdev_class irq_class = {
218         .name           = "irq",
219         .suspend        = irq_suspend,
220         .resume         = irq_resume,
221 };
222
223 static struct sys_device irq_device = {
224         .id     = 0,
225         .cls    = &irq_class,
226 };
227
228 static int __init irq_init_sysfs(void)
229 {
230         int ret = sysdev_class_register(&irq_class);
231         if (ret == 0)
232                 ret = sysdev_register(&irq_device);
233         return ret;
234 }
235
236 device_initcall(irq_init_sysfs);
237
238 /*
239  * Flash handling.
240  */
241 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
242 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
243 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
244 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
245
246 static int ap_flash_init(void)
247 {
248         u32 tmp;
249
250         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
251
252         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
253         writel(tmp, EBI_CSR1);
254
255         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
256                 writel(0xa05f, EBI_LOCK);
257                 writel(tmp, EBI_CSR1);
258                 writel(0, EBI_LOCK);
259         }
260         return 0;
261 }
262
263 static void ap_flash_exit(void)
264 {
265         u32 tmp;
266
267         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
268
269         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
270         writel(tmp, EBI_CSR1);
271
272         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
273                 writel(0xa05f, EBI_LOCK);
274                 writel(tmp, EBI_CSR1);
275                 writel(0, EBI_LOCK);
276         }
277 }
278
279 static void ap_flash_set_vpp(int on)
280 {
281         unsigned long reg = on ? SC_CTRLS : SC_CTRLC;
282
283         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
284 }
285
286 static struct flash_platform_data ap_flash_data = {
287         .map_name       = "cfi_probe",
288         .width          = 4,
289         .init           = ap_flash_init,
290         .exit           = ap_flash_exit,
291         .set_vpp        = ap_flash_set_vpp,
292 };
293
294 static struct resource cfi_flash_resource = {
295         .start          = INTEGRATOR_FLASH_BASE,
296         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
297         .flags          = IORESOURCE_MEM,
298 };
299
300 static struct platform_device cfi_flash_device = {
301         .name           = "armflash",
302         .id             = 0,
303         .dev            = {
304                 .platform_data  = &ap_flash_data,
305         },
306         .num_resources  = 1,
307         .resource       = &cfi_flash_resource,
308 };
309
310 static void __init ap_init(void)
311 {
312         unsigned long sc_dec;
313         int i;
314
315         platform_device_register(&cfi_flash_device);
316
317         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
318         for (i = 0; i < 4; i++) {
319                 struct lm_device *lmdev;
320
321                 if ((sc_dec & (16 << i)) == 0)
322                         continue;
323
324                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
325                 if (!lmdev)
326                         continue;
327
328                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
329                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
330                 lmdev->resource.flags = IORESOURCE_MEM;
331                 lmdev->irq = IRQ_AP_EXPINT0 + i;
332                 lmdev->id = i;
333
334                 lm_device_register(lmdev);
335         }
336 }
337
338 static void __init ap_init_timer(void)
339 {
340         integrator_time_init(1000000 * TICKS_PER_uSEC / HZ, 0);
341 }
342
343 static struct sys_timer ap_timer = {
344         .init           = ap_init_timer,
345 };
346
347 MACHINE_START(INTEGRATOR, "ARM-Integrator")
348         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
349         .phys_io        = 0x16000000,
350         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
351         .boot_params    = 0x00000100,
352         .map_io         = ap_map_io,
353         .init_irq       = ap_init_irq,
354         .timer          = &ap_timer,
355         .init_machine   = ap_init,
356 MACHINE_END