Merge git://bedivere.hansenpartnership.com/git/scsi-rc-fixes-2.6
[linux-2.6.git] / arch / arm / mach-exynos4 / cpu.c
1 /* linux/arch/arm/mach-exynos4/cpu.c
2  *
3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4  *              http://www.samsung.com
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9 */
10
11 #include <linux/sched.h>
12 #include <linux/sysdev.h>
13
14 #include <asm/mach/map.h>
15 #include <asm/mach/irq.h>
16
17 #include <asm/proc-fns.h>
18 #include <asm/hardware/cache-l2x0.h>
19 #include <asm/hardware/gic.h>
20
21 #include <plat/cpu.h>
22 #include <plat/clock.h>
23 #include <plat/devs.h>
24 #include <plat/exynos4.h>
25 #include <plat/adc-core.h>
26 #include <plat/sdhci.h>
27 #include <plat/fb-core.h>
28 #include <plat/fimc-core.h>
29 #include <plat/iic-core.h>
30 #include <plat/reset.h>
31
32 #include <mach/regs-irq.h>
33 #include <mach/regs-pmu.h>
34
35 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
36                          unsigned int irq_start);
37 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
38
39 /* Initial IO mappings */
40 static struct map_desc exynos4_iodesc[] __initdata = {
41         {
42                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
43                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
44                 .length         = SZ_4K,
45                 .type           = MT_DEVICE,
46         }, {
47                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
48                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
49                 .length         = SZ_4K,
50                 .type           = MT_DEVICE,
51         }, {
52                 .virtual        = (unsigned long)S5P_VA_CMU,
53                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
54                 .length         = SZ_128K,
55                 .type           = MT_DEVICE,
56         }, {
57                 .virtual        = (unsigned long)S5P_VA_PMU,
58                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
59                 .length         = SZ_64K,
60                 .type           = MT_DEVICE,
61         }, {
62                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
63                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
64                 .length         = SZ_4K,
65                 .type           = MT_DEVICE,
66         }, {
67                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
68                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
69                 .length         = SZ_8K,
70                 .type           = MT_DEVICE,
71         }, {
72                 .virtual        = (unsigned long)S5P_VA_L2CC,
73                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
74                 .length         = SZ_4K,
75                 .type           = MT_DEVICE,
76         }, {
77                 .virtual        = (unsigned long)S5P_VA_GPIO1,
78                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
79                 .length         = SZ_4K,
80                 .type           = MT_DEVICE,
81         }, {
82                 .virtual        = (unsigned long)S5P_VA_GPIO2,
83                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
84                 .length         = SZ_4K,
85                 .type           = MT_DEVICE,
86         }, {
87                 .virtual        = (unsigned long)S5P_VA_GPIO3,
88                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
89                 .length         = SZ_256,
90                 .type           = MT_DEVICE,
91         }, {
92                 .virtual        = (unsigned long)S5P_VA_DMC0,
93                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
94                 .length         = SZ_4K,
95                 .type           = MT_DEVICE,
96         }, {
97                 .virtual        = (unsigned long)S3C_VA_UART,
98                 .pfn            = __phys_to_pfn(S3C_PA_UART),
99                 .length         = SZ_512K,
100                 .type           = MT_DEVICE,
101         }, {
102                 .virtual        = (unsigned long)S5P_VA_SROMC,
103                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
104                 .length         = SZ_4K,
105                 .type           = MT_DEVICE,
106         }, {
107                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
108                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
109                 .length         = SZ_4K,
110                 .type           = MT_DEVICE,
111         }, {
112                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
113                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
114                 .length         = SZ_64K,
115                 .type           = MT_DEVICE,
116         }, {
117                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
118                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
119                 .length         = SZ_64K,
120                 .type           = MT_DEVICE,
121         },
122 };
123
124 static void exynos4_idle(void)
125 {
126         if (!need_resched())
127                 cpu_do_idle();
128
129         local_irq_enable();
130 }
131
132 static void exynos4_sw_reset(void)
133 {
134         __raw_writel(0x1, S5P_SWRESET);
135 }
136
137 /*
138  * exynos4_map_io
139  *
140  * register the standard cpu IO areas
141  */
142 void __init exynos4_map_io(void)
143 {
144         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
145
146         /* initialize device information early */
147         exynos4_default_sdhci0();
148         exynos4_default_sdhci1();
149         exynos4_default_sdhci2();
150         exynos4_default_sdhci3();
151
152         s3c_adc_setname("samsung-adc-v3");
153
154         s3c_fimc_setname(0, "exynos4-fimc");
155         s3c_fimc_setname(1, "exynos4-fimc");
156         s3c_fimc_setname(2, "exynos4-fimc");
157         s3c_fimc_setname(3, "exynos4-fimc");
158
159         /* The I2C bus controllers are directly compatible with s3c2440 */
160         s3c_i2c0_setname("s3c2440-i2c");
161         s3c_i2c1_setname("s3c2440-i2c");
162         s3c_i2c2_setname("s3c2440-i2c");
163
164         s5p_fb_setname(0, "exynos4-fb");
165 }
166
167 void __init exynos4_init_clocks(int xtal)
168 {
169         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
170
171         s3c24xx_register_baseclocks(xtal);
172         s5p_register_clocks(xtal);
173         exynos4_register_clocks();
174         exynos4_setup_clocks();
175 }
176
177 static void exynos4_gic_irq_eoi(struct irq_data *d)
178 {
179         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
180
181         gic_data->cpu_base = S5P_VA_GIC_CPU +
182                             (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
183 }
184
185 void __init exynos4_init_irq(void)
186 {
187         int irq;
188
189         gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
190         gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
191
192         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
193
194                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
195                                 COMBINER_IRQ(irq, 0));
196                 combiner_cascade_irq(irq, IRQ_SPI(irq));
197         }
198
199         /* The parameters of s5p_init_irq() are for VIC init.
200          * Theses parameters should be NULL and 0 because EXYNOS4
201          * uses GIC instead of VIC.
202          */
203         s5p_init_irq(NULL, 0);
204 }
205
206 struct sysdev_class exynos4_sysclass = {
207         .name   = "exynos4-core",
208 };
209
210 static struct sys_device exynos4_sysdev = {
211         .cls    = &exynos4_sysclass,
212 };
213
214 static int __init exynos4_core_init(void)
215 {
216         return sysdev_class_register(&exynos4_sysclass);
217 }
218
219 core_initcall(exynos4_core_init);
220
221 #ifdef CONFIG_CACHE_L2X0
222 static int __init exynos4_l2x0_cache_init(void)
223 {
224         /* TAG, Data Latency Control: 2cycle */
225         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
226         __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
227
228         /* L2X0 Prefetch Control */
229         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
230
231         /* L2X0 Power Control */
232         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
233                      S5P_VA_L2CC + L2X0_POWER_CTRL);
234
235         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
236
237         return 0;
238 }
239
240 early_initcall(exynos4_l2x0_cache_init);
241 #endif
242
243 int __init exynos4_init(void)
244 {
245         printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
246
247         /* set idle function */
248         pm_idle = exynos4_idle;
249
250         /* set sw_reset function */
251         s5p_reset_hook = exynos4_sw_reset;
252
253         return sysdev_register(&exynos4_sysdev);
254 }