Merge branch 'fixes-hwmod-regression' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / arm / mach-exynos / cpu.c
1 /* linux/arch/arm/mach-exynos/cpu.c
2  *
3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4  *              http://www.samsung.com
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9 */
10
11 #include <linux/sched.h>
12 #include <linux/sysdev.h>
13
14 #include <asm/mach/map.h>
15 #include <asm/mach/irq.h>
16
17 #include <asm/proc-fns.h>
18 #include <asm/hardware/cache-l2x0.h>
19 #include <asm/hardware/gic.h>
20
21 #include <plat/cpu.h>
22 #include <plat/clock.h>
23 #include <plat/devs.h>
24 #include <plat/exynos4.h>
25 #include <plat/adc-core.h>
26 #include <plat/sdhci.h>
27 #include <plat/fb-core.h>
28 #include <plat/fimc-core.h>
29 #include <plat/iic-core.h>
30 #include <plat/reset.h>
31 #include <plat/tv-core.h>
32
33 #include <mach/regs-irq.h>
34 #include <mach/regs-pmu.h>
35
36 unsigned int gic_bank_offset __read_mostly;
37
38 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
39                          unsigned int irq_start);
40 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
41
42 /* Initial IO mappings */
43 static struct map_desc exynos_iodesc[] __initdata = {
44         {
45                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
46                 .pfn            = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
47                 .length         = SZ_4K,
48                 .type           = MT_DEVICE,
49         }, {
50                 .virtual        = (unsigned long)S5P_VA_PMU,
51                 .pfn            = __phys_to_pfn(EXYNOS_PA_PMU),
52                 .length         = SZ_64K,
53                 .type           = MT_DEVICE,
54         }, {
55                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
56                 .pfn            = __phys_to_pfn(EXYNOS_PA_COMBINER),
57                 .length         = SZ_4K,
58                 .type           = MT_DEVICE,
59         }, {
60                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
61                 .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
62                 .length         = SZ_64K,
63                 .type           = MT_DEVICE,
64         }, {
65                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
66                 .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
67                 .length         = SZ_64K,
68                 .type           = MT_DEVICE,
69         }, {
70                 .virtual        = (unsigned long)S3C_VA_UART,
71                 .pfn            = __phys_to_pfn(S3C_PA_UART),
72                 .length         = SZ_512K,
73                 .type           = MT_DEVICE,
74         },
75 };
76
77 static struct map_desc exynos4_iodesc[] __initdata = {
78         {
79                 .virtual        = (unsigned long)S5P_VA_CMU,
80                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
81                 .length         = SZ_128K,
82                 .type           = MT_DEVICE,
83         }, {
84                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
85                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
86                 .length         = SZ_8K,
87                 .type           = MT_DEVICE,
88         }, {
89                 .virtual        = (unsigned long)S5P_VA_L2CC,
90                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
91                 .length         = SZ_4K,
92                 .type           = MT_DEVICE,
93         }, {
94                 .virtual        = (unsigned long)S5P_VA_GPIO1,
95                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
96                 .length         = SZ_4K,
97                 .type           = MT_DEVICE,
98         }, {
99                 .virtual        = (unsigned long)S5P_VA_GPIO2,
100                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
101                 .length         = SZ_4K,
102                 .type           = MT_DEVICE,
103         }, {
104                 .virtual        = (unsigned long)S5P_VA_GPIO3,
105                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
106                 .length         = SZ_256,
107                 .type           = MT_DEVICE,
108         }, {
109                 .virtual        = (unsigned long)S5P_VA_DMC0,
110                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
111                 .length         = SZ_4K,
112                 .type           = MT_DEVICE,
113         }, {
114                 .virtual        = (unsigned long)S5P_VA_SROMC,
115                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
116                 .length         = SZ_4K,
117                 .type           = MT_DEVICE,
118         }, {
119                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
120                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
121                 .length         = SZ_4K,
122                 .type           = MT_DEVICE,
123         },
124 };
125
126 static struct map_desc exynos4_iodesc0[] __initdata = {
127         {
128                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
129                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
130                 .length         = SZ_4K,
131                 .type           = MT_DEVICE,
132         },
133 };
134
135 static struct map_desc exynos4_iodesc1[] __initdata = {
136         {
137                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
139                 .length         = SZ_4K,
140                 .type           = MT_DEVICE,
141         },
142 };
143
144 static void exynos_idle(void)
145 {
146         if (!need_resched())
147                 cpu_do_idle();
148
149         local_irq_enable();
150 }
151
152 static void exynos4_sw_reset(void)
153 {
154         __raw_writel(0x1, S5P_SWRESET);
155 }
156
157 /*
158  * exynos_map_io
159  *
160  * register the standard cpu IO areas
161  */
162 void __init exynos4_map_io(void)
163 {
164         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
165         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
166
167         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
168                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
169         else
170                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
171
172         /* initialize device information early */
173         exynos4_default_sdhci0();
174         exynos4_default_sdhci1();
175         exynos4_default_sdhci2();
176         exynos4_default_sdhci3();
177
178         s3c_adc_setname("samsung-adc-v3");
179
180         s3c_fimc_setname(0, "exynos4-fimc");
181         s3c_fimc_setname(1, "exynos4-fimc");
182         s3c_fimc_setname(2, "exynos4-fimc");
183         s3c_fimc_setname(3, "exynos4-fimc");
184
185         /* The I2C bus controllers are directly compatible with s3c2440 */
186         s3c_i2c0_setname("s3c2440-i2c");
187         s3c_i2c1_setname("s3c2440-i2c");
188         s3c_i2c2_setname("s3c2440-i2c");
189
190         s5p_fb_setname(0, "exynos4-fb");
191         s5p_hdmi_setname("exynos4-hdmi");
192 }
193
194 void __init exynos4_init_clocks(int xtal)
195 {
196         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
197
198         s3c24xx_register_baseclocks(xtal);
199         s5p_register_clocks(xtal);
200
201         if (soc_is_exynos4210())
202                 exynos4210_register_clocks();
203         else if (soc_is_exynos4212() || soc_is_exynos4412())
204                 exynos4212_register_clocks();
205
206         exynos4_register_clocks();
207         exynos4_setup_clocks();
208 }
209
210 static void exynos4_gic_irq_fix_base(struct irq_data *d)
211 {
212         struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
213
214         gic_data->cpu_base = S5P_VA_GIC_CPU +
215                             (gic_bank_offset * smp_processor_id());
216
217         gic_data->dist_base = S5P_VA_GIC_DIST +
218                             (gic_bank_offset * smp_processor_id());
219 }
220
221 void __init exynos4_init_irq(void)
222 {
223         int irq;
224
225         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
226
227         gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
228         gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
229         gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
230         gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
231
232         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
233
234                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
235                                 COMBINER_IRQ(irq, 0));
236                 combiner_cascade_irq(irq, IRQ_SPI(irq));
237         }
238
239         /* The parameters of s5p_init_irq() are for VIC init.
240          * Theses parameters should be NULL and 0 because EXYNOS4
241          * uses GIC instead of VIC.
242          */
243         s5p_init_irq(NULL, 0);
244 }
245
246 struct sysdev_class exynos4_sysclass = {
247         .name   = "exynos4-core",
248 };
249
250 static struct sys_device exynos4_sysdev = {
251         .cls    = &exynos4_sysclass,
252 };
253
254 static int __init exynos4_core_init(void)
255 {
256         return sysdev_class_register(&exynos4_sysclass);
257 }
258 core_initcall(exynos4_core_init);
259
260 #ifdef CONFIG_CACHE_L2X0
261 static int __init exynos4_l2x0_cache_init(void)
262 {
263         /* TAG, Data Latency Control: 2cycle */
264         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
265
266         if (soc_is_exynos4210())
267                 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
268         else if (soc_is_exynos4212() || soc_is_exynos4412())
269                 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
270
271         /* L2X0 Prefetch Control */
272         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
273
274         /* L2X0 Power Control */
275         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
276                      S5P_VA_L2CC + L2X0_POWER_CTRL);
277
278         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
279
280         return 0;
281 }
282
283 early_initcall(exynos4_l2x0_cache_init);
284 #endif
285
286 int __init exynos_init(void)
287 {
288         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
289
290         /* set idle function */
291         pm_idle = exynos_idle;
292
293         /* set sw_reset function */
294         if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
295                 s5p_reset_hook = exynos4_sw_reset;
296
297         return sysdev_register(&exynos4_sysdev);
298 }