ARM: 5877/1: ep93xx: use pr_fmt in core.c
[linux-2.6.git] / arch / arm / mach-ep93xx / core.c
1 /*
2  * arch/arm/mach-ep93xx/core.c
3  * Core routines for Cirrus EP93xx chips.
4  *
5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
7  *
8  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9  * role in the ep93xx linux community.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or (at
14  * your option) any later version.
15  */
16
17 #define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/interrupt.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/timex.h>
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/leds.h>
28 #include <linux/termios.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/serial.h>
31 #include <linux/i2c.h>
32 #include <linux/i2c-gpio.h>
33
34 #include <mach/hardware.h>
35 #include <mach/fb.h>
36 #include <mach/ep93xx_keypad.h>
37
38 #include <asm/mach/map.h>
39 #include <asm/mach/time.h>
40 #include <asm/mach/irq.h>
41
42 #include <asm/hardware/vic.h>
43
44
45 /*************************************************************************
46  * Static I/O mappings that are needed for all EP93xx platforms
47  *************************************************************************/
48 static struct map_desc ep93xx_io_desc[] __initdata = {
49         {
50                 .virtual        = EP93XX_AHB_VIRT_BASE,
51                 .pfn            = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
52                 .length         = EP93XX_AHB_SIZE,
53                 .type           = MT_DEVICE,
54         }, {
55                 .virtual        = EP93XX_APB_VIRT_BASE,
56                 .pfn            = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
57                 .length         = EP93XX_APB_SIZE,
58                 .type           = MT_DEVICE,
59         },
60 };
61
62 void __init ep93xx_map_io(void)
63 {
64         iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
65 }
66
67
68 /*************************************************************************
69  * Timer handling for EP93xx
70  *************************************************************************
71  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
72  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
73  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
74  * is free-running, and can't generate interrupts.
75  *
76  * The 508 kHz timers are ideal for use for the timer interrupt, as the
77  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
78  * bit timers (timer 1) since we don't need more than 16 bits of reload
79  * value as long as HZ >= 8.
80  *
81  * The higher clock rate of timer 4 makes it a better choice than the
82  * other timers for use in gettimeoffset(), while the fact that it can't
83  * generate interrupts means we don't have to worry about not being able
84  * to use this timer for something else.  We also use timer 4 for keeping
85  * track of lost jiffies.
86  */
87 static unsigned int last_jiffy_time;
88
89 #define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
90
91 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
92 {
93         __raw_writel(1, EP93XX_TIMER1_CLEAR);
94         while ((signed long)
95                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
96                                                 >= TIMER4_TICKS_PER_JIFFY) {
97                 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
98                 timer_tick();
99         }
100
101         return IRQ_HANDLED;
102 }
103
104 static struct irqaction ep93xx_timer_irq = {
105         .name           = "ep93xx timer",
106         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
107         .handler        = ep93xx_timer_interrupt,
108 };
109
110 static void __init ep93xx_timer_init(void)
111 {
112         /* Enable periodic HZ timer.  */
113         __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
114         __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
115         __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
116
117         /* Enable lost jiffy timer.  */
118         __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
119
120         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
121 }
122
123 static unsigned long ep93xx_gettimeoffset(void)
124 {
125         int offset;
126
127         offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
128
129         /* Calculate (1000000 / 983040) * offset.  */
130         return offset + (53 * offset / 3072);
131 }
132
133 struct sys_timer ep93xx_timer = {
134         .init           = ep93xx_timer_init,
135         .offset         = ep93xx_gettimeoffset,
136 };
137
138
139 /*************************************************************************
140  * GPIO handling for EP93xx
141  *************************************************************************/
142 static unsigned char gpio_int_unmasked[3];
143 static unsigned char gpio_int_enabled[3];
144 static unsigned char gpio_int_type1[3];
145 static unsigned char gpio_int_type2[3];
146 static unsigned char gpio_int_debounce[3];
147
148 /* Port ordering is: A B F */
149 static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
150 static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
151 static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
152 static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
153 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
154
155 void ep93xx_gpio_update_int_params(unsigned port)
156 {
157         BUG_ON(port > 2);
158
159         __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
160
161         __raw_writeb(gpio_int_type2[port],
162                 EP93XX_GPIO_REG(int_type2_register_offset[port]));
163
164         __raw_writeb(gpio_int_type1[port],
165                 EP93XX_GPIO_REG(int_type1_register_offset[port]));
166
167         __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
168                 EP93XX_GPIO_REG(int_en_register_offset[port]));
169 }
170
171 void ep93xx_gpio_int_mask(unsigned line)
172 {
173         gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
174 }
175
176 void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
177 {
178         int line = irq_to_gpio(irq);
179         int port = line >> 3;
180         int port_mask = 1 << (line & 7);
181
182         if (enable)
183                 gpio_int_debounce[port] |= port_mask;
184         else
185                 gpio_int_debounce[port] &= ~port_mask;
186
187         __raw_writeb(gpio_int_debounce[port],
188                 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
189 }
190 EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
191
192 /*************************************************************************
193  * EP93xx IRQ handling
194  *************************************************************************/
195 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
196 {
197         unsigned char status;
198         int i;
199
200         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
201         for (i = 0; i < 8; i++) {
202                 if (status & (1 << i)) {
203                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
204                         generic_handle_irq(gpio_irq);
205                 }
206         }
207
208         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
209         for (i = 0; i < 8; i++) {
210                 if (status & (1 << i)) {
211                         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
212                         generic_handle_irq(gpio_irq);
213                 }
214         }
215 }
216
217 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
218 {
219         /*
220          * map discontiguous hw irq range to continous sw irq range:
221          *
222          *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
223          */
224         int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
225         int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
226
227         generic_handle_irq(gpio_irq);
228 }
229
230 static void ep93xx_gpio_irq_ack(unsigned int irq)
231 {
232         int line = irq_to_gpio(irq);
233         int port = line >> 3;
234         int port_mask = 1 << (line & 7);
235
236         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
237                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
238                 ep93xx_gpio_update_int_params(port);
239         }
240
241         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
242 }
243
244 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
245 {
246         int line = irq_to_gpio(irq);
247         int port = line >> 3;
248         int port_mask = 1 << (line & 7);
249
250         if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
251                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
252
253         gpio_int_unmasked[port] &= ~port_mask;
254         ep93xx_gpio_update_int_params(port);
255
256         __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
257 }
258
259 static void ep93xx_gpio_irq_mask(unsigned int irq)
260 {
261         int line = irq_to_gpio(irq);
262         int port = line >> 3;
263
264         gpio_int_unmasked[port] &= ~(1 << (line & 7));
265         ep93xx_gpio_update_int_params(port);
266 }
267
268 static void ep93xx_gpio_irq_unmask(unsigned int irq)
269 {
270         int line = irq_to_gpio(irq);
271         int port = line >> 3;
272
273         gpio_int_unmasked[port] |= 1 << (line & 7);
274         ep93xx_gpio_update_int_params(port);
275 }
276
277
278 /*
279  * gpio_int_type1 controls whether the interrupt is level (0) or
280  * edge (1) triggered, while gpio_int_type2 controls whether it
281  * triggers on low/falling (0) or high/rising (1).
282  */
283 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
284 {
285         struct irq_desc *desc = irq_desc + irq;
286         const int gpio = irq_to_gpio(irq);
287         const int port = gpio >> 3;
288         const int port_mask = 1 << (gpio & 7);
289
290         gpio_direction_input(gpio);
291
292         switch (type) {
293         case IRQ_TYPE_EDGE_RISING:
294                 gpio_int_type1[port] |= port_mask;
295                 gpio_int_type2[port] |= port_mask;
296                 desc->handle_irq = handle_edge_irq;
297                 break;
298         case IRQ_TYPE_EDGE_FALLING:
299                 gpio_int_type1[port] |= port_mask;
300                 gpio_int_type2[port] &= ~port_mask;
301                 desc->handle_irq = handle_edge_irq;
302                 break;
303         case IRQ_TYPE_LEVEL_HIGH:
304                 gpio_int_type1[port] &= ~port_mask;
305                 gpio_int_type2[port] |= port_mask;
306                 desc->handle_irq = handle_level_irq;
307                 break;
308         case IRQ_TYPE_LEVEL_LOW:
309                 gpio_int_type1[port] &= ~port_mask;
310                 gpio_int_type2[port] &= ~port_mask;
311                 desc->handle_irq = handle_level_irq;
312                 break;
313         case IRQ_TYPE_EDGE_BOTH:
314                 gpio_int_type1[port] |= port_mask;
315                 /* set initial polarity based on current input level */
316                 if (gpio_get_value(gpio))
317                         gpio_int_type2[port] &= ~port_mask; /* falling */
318                 else
319                         gpio_int_type2[port] |= port_mask; /* rising */
320                 desc->handle_irq = handle_edge_irq;
321                 break;
322         default:
323                 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
324                 return -EINVAL;
325         }
326
327         gpio_int_enabled[port] |= port_mask;
328
329         desc->status &= ~IRQ_TYPE_SENSE_MASK;
330         desc->status |= type & IRQ_TYPE_SENSE_MASK;
331
332         ep93xx_gpio_update_int_params(port);
333
334         return 0;
335 }
336
337 static struct irq_chip ep93xx_gpio_irq_chip = {
338         .name           = "GPIO",
339         .ack            = ep93xx_gpio_irq_ack,
340         .mask_ack       = ep93xx_gpio_irq_mask_ack,
341         .mask           = ep93xx_gpio_irq_mask,
342         .unmask         = ep93xx_gpio_irq_unmask,
343         .set_type       = ep93xx_gpio_irq_type,
344 };
345
346
347 void __init ep93xx_init_irq(void)
348 {
349         int gpio_irq;
350
351         vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
352         vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
353
354         for (gpio_irq = gpio_to_irq(0);
355              gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
356                 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
357                 set_irq_handler(gpio_irq, handle_level_irq);
358                 set_irq_flags(gpio_irq, IRQF_VALID);
359         }
360
361         set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
362         set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
363         set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
364         set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
365         set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
366         set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
367         set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
368         set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
369         set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
370 }
371
372
373 /*************************************************************************
374  * EP93xx System Controller Software Locked register handling
375  *************************************************************************/
376
377 /*
378  * syscon_swlock prevents anything else from writing to the syscon
379  * block while a software locked register is being written.
380  */
381 static DEFINE_SPINLOCK(syscon_swlock);
382
383 void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
384 {
385         unsigned long flags;
386
387         spin_lock_irqsave(&syscon_swlock, flags);
388
389         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
390         __raw_writel(val, reg);
391
392         spin_unlock_irqrestore(&syscon_swlock, flags);
393 }
394 EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
395
396 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
397 {
398         unsigned long flags;
399         unsigned int val;
400
401         spin_lock_irqsave(&syscon_swlock, flags);
402
403         val = __raw_readl(EP93XX_SYSCON_DEVCFG);
404         val |= set_bits;
405         val &= ~clear_bits;
406         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
407         __raw_writel(val, EP93XX_SYSCON_DEVCFG);
408
409         spin_unlock_irqrestore(&syscon_swlock, flags);
410 }
411 EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
412
413
414 /*************************************************************************
415  * EP93xx peripheral handling
416  *************************************************************************/
417 #define EP93XX_UART_MCR_OFFSET          (0x0100)
418
419 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
420                                   void __iomem *base, unsigned int mctrl)
421 {
422         unsigned int mcr;
423
424         mcr = 0;
425         if (!(mctrl & TIOCM_RTS))
426                 mcr |= 2;
427         if (!(mctrl & TIOCM_DTR))
428                 mcr |= 1;
429
430         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
431 }
432
433 static struct amba_pl010_data ep93xx_uart_data = {
434         .set_mctrl      = ep93xx_uart_set_mctrl,
435 };
436
437 static struct amba_device uart1_device = {
438         .dev            = {
439                 .init_name      = "apb:uart1",
440                 .platform_data  = &ep93xx_uart_data,
441         },
442         .res            = {
443                 .start  = EP93XX_UART1_PHYS_BASE,
444                 .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
445                 .flags  = IORESOURCE_MEM,
446         },
447         .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
448         .periphid       = 0x00041010,
449 };
450
451 static struct amba_device uart2_device = {
452         .dev            = {
453                 .init_name      = "apb:uart2",
454                 .platform_data  = &ep93xx_uart_data,
455         },
456         .res            = {
457                 .start  = EP93XX_UART2_PHYS_BASE,
458                 .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
459                 .flags  = IORESOURCE_MEM,
460         },
461         .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
462         .periphid       = 0x00041010,
463 };
464
465 static struct amba_device uart3_device = {
466         .dev            = {
467                 .init_name      = "apb:uart3",
468                 .platform_data  = &ep93xx_uart_data,
469         },
470         .res            = {
471                 .start  = EP93XX_UART3_PHYS_BASE,
472                 .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
473                 .flags  = IORESOURCE_MEM,
474         },
475         .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
476         .periphid       = 0x00041010,
477 };
478
479
480 static struct resource ep93xx_rtc_resource[] = {
481         {
482                 .start          = EP93XX_RTC_PHYS_BASE,
483                 .end            = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
484                 .flags          = IORESOURCE_MEM,
485         },
486 };
487
488 static struct platform_device ep93xx_rtc_device = {
489         .name           = "ep93xx-rtc",
490         .id             = -1,
491         .num_resources  = ARRAY_SIZE(ep93xx_rtc_resource),
492         .resource       = ep93xx_rtc_resource,
493 };
494
495
496 static struct resource ep93xx_ohci_resources[] = {
497         [0] = {
498                 .start  = EP93XX_USB_PHYS_BASE,
499                 .end    = EP93XX_USB_PHYS_BASE + 0x0fff,
500                 .flags  = IORESOURCE_MEM,
501         },
502         [1] = {
503                 .start  = IRQ_EP93XX_USB,
504                 .end    = IRQ_EP93XX_USB,
505                 .flags  = IORESOURCE_IRQ,
506         },
507 };
508
509
510 static struct platform_device ep93xx_ohci_device = {
511         .name           = "ep93xx-ohci",
512         .id             = -1,
513         .dev            = {
514                 .dma_mask               = &ep93xx_ohci_device.dev.coherent_dma_mask,
515                 .coherent_dma_mask      = DMA_BIT_MASK(32),
516         },
517         .num_resources  = ARRAY_SIZE(ep93xx_ohci_resources),
518         .resource       = ep93xx_ohci_resources,
519 };
520
521 static struct ep93xx_eth_data ep93xx_eth_data;
522
523 static struct resource ep93xx_eth_resource[] = {
524         {
525                 .start  = EP93XX_ETHERNET_PHYS_BASE,
526                 .end    = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
527                 .flags  = IORESOURCE_MEM,
528         }, {
529                 .start  = IRQ_EP93XX_ETHERNET,
530                 .end    = IRQ_EP93XX_ETHERNET,
531                 .flags  = IORESOURCE_IRQ,
532         }
533 };
534
535 static struct platform_device ep93xx_eth_device = {
536         .name           = "ep93xx-eth",
537         .id             = -1,
538         .dev            = {
539                 .platform_data  = &ep93xx_eth_data,
540         },
541         .num_resources  = ARRAY_SIZE(ep93xx_eth_resource),
542         .resource       = ep93xx_eth_resource,
543 };
544
545 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
546 {
547         if (copy_addr)
548                 memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
549
550         ep93xx_eth_data = *data;
551         platform_device_register(&ep93xx_eth_device);
552 }
553
554
555 /*************************************************************************
556  * EP93xx i2c peripheral handling
557  *************************************************************************/
558 static struct i2c_gpio_platform_data ep93xx_i2c_data;
559
560 static struct platform_device ep93xx_i2c_device = {
561         .name                   = "i2c-gpio",
562         .id                     = 0,
563         .dev.platform_data      = &ep93xx_i2c_data,
564 };
565
566 void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
567                                 struct i2c_board_info *devices, int num)
568 {
569         /*
570          * Set the EEPROM interface pin drive type control.
571          * Defines the driver type for the EECLK and EEDAT pins as either
572          * open drain, which will require an external pull-up, or a normal
573          * CMOS driver.
574          */
575         if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
576                 pr_warning("sda != EEDAT, open drain has no effect\n");
577         if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
578                 pr_warning("scl != EECLK, open drain has no effect\n");
579
580         __raw_writel((data->sda_is_open_drain << 1) |
581                      (data->scl_is_open_drain << 0),
582                      EP93XX_GPIO_EEDRIVE);
583
584         ep93xx_i2c_data = *data;
585         i2c_register_board_info(0, devices, num);
586         platform_device_register(&ep93xx_i2c_device);
587 }
588
589
590 /*************************************************************************
591  * EP93xx LEDs
592  *************************************************************************/
593 static struct gpio_led ep93xx_led_pins[] = {
594         {
595                 .name                   = "platform:grled",
596                 .gpio                   = EP93XX_GPIO_LINE_GRLED,
597         }, {
598                 .name                   = "platform:rdled",
599                 .gpio                   = EP93XX_GPIO_LINE_RDLED,
600         },
601 };
602
603 static struct gpio_led_platform_data ep93xx_led_data = {
604         .num_leds       = ARRAY_SIZE(ep93xx_led_pins),
605         .leds           = ep93xx_led_pins,
606 };
607
608 static struct platform_device ep93xx_leds = {
609         .name           = "leds-gpio",
610         .id             = -1,
611         .dev            = {
612                 .platform_data  = &ep93xx_led_data,
613         },
614 };
615
616
617 /*************************************************************************
618  * EP93xx pwm peripheral handling
619  *************************************************************************/
620 static struct resource ep93xx_pwm0_resource[] = {
621         {
622                 .start  = EP93XX_PWM_PHYS_BASE,
623                 .end    = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
624                 .flags  = IORESOURCE_MEM,
625         },
626 };
627
628 static struct platform_device ep93xx_pwm0_device = {
629         .name           = "ep93xx-pwm",
630         .id             = 0,
631         .num_resources  = ARRAY_SIZE(ep93xx_pwm0_resource),
632         .resource       = ep93xx_pwm0_resource,
633 };
634
635 static struct resource ep93xx_pwm1_resource[] = {
636         {
637                 .start  = EP93XX_PWM_PHYS_BASE + 0x20,
638                 .end    = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
639                 .flags  = IORESOURCE_MEM,
640         },
641 };
642
643 static struct platform_device ep93xx_pwm1_device = {
644         .name           = "ep93xx-pwm",
645         .id             = 1,
646         .num_resources  = ARRAY_SIZE(ep93xx_pwm1_resource),
647         .resource       = ep93xx_pwm1_resource,
648 };
649
650 void __init ep93xx_register_pwm(int pwm0, int pwm1)
651 {
652         if (pwm0)
653                 platform_device_register(&ep93xx_pwm0_device);
654
655         /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
656         if (pwm1)
657                 platform_device_register(&ep93xx_pwm1_device);
658 }
659
660 int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
661 {
662         int err;
663
664         if (pdev->id == 0) {
665                 err = 0;
666         } else if (pdev->id == 1) {
667                 err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
668                                    dev_name(&pdev->dev));
669                 if (err)
670                         return err;
671                 err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
672                 if (err)
673                         goto fail;
674
675                 /* PWM 1 output on EGPIO[14] */
676                 ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
677         } else {
678                 err = -ENODEV;
679         }
680
681         return err;
682
683 fail:
684         gpio_free(EP93XX_GPIO_LINE_EGPIO14);
685         return err;
686 }
687 EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
688
689 void ep93xx_pwm_release_gpio(struct platform_device *pdev)
690 {
691         if (pdev->id == 1) {
692                 gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
693                 gpio_free(EP93XX_GPIO_LINE_EGPIO14);
694
695                 /* EGPIO[14] used for GPIO */
696                 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
697         }
698 }
699 EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
700
701
702 /*************************************************************************
703  * EP93xx video peripheral handling
704  *************************************************************************/
705 static struct ep93xxfb_mach_info ep93xxfb_data;
706
707 static struct resource ep93xx_fb_resource[] = {
708         {
709                 .start          = EP93XX_RASTER_PHYS_BASE,
710                 .end            = EP93XX_RASTER_PHYS_BASE + 0x800 - 1,
711                 .flags          = IORESOURCE_MEM,
712         },
713 };
714
715 static struct platform_device ep93xx_fb_device = {
716         .name                   = "ep93xx-fb",
717         .id                     = -1,
718         .dev                    = {
719                 .platform_data  = &ep93xxfb_data,
720                 .coherent_dma_mask      = DMA_BIT_MASK(32),
721                 .dma_mask               = &ep93xx_fb_device.dev.coherent_dma_mask,
722         },
723         .num_resources          = ARRAY_SIZE(ep93xx_fb_resource),
724         .resource               = ep93xx_fb_resource,
725 };
726
727 void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
728 {
729         ep93xxfb_data = *data;
730         platform_device_register(&ep93xx_fb_device);
731 }
732
733
734 /*************************************************************************
735  * EP93xx matrix keypad peripheral handling
736  *************************************************************************/
737 static struct resource ep93xx_keypad_resource[] = {
738         {
739                 .start  = EP93XX_KEY_MATRIX_PHYS_BASE,
740                 .end    = EP93XX_KEY_MATRIX_PHYS_BASE + 0x0c - 1,
741                 .flags  = IORESOURCE_MEM,
742         }, {
743                 .start  = IRQ_EP93XX_KEY,
744                 .end    = IRQ_EP93XX_KEY,
745                 .flags  = IORESOURCE_IRQ,
746         },
747 };
748
749 static struct platform_device ep93xx_keypad_device = {
750         .name                   = "ep93xx-keypad",
751         .id                     = -1,
752         .num_resources          = ARRAY_SIZE(ep93xx_keypad_resource),
753         .resource               = ep93xx_keypad_resource,
754 };
755
756 void __init ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data)
757 {
758         ep93xx_keypad_device.dev.platform_data = data;
759         platform_device_register(&ep93xx_keypad_device);
760 }
761
762 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev)
763 {
764         int err;
765         int i;
766
767         for (i = 0; i < 8; i++) {
768                 err = gpio_request(EP93XX_GPIO_LINE_C(i), dev_name(&pdev->dev));
769                 if (err)
770                         goto fail_gpio_c;
771                 err = gpio_request(EP93XX_GPIO_LINE_D(i), dev_name(&pdev->dev));
772                 if (err)
773                         goto fail_gpio_d;
774         }
775
776         /* Enable the keypad controller; GPIO ports C and D used for keypad */
777         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_KEYS |
778                                  EP93XX_SYSCON_DEVCFG_GONK);
779
780         return 0;
781
782 fail_gpio_d:
783         gpio_free(EP93XX_GPIO_LINE_C(i));
784 fail_gpio_c:
785         for ( ; i >= 0; --i) {
786                 gpio_free(EP93XX_GPIO_LINE_C(i));
787                 gpio_free(EP93XX_GPIO_LINE_D(i));
788         }
789         return err;
790 }
791 EXPORT_SYMBOL(ep93xx_keypad_acquire_gpio);
792
793 void ep93xx_keypad_release_gpio(struct platform_device *pdev)
794 {
795         int i;
796
797         for (i = 0; i < 8; i++) {
798                 gpio_free(EP93XX_GPIO_LINE_C(i));
799                 gpio_free(EP93XX_GPIO_LINE_D(i));
800         }
801
802         /* Disable the keypad controller; GPIO ports C and D used for GPIO */
803         ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
804                                EP93XX_SYSCON_DEVCFG_GONK);
805 }
806 EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
807
808
809 extern void ep93xx_gpio_init(void);
810
811 void __init ep93xx_init_devices(void)
812 {
813         /* Disallow access to MaverickCrunch initially */
814         ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
815
816         ep93xx_gpio_init();
817
818         amba_device_register(&uart1_device, &iomem_resource);
819         amba_device_register(&uart2_device, &iomem_resource);
820         amba_device_register(&uart3_device, &iomem_resource);
821
822         platform_device_register(&ep93xx_rtc_device);
823         platform_device_register(&ep93xx_ohci_device);
824         platform_device_register(&ep93xx_leds);
825 }