Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
[linux-2.6.git] / arch / arm / mach-davinci / dm646x.c
1 /*
2  * TI DaVinci DM644x chip specific setup
3  *
4  * Author: Kevin Hilman, Deep Root Systems, LLC
5  *
6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7  * the terms of the GNU General Public License version 2. This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  */
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/serial_8250.h>
15 #include <linux/platform_device.h>
16 #include <linux/gpio.h>
17
18 #include <asm/mach/map.h>
19
20 #include <mach/dm646x.h>
21 #include <mach/cputype.h>
22 #include <mach/edma.h>
23 #include <mach/irqs.h>
24 #include <mach/psc.h>
25 #include <mach/mux.h>
26 #include <mach/time.h>
27 #include <mach/serial.h>
28 #include <mach/common.h>
29 #include <mach/asp.h>
30
31 #include "clock.h"
32 #include "mux.h"
33
34 #define DAVINCI_VPIF_BASE       (0x01C12000)
35 #define VDD3P3V_PWDN_OFFSET     (0x48)
36 #define VSCLKDIS_OFFSET         (0x6C)
37
38 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
39                                         BIT_MASK(0))
40 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
41                                         BIT_MASK(8))
42
43 /*
44  * Device specific clocks
45  */
46 #define DM646X_REF_FREQ         27000000
47 #define DM646X_AUX_FREQ         24000000
48
49 static struct pll_data pll1_data = {
50         .num       = 1,
51         .phys_base = DAVINCI_PLL1_BASE,
52 };
53
54 static struct pll_data pll2_data = {
55         .num       = 2,
56         .phys_base = DAVINCI_PLL2_BASE,
57 };
58
59 static struct clk ref_clk = {
60         .name = "ref_clk",
61         .rate = DM646X_REF_FREQ,
62         .set_rate = davinci_simple_set_rate,
63 };
64
65 static struct clk aux_clkin = {
66         .name = "aux_clkin",
67         .rate = DM646X_AUX_FREQ,
68 };
69
70 static struct clk pll1_clk = {
71         .name = "pll1",
72         .parent = &ref_clk,
73         .pll_data = &pll1_data,
74         .flags = CLK_PLL,
75 };
76
77 static struct clk pll1_sysclk1 = {
78         .name = "pll1_sysclk1",
79         .parent = &pll1_clk,
80         .flags = CLK_PLL,
81         .div_reg = PLLDIV1,
82 };
83
84 static struct clk pll1_sysclk2 = {
85         .name = "pll1_sysclk2",
86         .parent = &pll1_clk,
87         .flags = CLK_PLL,
88         .div_reg = PLLDIV2,
89 };
90
91 static struct clk pll1_sysclk3 = {
92         .name = "pll1_sysclk3",
93         .parent = &pll1_clk,
94         .flags = CLK_PLL,
95         .div_reg = PLLDIV3,
96 };
97
98 static struct clk pll1_sysclk4 = {
99         .name = "pll1_sysclk4",
100         .parent = &pll1_clk,
101         .flags = CLK_PLL,
102         .div_reg = PLLDIV4,
103 };
104
105 static struct clk pll1_sysclk5 = {
106         .name = "pll1_sysclk5",
107         .parent = &pll1_clk,
108         .flags = CLK_PLL,
109         .div_reg = PLLDIV5,
110 };
111
112 static struct clk pll1_sysclk6 = {
113         .name = "pll1_sysclk6",
114         .parent = &pll1_clk,
115         .flags = CLK_PLL,
116         .div_reg = PLLDIV6,
117 };
118
119 static struct clk pll1_sysclk8 = {
120         .name = "pll1_sysclk8",
121         .parent = &pll1_clk,
122         .flags = CLK_PLL,
123         .div_reg = PLLDIV8,
124 };
125
126 static struct clk pll1_sysclk9 = {
127         .name = "pll1_sysclk9",
128         .parent = &pll1_clk,
129         .flags = CLK_PLL,
130         .div_reg = PLLDIV9,
131 };
132
133 static struct clk pll1_sysclkbp = {
134         .name = "pll1_sysclkbp",
135         .parent = &pll1_clk,
136         .flags = CLK_PLL | PRE_PLL,
137         .div_reg = BPDIV,
138 };
139
140 static struct clk pll1_aux_clk = {
141         .name = "pll1_aux_clk",
142         .parent = &pll1_clk,
143         .flags = CLK_PLL | PRE_PLL,
144 };
145
146 static struct clk pll2_clk = {
147         .name = "pll2_clk",
148         .parent = &ref_clk,
149         .pll_data = &pll2_data,
150         .flags = CLK_PLL,
151 };
152
153 static struct clk pll2_sysclk1 = {
154         .name = "pll2_sysclk1",
155         .parent = &pll2_clk,
156         .flags = CLK_PLL,
157         .div_reg = PLLDIV1,
158 };
159
160 static struct clk dsp_clk = {
161         .name = "dsp",
162         .parent = &pll1_sysclk1,
163         .lpsc = DM646X_LPSC_C64X_CPU,
164         .flags = PSC_DSP,
165         .usecount = 1,                  /* REVISIT how to disable? */
166 };
167
168 static struct clk arm_clk = {
169         .name = "arm",
170         .parent = &pll1_sysclk2,
171         .lpsc = DM646X_LPSC_ARM,
172         .flags = ALWAYS_ENABLED,
173 };
174
175 static struct clk edma_cc_clk = {
176         .name = "edma_cc",
177         .parent = &pll1_sysclk2,
178         .lpsc = DM646X_LPSC_TPCC,
179         .flags = ALWAYS_ENABLED,
180 };
181
182 static struct clk edma_tc0_clk = {
183         .name = "edma_tc0",
184         .parent = &pll1_sysclk2,
185         .lpsc = DM646X_LPSC_TPTC0,
186         .flags = ALWAYS_ENABLED,
187 };
188
189 static struct clk edma_tc1_clk = {
190         .name = "edma_tc1",
191         .parent = &pll1_sysclk2,
192         .lpsc = DM646X_LPSC_TPTC1,
193         .flags = ALWAYS_ENABLED,
194 };
195
196 static struct clk edma_tc2_clk = {
197         .name = "edma_tc2",
198         .parent = &pll1_sysclk2,
199         .lpsc = DM646X_LPSC_TPTC2,
200         .flags = ALWAYS_ENABLED,
201 };
202
203 static struct clk edma_tc3_clk = {
204         .name = "edma_tc3",
205         .parent = &pll1_sysclk2,
206         .lpsc = DM646X_LPSC_TPTC3,
207         .flags = ALWAYS_ENABLED,
208 };
209
210 static struct clk uart0_clk = {
211         .name = "uart0",
212         .parent = &aux_clkin,
213         .lpsc = DM646X_LPSC_UART0,
214 };
215
216 static struct clk uart1_clk = {
217         .name = "uart1",
218         .parent = &aux_clkin,
219         .lpsc = DM646X_LPSC_UART1,
220 };
221
222 static struct clk uart2_clk = {
223         .name = "uart2",
224         .parent = &aux_clkin,
225         .lpsc = DM646X_LPSC_UART2,
226 };
227
228 static struct clk i2c_clk = {
229         .name = "I2CCLK",
230         .parent = &pll1_sysclk3,
231         .lpsc = DM646X_LPSC_I2C,
232 };
233
234 static struct clk gpio_clk = {
235         .name = "gpio",
236         .parent = &pll1_sysclk3,
237         .lpsc = DM646X_LPSC_GPIO,
238 };
239
240 static struct clk mcasp0_clk = {
241         .name = "mcasp0",
242         .parent = &pll1_sysclk3,
243         .lpsc = DM646X_LPSC_McASP0,
244 };
245
246 static struct clk mcasp1_clk = {
247         .name = "mcasp1",
248         .parent = &pll1_sysclk3,
249         .lpsc = DM646X_LPSC_McASP1,
250 };
251
252 static struct clk aemif_clk = {
253         .name = "aemif",
254         .parent = &pll1_sysclk3,
255         .lpsc = DM646X_LPSC_AEMIF,
256         .flags = ALWAYS_ENABLED,
257 };
258
259 static struct clk emac_clk = {
260         .name = "emac",
261         .parent = &pll1_sysclk3,
262         .lpsc = DM646X_LPSC_EMAC,
263 };
264
265 static struct clk pwm0_clk = {
266         .name = "pwm0",
267         .parent = &pll1_sysclk3,
268         .lpsc = DM646X_LPSC_PWM0,
269         .usecount = 1,            /* REVIST: disabling hangs system */
270 };
271
272 static struct clk pwm1_clk = {
273         .name = "pwm1",
274         .parent = &pll1_sysclk3,
275         .lpsc = DM646X_LPSC_PWM1,
276         .usecount = 1,            /* REVIST: disabling hangs system */
277 };
278
279 static struct clk timer0_clk = {
280         .name = "timer0",
281         .parent = &pll1_sysclk3,
282         .lpsc = DM646X_LPSC_TIMER0,
283 };
284
285 static struct clk timer1_clk = {
286         .name = "timer1",
287         .parent = &pll1_sysclk3,
288         .lpsc = DM646X_LPSC_TIMER1,
289 };
290
291 static struct clk timer2_clk = {
292         .name = "timer2",
293         .parent = &pll1_sysclk3,
294         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
295 };
296
297
298 static struct clk ide_clk = {
299         .name = "ide",
300         .parent = &pll1_sysclk4,
301         .lpsc = DAVINCI_LPSC_ATA,
302 };
303
304 static struct clk vpif0_clk = {
305         .name = "vpif0",
306         .parent = &ref_clk,
307         .lpsc = DM646X_LPSC_VPSSMSTR,
308         .flags = ALWAYS_ENABLED,
309 };
310
311 static struct clk vpif1_clk = {
312         .name = "vpif1",
313         .parent = &ref_clk,
314         .lpsc = DM646X_LPSC_VPSSSLV,
315         .flags = ALWAYS_ENABLED,
316 };
317
318 static struct clk_lookup dm646x_clks[] = {
319         CLK(NULL, "ref", &ref_clk),
320         CLK(NULL, "aux", &aux_clkin),
321         CLK(NULL, "pll1", &pll1_clk),
322         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
323         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
324         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
325         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
326         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
327         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
328         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
329         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
330         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
331         CLK(NULL, "pll1_aux", &pll1_aux_clk),
332         CLK(NULL, "pll2", &pll2_clk),
333         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
334         CLK(NULL, "dsp", &dsp_clk),
335         CLK(NULL, "arm", &arm_clk),
336         CLK(NULL, "edma_cc", &edma_cc_clk),
337         CLK(NULL, "edma_tc0", &edma_tc0_clk),
338         CLK(NULL, "edma_tc1", &edma_tc1_clk),
339         CLK(NULL, "edma_tc2", &edma_tc2_clk),
340         CLK(NULL, "edma_tc3", &edma_tc3_clk),
341         CLK(NULL, "uart0", &uart0_clk),
342         CLK(NULL, "uart1", &uart1_clk),
343         CLK(NULL, "uart2", &uart2_clk),
344         CLK("i2c_davinci.1", NULL, &i2c_clk),
345         CLK(NULL, "gpio", &gpio_clk),
346         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
347         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
348         CLK(NULL, "aemif", &aemif_clk),
349         CLK("davinci_emac.1", NULL, &emac_clk),
350         CLK(NULL, "pwm0", &pwm0_clk),
351         CLK(NULL, "pwm1", &pwm1_clk),
352         CLK(NULL, "timer0", &timer0_clk),
353         CLK(NULL, "timer1", &timer1_clk),
354         CLK("watchdog", NULL, &timer2_clk),
355         CLK("palm_bk3710", NULL, &ide_clk),
356         CLK(NULL, "vpif0", &vpif0_clk),
357         CLK(NULL, "vpif1", &vpif1_clk),
358         CLK(NULL, NULL, NULL),
359 };
360
361 static struct emac_platform_data dm646x_emac_pdata = {
362         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
363         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
364         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
365         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
366         .version                = EMAC_VERSION_2,
367 };
368
369 static struct resource dm646x_emac_resources[] = {
370         {
371                 .start  = DM646X_EMAC_BASE,
372                 .end    = DM646X_EMAC_BASE + SZ_16K - 1,
373                 .flags  = IORESOURCE_MEM,
374         },
375         {
376                 .start  = IRQ_DM646X_EMACRXTHINT,
377                 .end    = IRQ_DM646X_EMACRXTHINT,
378                 .flags  = IORESOURCE_IRQ,
379         },
380         {
381                 .start  = IRQ_DM646X_EMACRXINT,
382                 .end    = IRQ_DM646X_EMACRXINT,
383                 .flags  = IORESOURCE_IRQ,
384         },
385         {
386                 .start  = IRQ_DM646X_EMACTXINT,
387                 .end    = IRQ_DM646X_EMACTXINT,
388                 .flags  = IORESOURCE_IRQ,
389         },
390         {
391                 .start  = IRQ_DM646X_EMACMISCINT,
392                 .end    = IRQ_DM646X_EMACMISCINT,
393                 .flags  = IORESOURCE_IRQ,
394         },
395 };
396
397 static struct platform_device dm646x_emac_device = {
398         .name           = "davinci_emac",
399         .id             = 1,
400         .dev = {
401                 .platform_data  = &dm646x_emac_pdata,
402         },
403         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
404         .resource       = dm646x_emac_resources,
405 };
406
407 static struct resource dm646x_mdio_resources[] = {
408         {
409                 .start  = DM646X_EMAC_MDIO_BASE,
410                 .end    = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
411                 .flags  = IORESOURCE_MEM,
412         },
413 };
414
415 static struct platform_device dm646x_mdio_device = {
416         .name           = "davinci_mdio",
417         .id             = 0,
418         .num_resources  = ARRAY_SIZE(dm646x_mdio_resources),
419         .resource       = dm646x_mdio_resources,
420 };
421
422 /*
423  * Device specific mux setup
424  *
425  *      soc     description     mux  mode   mode  mux    dbg
426  *                              reg  offset mask  mode
427  */
428 static const struct mux_config dm646x_pins[] = {
429 #ifdef CONFIG_DAVINCI_MUX
430 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
431
432 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
433
434 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
435
436 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
437
438 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
439
440 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
441
442 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
443
444 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
445
446 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
447
448 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
449
450 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
451
452 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
453
454 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
455
456 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
457 #endif
458 };
459
460 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
461         [IRQ_DM646X_VP_VERTINT0]        = 7,
462         [IRQ_DM646X_VP_VERTINT1]        = 7,
463         [IRQ_DM646X_VP_VERTINT2]        = 7,
464         [IRQ_DM646X_VP_VERTINT3]        = 7,
465         [IRQ_DM646X_VP_ERRINT]          = 7,
466         [IRQ_DM646X_RESERVED_1]         = 7,
467         [IRQ_DM646X_RESERVED_2]         = 7,
468         [IRQ_DM646X_WDINT]              = 7,
469         [IRQ_DM646X_CRGENINT0]          = 7,
470         [IRQ_DM646X_CRGENINT1]          = 7,
471         [IRQ_DM646X_TSIFINT0]           = 7,
472         [IRQ_DM646X_TSIFINT1]           = 7,
473         [IRQ_DM646X_VDCEINT]            = 7,
474         [IRQ_DM646X_USBINT]             = 7,
475         [IRQ_DM646X_USBDMAINT]          = 7,
476         [IRQ_DM646X_PCIINT]             = 7,
477         [IRQ_CCINT0]                    = 7,    /* dma */
478         [IRQ_CCERRINT]                  = 7,    /* dma */
479         [IRQ_TCERRINT0]                 = 7,    /* dma */
480         [IRQ_TCERRINT]                  = 7,    /* dma */
481         [IRQ_DM646X_TCERRINT2]          = 7,
482         [IRQ_DM646X_TCERRINT3]          = 7,
483         [IRQ_DM646X_IDE]                = 7,
484         [IRQ_DM646X_HPIINT]             = 7,
485         [IRQ_DM646X_EMACRXTHINT]        = 7,
486         [IRQ_DM646X_EMACRXINT]          = 7,
487         [IRQ_DM646X_EMACTXINT]          = 7,
488         [IRQ_DM646X_EMACMISCINT]        = 7,
489         [IRQ_DM646X_MCASP0TXINT]        = 7,
490         [IRQ_DM646X_MCASP0RXINT]        = 7,
491         [IRQ_AEMIFINT]                  = 7,
492         [IRQ_DM646X_RESERVED_3]         = 7,
493         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
494         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
495         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
496         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
497         [IRQ_PWMINT0]                   = 7,
498         [IRQ_PWMINT1]                   = 7,
499         [IRQ_DM646X_VLQINT]             = 7,
500         [IRQ_I2C]                       = 7,
501         [IRQ_UARTINT0]                  = 7,
502         [IRQ_UARTINT1]                  = 7,
503         [IRQ_DM646X_UARTINT2]           = 7,
504         [IRQ_DM646X_SPINT0]             = 7,
505         [IRQ_DM646X_SPINT1]             = 7,
506         [IRQ_DM646X_DSP2ARMINT]         = 7,
507         [IRQ_DM646X_RESERVED_4]         = 7,
508         [IRQ_DM646X_PSCINT]             = 7,
509         [IRQ_DM646X_GPIO0]              = 7,
510         [IRQ_DM646X_GPIO1]              = 7,
511         [IRQ_DM646X_GPIO2]              = 7,
512         [IRQ_DM646X_GPIO3]              = 7,
513         [IRQ_DM646X_GPIO4]              = 7,
514         [IRQ_DM646X_GPIO5]              = 7,
515         [IRQ_DM646X_GPIO6]              = 7,
516         [IRQ_DM646X_GPIO7]              = 7,
517         [IRQ_DM646X_GPIOBNK0]           = 7,
518         [IRQ_DM646X_GPIOBNK1]           = 7,
519         [IRQ_DM646X_GPIOBNK2]           = 7,
520         [IRQ_DM646X_DDRINT]             = 7,
521         [IRQ_DM646X_AEMIFINT]           = 7,
522         [IRQ_COMMTX]                    = 7,
523         [IRQ_COMMRX]                    = 7,
524         [IRQ_EMUINT]                    = 7,
525 };
526
527 /*----------------------------------------------------------------------*/
528
529 /* Four Transfer Controllers on DM646x */
530 static const s8
531 dm646x_queue_tc_mapping[][2] = {
532         /* {event queue no, TC no} */
533         {0, 0},
534         {1, 1},
535         {2, 2},
536         {3, 3},
537         {-1, -1},
538 };
539
540 static const s8
541 dm646x_queue_priority_mapping[][2] = {
542         /* {event queue no, Priority} */
543         {0, 4},
544         {1, 0},
545         {2, 5},
546         {3, 1},
547         {-1, -1},
548 };
549
550 static struct edma_soc_info edma_cc0_info = {
551         .n_channel              = 64,
552         .n_region               = 6,    /* 0-1, 4-7 */
553         .n_slot                 = 512,
554         .n_tc                   = 4,
555         .n_cc                   = 1,
556         .queue_tc_mapping       = dm646x_queue_tc_mapping,
557         .queue_priority_mapping = dm646x_queue_priority_mapping,
558 };
559
560 static struct edma_soc_info *dm646x_edma_info[EDMA_MAX_CC] = {
561         &edma_cc0_info,
562 };
563
564 static struct resource edma_resources[] = {
565         {
566                 .name   = "edma_cc0",
567                 .start  = 0x01c00000,
568                 .end    = 0x01c00000 + SZ_64K - 1,
569                 .flags  = IORESOURCE_MEM,
570         },
571         {
572                 .name   = "edma_tc0",
573                 .start  = 0x01c10000,
574                 .end    = 0x01c10000 + SZ_1K - 1,
575                 .flags  = IORESOURCE_MEM,
576         },
577         {
578                 .name   = "edma_tc1",
579                 .start  = 0x01c10400,
580                 .end    = 0x01c10400 + SZ_1K - 1,
581                 .flags  = IORESOURCE_MEM,
582         },
583         {
584                 .name   = "edma_tc2",
585                 .start  = 0x01c10800,
586                 .end    = 0x01c10800 + SZ_1K - 1,
587                 .flags  = IORESOURCE_MEM,
588         },
589         {
590                 .name   = "edma_tc3",
591                 .start  = 0x01c10c00,
592                 .end    = 0x01c10c00 + SZ_1K - 1,
593                 .flags  = IORESOURCE_MEM,
594         },
595         {
596                 .name   = "edma0",
597                 .start  = IRQ_CCINT0,
598                 .flags  = IORESOURCE_IRQ,
599         },
600         {
601                 .name   = "edma0_err",
602                 .start  = IRQ_CCERRINT,
603                 .flags  = IORESOURCE_IRQ,
604         },
605         /* not using TC*_ERR */
606 };
607
608 static struct platform_device dm646x_edma_device = {
609         .name                   = "edma",
610         .id                     = 0,
611         .dev.platform_data      = dm646x_edma_info,
612         .num_resources          = ARRAY_SIZE(edma_resources),
613         .resource               = edma_resources,
614 };
615
616 static struct resource dm646x_mcasp0_resources[] = {
617         {
618                 .name   = "mcasp0",
619                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
620                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
621                 .flags  = IORESOURCE_MEM,
622         },
623         /* first TX, then RX */
624         {
625                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
626                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
627                 .flags  = IORESOURCE_DMA,
628         },
629         {
630                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
631                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
632                 .flags  = IORESOURCE_DMA,
633         },
634 };
635
636 static struct resource dm646x_mcasp1_resources[] = {
637         {
638                 .name   = "mcasp1",
639                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
640                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
641                 .flags  = IORESOURCE_MEM,
642         },
643         /* DIT mode, only TX event */
644         {
645                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
646                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
647                 .flags  = IORESOURCE_DMA,
648         },
649         /* DIT mode, dummy entry */
650         {
651                 .start  = -1,
652                 .end    = -1,
653                 .flags  = IORESOURCE_DMA,
654         },
655 };
656
657 static struct platform_device dm646x_mcasp0_device = {
658         .name           = "davinci-mcasp",
659         .id             = 0,
660         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
661         .resource       = dm646x_mcasp0_resources,
662 };
663
664 static struct platform_device dm646x_mcasp1_device = {
665         .name           = "davinci-mcasp",
666         .id             = 1,
667         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
668         .resource       = dm646x_mcasp1_resources,
669 };
670
671 static struct platform_device dm646x_dit_device = {
672         .name   = "spdif-dit",
673         .id     = -1,
674 };
675
676 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
677
678 static struct resource vpif_resource[] = {
679         {
680                 .start  = DAVINCI_VPIF_BASE,
681                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
682                 .flags  = IORESOURCE_MEM,
683         }
684 };
685
686 static struct platform_device vpif_dev = {
687         .name           = "vpif",
688         .id             = -1,
689         .dev            = {
690                         .dma_mask               = &vpif_dma_mask,
691                         .coherent_dma_mask      = DMA_BIT_MASK(32),
692         },
693         .resource       = vpif_resource,
694         .num_resources  = ARRAY_SIZE(vpif_resource),
695 };
696
697 static struct resource vpif_display_resource[] = {
698         {
699                 .start = IRQ_DM646X_VP_VERTINT2,
700                 .end   = IRQ_DM646X_VP_VERTINT2,
701                 .flags = IORESOURCE_IRQ,
702         },
703         {
704                 .start = IRQ_DM646X_VP_VERTINT3,
705                 .end   = IRQ_DM646X_VP_VERTINT3,
706                 .flags = IORESOURCE_IRQ,
707         },
708 };
709
710 static struct platform_device vpif_display_dev = {
711         .name           = "vpif_display",
712         .id             = -1,
713         .dev            = {
714                         .dma_mask               = &vpif_dma_mask,
715                         .coherent_dma_mask      = DMA_BIT_MASK(32),
716         },
717         .resource       = vpif_display_resource,
718         .num_resources  = ARRAY_SIZE(vpif_display_resource),
719 };
720
721 static struct resource vpif_capture_resource[] = {
722         {
723                 .start = IRQ_DM646X_VP_VERTINT0,
724                 .end   = IRQ_DM646X_VP_VERTINT0,
725                 .flags = IORESOURCE_IRQ,
726         },
727         {
728                 .start = IRQ_DM646X_VP_VERTINT1,
729                 .end   = IRQ_DM646X_VP_VERTINT1,
730                 .flags = IORESOURCE_IRQ,
731         },
732 };
733
734 static struct platform_device vpif_capture_dev = {
735         .name           = "vpif_capture",
736         .id             = -1,
737         .dev            = {
738                         .dma_mask               = &vpif_dma_mask,
739                         .coherent_dma_mask      = DMA_BIT_MASK(32),
740         },
741         .resource       = vpif_capture_resource,
742         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
743 };
744
745 /*----------------------------------------------------------------------*/
746
747 static struct map_desc dm646x_io_desc[] = {
748         {
749                 .virtual        = IO_VIRT,
750                 .pfn            = __phys_to_pfn(IO_PHYS),
751                 .length         = IO_SIZE,
752                 .type           = MT_DEVICE
753         },
754         {
755                 .virtual        = SRAM_VIRT,
756                 .pfn            = __phys_to_pfn(0x00010000),
757                 .length         = SZ_32K,
758                 .type           = MT_MEMORY_NONCACHED,
759         },
760 };
761
762 /* Contents of JTAG ID register used to identify exact cpu type */
763 static struct davinci_id dm646x_ids[] = {
764         {
765                 .variant        = 0x0,
766                 .part_no        = 0xb770,
767                 .manufacturer   = 0x017,
768                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
769                 .name           = "dm6467_rev1.x",
770         },
771         {
772                 .variant        = 0x1,
773                 .part_no        = 0xb770,
774                 .manufacturer   = 0x017,
775                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
776                 .name           = "dm6467_rev3.x",
777         },
778 };
779
780 static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
781
782 /*
783  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
784  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
785  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
786  * T1_TOP: Timer 1, top   :  <unused>
787  */
788 static struct davinci_timer_info dm646x_timer_info = {
789         .timers         = davinci_timer_instance,
790         .clockevent_id  = T0_BOT,
791         .clocksource_id = T0_TOP,
792 };
793
794 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
795         {
796                 .mapbase        = DAVINCI_UART0_BASE,
797                 .irq            = IRQ_UARTINT0,
798                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
799                                   UPF_IOREMAP,
800                 .iotype         = UPIO_MEM32,
801                 .regshift       = 2,
802         },
803         {
804                 .mapbase        = DAVINCI_UART1_BASE,
805                 .irq            = IRQ_UARTINT1,
806                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
807                                   UPF_IOREMAP,
808                 .iotype         = UPIO_MEM32,
809                 .regshift       = 2,
810         },
811         {
812                 .mapbase        = DAVINCI_UART2_BASE,
813                 .irq            = IRQ_DM646X_UARTINT2,
814                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
815                                   UPF_IOREMAP,
816                 .iotype         = UPIO_MEM32,
817                 .regshift       = 2,
818         },
819         {
820                 .flags          = 0
821         },
822 };
823
824 static struct platform_device dm646x_serial_device = {
825         .name                   = "serial8250",
826         .id                     = PLAT8250_DEV_PLATFORM,
827         .dev                    = {
828                 .platform_data  = dm646x_serial_platform_data,
829         },
830 };
831
832 static struct davinci_soc_info davinci_soc_info_dm646x = {
833         .io_desc                = dm646x_io_desc,
834         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
835         .jtag_id_reg            = 0x01c40028,
836         .ids                    = dm646x_ids,
837         .ids_num                = ARRAY_SIZE(dm646x_ids),
838         .cpu_clks               = dm646x_clks,
839         .psc_bases              = dm646x_psc_bases,
840         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
841         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
842         .pinmux_pins            = dm646x_pins,
843         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
844         .intc_base              = DAVINCI_ARM_INTC_BASE,
845         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
846         .intc_irq_prios         = dm646x_default_priorities,
847         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
848         .timer_info             = &dm646x_timer_info,
849         .gpio_type              = GPIO_TYPE_DAVINCI,
850         .gpio_base              = DAVINCI_GPIO_BASE,
851         .gpio_num               = 43, /* Only 33 usable */
852         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
853         .serial_dev             = &dm646x_serial_device,
854         .emac_pdata             = &dm646x_emac_pdata,
855         .sram_dma               = 0x10010000,
856         .sram_len               = SZ_32K,
857         .reset_device           = &davinci_wdt_device,
858 };
859
860 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
861 {
862         dm646x_mcasp0_device.dev.platform_data = pdata;
863         platform_device_register(&dm646x_mcasp0_device);
864 }
865
866 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
867 {
868         dm646x_mcasp1_device.dev.platform_data = pdata;
869         platform_device_register(&dm646x_mcasp1_device);
870         platform_device_register(&dm646x_dit_device);
871 }
872
873 void dm646x_setup_vpif(struct vpif_display_config *display_config,
874                        struct vpif_capture_config *capture_config)
875 {
876         unsigned int value;
877         void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
878
879         value = __raw_readl(base + VSCLKDIS_OFFSET);
880         value &= ~VSCLKDIS_MASK;
881         __raw_writel(value, base + VSCLKDIS_OFFSET);
882
883         value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
884         value &= ~VDD3P3V_VID_MASK;
885         __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
886
887         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
888         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
889         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
890         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
891
892         vpif_display_dev.dev.platform_data = display_config;
893         vpif_capture_dev.dev.platform_data = capture_config;
894         platform_device_register(&vpif_dev);
895         platform_device_register(&vpif_display_dev);
896         platform_device_register(&vpif_capture_dev);
897 }
898
899 int __init dm646x_init_edma(struct edma_rsv_info *rsv)
900 {
901         edma_cc0_info.rsv = rsv;
902
903         return platform_device_register(&dm646x_edma_device);
904 }
905
906 void __init dm646x_init(void)
907 {
908         davinci_common_init(&davinci_soc_info_dm646x);
909 }
910
911 static int __init dm646x_init_devices(void)
912 {
913         if (!cpu_is_davinci_dm646x())
914                 return 0;
915
916         platform_device_register(&dm646x_mdio_device);
917         platform_device_register(&dm646x_emac_device);
918         clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
919                       NULL, &dm646x_emac_device.dev);
920
921         return 0;
922 }
923 postcore_initcall(dm646x_init_devices);