Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / arm / mach-davinci / dm365.c
1 /*
2  * TI DaVinci DM365 chip specific setup
3  *
4  * Copyright (C) 2009 Texas Instruments
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation version 2.
9  *
10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11  * kind, whether express or implied; without even the implied warranty
12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/clk.h>
18 #include <linux/serial_8250.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/gpio.h>
22
23 #include <asm/mach/map.h>
24
25 #include <mach/dm365.h>
26 #include <mach/clock.h>
27 #include <mach/cputype.h>
28 #include <mach/edma.h>
29 #include <mach/psc.h>
30 #include <mach/mux.h>
31 #include <mach/irqs.h>
32 #include <mach/time.h>
33 #include <mach/serial.h>
34 #include <mach/common.h>
35
36 #include "clock.h"
37 #include "mux.h"
38
39 #define DM365_REF_FREQ          24000000        /* 24 MHz on the DM365 EVM */
40
41 static struct pll_data pll1_data = {
42         .num            = 1,
43         .phys_base      = DAVINCI_PLL1_BASE,
44         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
45 };
46
47 static struct pll_data pll2_data = {
48         .num            = 2,
49         .phys_base      = DAVINCI_PLL2_BASE,
50         .flags          = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
51 };
52
53 static struct clk ref_clk = {
54         .name           = "ref_clk",
55         .rate           = DM365_REF_FREQ,
56 };
57
58 static struct clk pll1_clk = {
59         .name           = "pll1",
60         .parent         = &ref_clk,
61         .flags          = CLK_PLL,
62         .pll_data       = &pll1_data,
63 };
64
65 static struct clk pll1_aux_clk = {
66         .name           = "pll1_aux_clk",
67         .parent         = &pll1_clk,
68         .flags          = CLK_PLL | PRE_PLL,
69 };
70
71 static struct clk pll1_sysclkbp = {
72         .name           = "pll1_sysclkbp",
73         .parent         = &pll1_clk,
74         .flags          = CLK_PLL | PRE_PLL,
75         .div_reg        = BPDIV
76 };
77
78 static struct clk clkout0_clk = {
79         .name           = "clkout0",
80         .parent         = &pll1_clk,
81         .flags          = CLK_PLL | PRE_PLL,
82 };
83
84 static struct clk pll1_sysclk1 = {
85         .name           = "pll1_sysclk1",
86         .parent         = &pll1_clk,
87         .flags          = CLK_PLL,
88         .div_reg        = PLLDIV1,
89 };
90
91 static struct clk pll1_sysclk2 = {
92         .name           = "pll1_sysclk2",
93         .parent         = &pll1_clk,
94         .flags          = CLK_PLL,
95         .div_reg        = PLLDIV2,
96 };
97
98 static struct clk pll1_sysclk3 = {
99         .name           = "pll1_sysclk3",
100         .parent         = &pll1_clk,
101         .flags          = CLK_PLL,
102         .div_reg        = PLLDIV3,
103 };
104
105 static struct clk pll1_sysclk4 = {
106         .name           = "pll1_sysclk4",
107         .parent         = &pll1_clk,
108         .flags          = CLK_PLL,
109         .div_reg        = PLLDIV4,
110 };
111
112 static struct clk pll1_sysclk5 = {
113         .name           = "pll1_sysclk5",
114         .parent         = &pll1_clk,
115         .flags          = CLK_PLL,
116         .div_reg        = PLLDIV5,
117 };
118
119 static struct clk pll1_sysclk6 = {
120         .name           = "pll1_sysclk6",
121         .parent         = &pll1_clk,
122         .flags          = CLK_PLL,
123         .div_reg        = PLLDIV6,
124 };
125
126 static struct clk pll1_sysclk7 = {
127         .name           = "pll1_sysclk7",
128         .parent         = &pll1_clk,
129         .flags          = CLK_PLL,
130         .div_reg        = PLLDIV7,
131 };
132
133 static struct clk pll1_sysclk8 = {
134         .name           = "pll1_sysclk8",
135         .parent         = &pll1_clk,
136         .flags          = CLK_PLL,
137         .div_reg        = PLLDIV8,
138 };
139
140 static struct clk pll1_sysclk9 = {
141         .name           = "pll1_sysclk9",
142         .parent         = &pll1_clk,
143         .flags          = CLK_PLL,
144         .div_reg        = PLLDIV9,
145 };
146
147 static struct clk pll2_clk = {
148         .name           = "pll2",
149         .parent         = &ref_clk,
150         .flags          = CLK_PLL,
151         .pll_data       = &pll2_data,
152 };
153
154 static struct clk pll2_aux_clk = {
155         .name           = "pll2_aux_clk",
156         .parent         = &pll2_clk,
157         .flags          = CLK_PLL | PRE_PLL,
158 };
159
160 static struct clk clkout1_clk = {
161         .name           = "clkout1",
162         .parent         = &pll2_clk,
163         .flags          = CLK_PLL | PRE_PLL,
164 };
165
166 static struct clk pll2_sysclk1 = {
167         .name           = "pll2_sysclk1",
168         .parent         = &pll2_clk,
169         .flags          = CLK_PLL,
170         .div_reg        = PLLDIV1,
171 };
172
173 static struct clk pll2_sysclk2 = {
174         .name           = "pll2_sysclk2",
175         .parent         = &pll2_clk,
176         .flags          = CLK_PLL,
177         .div_reg        = PLLDIV2,
178 };
179
180 static struct clk pll2_sysclk3 = {
181         .name           = "pll2_sysclk3",
182         .parent         = &pll2_clk,
183         .flags          = CLK_PLL,
184         .div_reg        = PLLDIV3,
185 };
186
187 static struct clk pll2_sysclk4 = {
188         .name           = "pll2_sysclk4",
189         .parent         = &pll2_clk,
190         .flags          = CLK_PLL,
191         .div_reg        = PLLDIV4,
192 };
193
194 static struct clk pll2_sysclk5 = {
195         .name           = "pll2_sysclk5",
196         .parent         = &pll2_clk,
197         .flags          = CLK_PLL,
198         .div_reg        = PLLDIV5,
199 };
200
201 static struct clk pll2_sysclk6 = {
202         .name           = "pll2_sysclk6",
203         .parent         = &pll2_clk,
204         .flags          = CLK_PLL,
205         .div_reg        = PLLDIV6,
206 };
207
208 static struct clk pll2_sysclk7 = {
209         .name           = "pll2_sysclk7",
210         .parent         = &pll2_clk,
211         .flags          = CLK_PLL,
212         .div_reg        = PLLDIV7,
213 };
214
215 static struct clk pll2_sysclk8 = {
216         .name           = "pll2_sysclk8",
217         .parent         = &pll2_clk,
218         .flags          = CLK_PLL,
219         .div_reg        = PLLDIV8,
220 };
221
222 static struct clk pll2_sysclk9 = {
223         .name           = "pll2_sysclk9",
224         .parent         = &pll2_clk,
225         .flags          = CLK_PLL,
226         .div_reg        = PLLDIV9,
227 };
228
229 static struct clk vpss_dac_clk = {
230         .name           = "vpss_dac",
231         .parent         = &pll1_sysclk3,
232         .lpsc           = DM365_LPSC_DAC_CLK,
233 };
234
235 static struct clk vpss_master_clk = {
236         .name           = "vpss_master",
237         .parent         = &pll1_sysclk5,
238         .lpsc           = DM365_LPSC_VPSSMSTR,
239         .flags          = CLK_PSC,
240 };
241
242 static struct clk arm_clk = {
243         .name           = "arm_clk",
244         .parent         = &pll2_sysclk2,
245         .lpsc           = DAVINCI_LPSC_ARM,
246         .flags          = ALWAYS_ENABLED,
247 };
248
249 static struct clk uart0_clk = {
250         .name           = "uart0",
251         .parent         = &pll1_aux_clk,
252         .lpsc           = DAVINCI_LPSC_UART0,
253 };
254
255 static struct clk uart1_clk = {
256         .name           = "uart1",
257         .parent         = &pll1_sysclk4,
258         .lpsc           = DAVINCI_LPSC_UART1,
259 };
260
261 static struct clk i2c_clk = {
262         .name           = "i2c",
263         .parent         = &pll1_aux_clk,
264         .lpsc           = DAVINCI_LPSC_I2C,
265 };
266
267 static struct clk mmcsd0_clk = {
268         .name           = "mmcsd0",
269         .parent         = &pll1_sysclk8,
270         .lpsc           = DAVINCI_LPSC_MMC_SD,
271 };
272
273 static struct clk mmcsd1_clk = {
274         .name           = "mmcsd1",
275         .parent         = &pll1_sysclk4,
276         .lpsc           = DM365_LPSC_MMC_SD1,
277 };
278
279 static struct clk spi0_clk = {
280         .name           = "spi0",
281         .parent         = &pll1_sysclk4,
282         .lpsc           = DAVINCI_LPSC_SPI,
283 };
284
285 static struct clk spi1_clk = {
286         .name           = "spi1",
287         .parent         = &pll1_sysclk4,
288         .lpsc           = DM365_LPSC_SPI1,
289 };
290
291 static struct clk spi2_clk = {
292         .name           = "spi2",
293         .parent         = &pll1_sysclk4,
294         .lpsc           = DM365_LPSC_SPI2,
295 };
296
297 static struct clk spi3_clk = {
298         .name           = "spi3",
299         .parent         = &pll1_sysclk4,
300         .lpsc           = DM365_LPSC_SPI3,
301 };
302
303 static struct clk spi4_clk = {
304         .name           = "spi4",
305         .parent         = &pll1_aux_clk,
306         .lpsc           = DM365_LPSC_SPI4,
307 };
308
309 static struct clk gpio_clk = {
310         .name           = "gpio",
311         .parent         = &pll1_sysclk4,
312         .lpsc           = DAVINCI_LPSC_GPIO,
313 };
314
315 static struct clk aemif_clk = {
316         .name           = "aemif",
317         .parent         = &pll1_sysclk4,
318         .lpsc           = DAVINCI_LPSC_AEMIF,
319 };
320
321 static struct clk pwm0_clk = {
322         .name           = "pwm0",
323         .parent         = &pll1_aux_clk,
324         .lpsc           = DAVINCI_LPSC_PWM0,
325 };
326
327 static struct clk pwm1_clk = {
328         .name           = "pwm1",
329         .parent         = &pll1_aux_clk,
330         .lpsc           = DAVINCI_LPSC_PWM1,
331 };
332
333 static struct clk pwm2_clk = {
334         .name           = "pwm2",
335         .parent         = &pll1_aux_clk,
336         .lpsc           = DAVINCI_LPSC_PWM2,
337 };
338
339 static struct clk pwm3_clk = {
340         .name           = "pwm3",
341         .parent         = &ref_clk,
342         .lpsc           = DM365_LPSC_PWM3,
343 };
344
345 static struct clk timer0_clk = {
346         .name           = "timer0",
347         .parent         = &pll1_aux_clk,
348         .lpsc           = DAVINCI_LPSC_TIMER0,
349 };
350
351 static struct clk timer1_clk = {
352         .name           = "timer1",
353         .parent         = &pll1_aux_clk,
354         .lpsc           = DAVINCI_LPSC_TIMER1,
355 };
356
357 static struct clk timer2_clk = {
358         .name           = "timer2",
359         .parent         = &pll1_aux_clk,
360         .lpsc           = DAVINCI_LPSC_TIMER2,
361         .usecount       = 1,
362 };
363
364 static struct clk timer3_clk = {
365         .name           = "timer3",
366         .parent         = &pll1_aux_clk,
367         .lpsc           = DM365_LPSC_TIMER3,
368 };
369
370 static struct clk usb_clk = {
371         .name           = "usb",
372         .parent         = &pll2_sysclk1,
373         .lpsc           = DAVINCI_LPSC_USB,
374 };
375
376 static struct clk emac_clk = {
377         .name           = "emac",
378         .parent         = &pll1_sysclk4,
379         .lpsc           = DM365_LPSC_EMAC,
380 };
381
382 static struct clk voicecodec_clk = {
383         .name           = "voice_codec",
384         .parent         = &pll2_sysclk4,
385         .lpsc           = DM365_LPSC_VOICE_CODEC,
386 };
387
388 static struct clk asp0_clk = {
389         .name           = "asp0",
390         .parent         = &pll1_sysclk4,
391         .lpsc           = DM365_LPSC_McBSP1,
392 };
393
394 static struct clk rto_clk = {
395         .name           = "rto",
396         .parent         = &pll1_sysclk4,
397         .lpsc           = DM365_LPSC_RTO,
398 };
399
400 static struct clk mjcp_clk = {
401         .name           = "mjcp",
402         .parent         = &pll1_sysclk3,
403         .lpsc           = DM365_LPSC_MJCP,
404 };
405
406 static struct davinci_clk dm365_clks[] = {
407         CLK(NULL, "ref", &ref_clk),
408         CLK(NULL, "pll1", &pll1_clk),
409         CLK(NULL, "pll1_aux", &pll1_aux_clk),
410         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
411         CLK(NULL, "clkout0", &clkout0_clk),
412         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
413         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
414         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
415         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
416         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
417         CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
418         CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
419         CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
420         CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
421         CLK(NULL, "pll2", &pll2_clk),
422         CLK(NULL, "pll2_aux", &pll2_aux_clk),
423         CLK(NULL, "clkout1", &clkout1_clk),
424         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
425         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
426         CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
427         CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
428         CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
429         CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
430         CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
431         CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
432         CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
433         CLK(NULL, "vpss_dac", &vpss_dac_clk),
434         CLK(NULL, "vpss_master", &vpss_master_clk),
435         CLK(NULL, "arm", &arm_clk),
436         CLK(NULL, "uart0", &uart0_clk),
437         CLK(NULL, "uart1", &uart1_clk),
438         CLK("i2c_davinci.1", NULL, &i2c_clk),
439         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
440         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
441         CLK("spi_davinci.0", NULL, &spi0_clk),
442         CLK("spi_davinci.1", NULL, &spi1_clk),
443         CLK("spi_davinci.2", NULL, &spi2_clk),
444         CLK("spi_davinci.3", NULL, &spi3_clk),
445         CLK("spi_davinci.4", NULL, &spi4_clk),
446         CLK(NULL, "gpio", &gpio_clk),
447         CLK(NULL, "aemif", &aemif_clk),
448         CLK(NULL, "pwm0", &pwm0_clk),
449         CLK(NULL, "pwm1", &pwm1_clk),
450         CLK(NULL, "pwm2", &pwm2_clk),
451         CLK(NULL, "pwm3", &pwm3_clk),
452         CLK(NULL, "timer0", &timer0_clk),
453         CLK(NULL, "timer1", &timer1_clk),
454         CLK("watchdog", NULL, &timer2_clk),
455         CLK(NULL, "timer3", &timer3_clk),
456         CLK(NULL, "usb", &usb_clk),
457         CLK("davinci_emac.1", NULL, &emac_clk),
458         CLK("voice_codec", NULL, &voicecodec_clk),
459         CLK("soc-audio.0", NULL, &asp0_clk),
460         CLK(NULL, "rto", &rto_clk),
461         CLK(NULL, "mjcp", &mjcp_clk),
462         CLK(NULL, NULL, NULL),
463 };
464
465 /*----------------------------------------------------------------------*/
466
467 #define PINMUX0         0x00
468 #define PINMUX1         0x04
469 #define PINMUX2         0x08
470 #define PINMUX3         0x0c
471 #define PINMUX4         0x10
472 #define INTMUX          0x18
473 #define EVTMUX          0x1c
474
475
476 static const struct mux_config dm365_pins[] = {
477 #ifdef CONFIG_DAVINCI_MUX
478 MUX_CFG(DM365,  MMCSD0,         0,   24,     1,   0,     false)
479
480 MUX_CFG(DM365,  SD1_CLK,        0,   16,    3,    1,     false)
481 MUX_CFG(DM365,  SD1_CMD,        4,   30,    3,    1,     false)
482 MUX_CFG(DM365,  SD1_DATA3,      4,   28,    3,    1,     false)
483 MUX_CFG(DM365,  SD1_DATA2,      4,   26,    3,    1,     false)
484 MUX_CFG(DM365,  SD1_DATA1,      4,   24,    3,    1,     false)
485 MUX_CFG(DM365,  SD1_DATA0,      4,   22,    3,    1,     false)
486
487 MUX_CFG(DM365,  I2C_SDA,        3,   23,    3,    2,     false)
488 MUX_CFG(DM365,  I2C_SCL,        3,   21,    3,    2,     false)
489
490 MUX_CFG(DM365,  AEMIF_AR,       2,   0,     3,    1,     false)
491 MUX_CFG(DM365,  AEMIF_A3,       2,   2,     3,    1,     false)
492 MUX_CFG(DM365,  AEMIF_A7,       2,   4,     3,    1,     false)
493 MUX_CFG(DM365,  AEMIF_D15_8,    2,   6,     1,    1,     false)
494 MUX_CFG(DM365,  AEMIF_CE0,      2,   7,     1,    0,     false)
495
496 MUX_CFG(DM365,  MCBSP0_BDX,     0,   23,    1,    1,     false)
497 MUX_CFG(DM365,  MCBSP0_X,       0,   22,    1,    1,     false)
498 MUX_CFG(DM365,  MCBSP0_BFSX,    0,   21,    1,    1,     false)
499 MUX_CFG(DM365,  MCBSP0_BDR,     0,   20,    1,    1,     false)
500 MUX_CFG(DM365,  MCBSP0_R,       0,   19,    1,    1,     false)
501 MUX_CFG(DM365,  MCBSP0_BFSR,    0,   18,    1,    1,     false)
502
503 MUX_CFG(DM365,  SPI0_SCLK,      3,   28,    1,    1,     false)
504 MUX_CFG(DM365,  SPI0_SDI,       3,   26,    3,    1,     false)
505 MUX_CFG(DM365,  SPI0_SDO,       3,   25,    1,    1,     false)
506 MUX_CFG(DM365,  SPI0_SDENA0,    3,   29,    3,    1,     false)
507 MUX_CFG(DM365,  SPI0_SDENA1,    3,   26,    3,    2,     false)
508
509 MUX_CFG(DM365,  UART0_RXD,      3,   20,    1,    1,     false)
510 MUX_CFG(DM365,  UART0_TXD,      3,   19,    1,    1,     false)
511 MUX_CFG(DM365,  UART1_RXD,      3,   17,    3,    2,     false)
512 MUX_CFG(DM365,  UART1_TXD,      3,   15,    3,    2,     false)
513 MUX_CFG(DM365,  UART1_RTS,      3,   23,    3,    1,     false)
514 MUX_CFG(DM365,  UART1_CTS,      3,   21,    3,    1,     false)
515
516 MUX_CFG(DM365,  EMAC_TX_EN,     3,   17,    3,    1,     false)
517 MUX_CFG(DM365,  EMAC_TX_CLK,    3,   15,    3,    1,     false)
518 MUX_CFG(DM365,  EMAC_COL,       3,   14,    1,    1,     false)
519 MUX_CFG(DM365,  EMAC_TXD3,      3,   13,    1,    1,     false)
520 MUX_CFG(DM365,  EMAC_TXD2,      3,   12,    1,    1,     false)
521 MUX_CFG(DM365,  EMAC_TXD1,      3,   11,    1,    1,     false)
522 MUX_CFG(DM365,  EMAC_TXD0,      3,   10,    1,    1,     false)
523 MUX_CFG(DM365,  EMAC_RXD3,      3,   9,     1,    1,     false)
524 MUX_CFG(DM365,  EMAC_RXD2,      3,   8,     1,    1,     false)
525 MUX_CFG(DM365,  EMAC_RXD1,      3,   7,     1,    1,     false)
526 MUX_CFG(DM365,  EMAC_RXD0,      3,   6,     1,    1,     false)
527 MUX_CFG(DM365,  EMAC_RX_CLK,    3,   5,     1,    1,     false)
528 MUX_CFG(DM365,  EMAC_RX_DV,     3,   4,     1,    1,     false)
529 MUX_CFG(DM365,  EMAC_RX_ER,     3,   3,     1,    1,     false)
530 MUX_CFG(DM365,  EMAC_CRS,       3,   2,     1,    1,     false)
531 MUX_CFG(DM365,  EMAC_MDIO,      3,   1,     1,    1,     false)
532 MUX_CFG(DM365,  EMAC_MDCLK,     3,   0,     1,    1,     false)
533
534 MUX_CFG(DM365,  KEYPAD,         2,   0,     0x3f, 0x3f,  false)
535
536 MUX_CFG(DM365,  PWM0,           1,   0,     3,    2,     false)
537 MUX_CFG(DM365,  PWM0_G23,       3,   26,    3,    3,     false)
538 MUX_CFG(DM365,  PWM1,           1,   2,     3,    2,     false)
539 MUX_CFG(DM365,  PWM1_G25,       3,   29,    3,    2,     false)
540 MUX_CFG(DM365,  PWM2_G87,       1,   10,    3,    2,     false)
541 MUX_CFG(DM365,  PWM2_G88,       1,   8,     3,    2,     false)
542 MUX_CFG(DM365,  PWM2_G89,       1,   6,     3,    2,     false)
543 MUX_CFG(DM365,  PWM2_G90,       1,   4,     3,    2,     false)
544 MUX_CFG(DM365,  PWM3_G80,       1,   20,    3,    3,     false)
545 MUX_CFG(DM365,  PWM3_G81,       1,   18,    3,    3,     false)
546 MUX_CFG(DM365,  PWM3_G85,       1,   14,    3,    2,     false)
547 MUX_CFG(DM365,  PWM3_G86,       1,   12,    3,    2,     false)
548
549 MUX_CFG(DM365,  SPI1_SCLK,      4,   2,     3,    1,     false)
550 MUX_CFG(DM365,  SPI1_SDI,       3,   31,    1,    1,     false)
551 MUX_CFG(DM365,  SPI1_SDO,       4,   0,     3,    1,     false)
552 MUX_CFG(DM365,  SPI1_SDENA0,    4,   4,     3,    1,     false)
553 MUX_CFG(DM365,  SPI1_SDENA1,    4,   0,     3,    2,     false)
554
555 MUX_CFG(DM365,  SPI2_SCLK,      4,   10,    3,    1,     false)
556 MUX_CFG(DM365,  SPI2_SDI,       4,   6,     3,    1,     false)
557 MUX_CFG(DM365,  SPI2_SDO,       4,   8,     3,    1,     false)
558 MUX_CFG(DM365,  SPI2_SDENA0,    4,   12,    3,    1,     false)
559 MUX_CFG(DM365,  SPI2_SDENA1,    4,   8,     3,    2,     false)
560
561 MUX_CFG(DM365,  SPI3_SCLK,      0,   0,     3,    2,     false)
562 MUX_CFG(DM365,  SPI3_SDI,       0,   2,     3,    2,     false)
563 MUX_CFG(DM365,  SPI3_SDO,       0,   6,     3,    2,     false)
564 MUX_CFG(DM365,  SPI3_SDENA0,    0,   4,     3,    2,     false)
565 MUX_CFG(DM365,  SPI3_SDENA1,    0,   6,     3,    3,     false)
566
567 MUX_CFG(DM365,  SPI4_SCLK,      4,   18,    3,    1,     false)
568 MUX_CFG(DM365,  SPI4_SDI,       4,   14,    3,    1,     false)
569 MUX_CFG(DM365,  SPI4_SDO,       4,   16,    3,    1,     false)
570 MUX_CFG(DM365,  SPI4_SDENA0,    4,   20,    3,    1,     false)
571 MUX_CFG(DM365,  SPI4_SDENA1,    4,   16,    3,    2,     false)
572
573 MUX_CFG(DM365,  GPIO20,         3,   21,    3,    0,     false)
574 MUX_CFG(DM365,  GPIO33,         4,   12,    3,    0,     false)
575 MUX_CFG(DM365,  GPIO40,         4,   26,    3,    0,     false)
576
577 MUX_CFG(DM365,  VOUT_FIELD,     1,   18,    3,    1,     false)
578 MUX_CFG(DM365,  VOUT_FIELD_G81, 1,   18,    3,    0,     false)
579 MUX_CFG(DM365,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
580 MUX_CFG(DM365,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
581 MUX_CFG(DM365,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
582 MUX_CFG(DM365,  VIN_CAM_WEN,    0,   14,    3,    0,     false)
583 MUX_CFG(DM365,  VIN_CAM_VD,     0,   13,    1,    0,     false)
584 MUX_CFG(DM365,  VIN_CAM_HD,     0,   12,    1,    0,     false)
585 MUX_CFG(DM365,  VIN_YIN4_7_EN,  0,   0,     0xff, 0,     false)
586 MUX_CFG(DM365,  VIN_YIN0_3_EN,  0,   8,     0xf,  0,     false)
587
588 INT_CFG(DM365,  INT_EDMA_CC,         2,     1,    1,     false)
589 INT_CFG(DM365,  INT_EDMA_TC0_ERR,    3,     1,    1,     false)
590 INT_CFG(DM365,  INT_EDMA_TC1_ERR,    4,     1,    1,     false)
591 INT_CFG(DM365,  INT_EDMA_TC2_ERR,    22,    1,    1,     false)
592 INT_CFG(DM365,  INT_EDMA_TC3_ERR,    23,    1,    1,     false)
593 INT_CFG(DM365,  INT_PRTCSS,          10,    1,    1,     false)
594 INT_CFG(DM365,  INT_EMAC_RXTHRESH,   14,    1,    1,     false)
595 INT_CFG(DM365,  INT_EMAC_RXPULSE,    15,    1,    1,     false)
596 INT_CFG(DM365,  INT_EMAC_TXPULSE,    16,    1,    1,     false)
597 INT_CFG(DM365,  INT_EMAC_MISCPULSE,  17,    1,    1,     false)
598 INT_CFG(DM365,  INT_IMX0_ENABLE,     0,     1,    0,     false)
599 INT_CFG(DM365,  INT_IMX0_DISABLE,    0,     1,    1,     false)
600 INT_CFG(DM365,  INT_HDVICP_ENABLE,   0,     1,    1,     false)
601 INT_CFG(DM365,  INT_HDVICP_DISABLE,  0,     1,    0,     false)
602 INT_CFG(DM365,  INT_IMX1_ENABLE,     24,    1,    1,     false)
603 INT_CFG(DM365,  INT_IMX1_DISABLE,    24,    1,    0,     false)
604 INT_CFG(DM365,  INT_NSF_ENABLE,      25,    1,    1,     false)
605 INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
606 #endif
607 };
608
609 static struct emac_platform_data dm365_emac_pdata = {
610         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
611         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
612         .ctrl_ram_offset        = DM365_EMAC_CNTRL_RAM_OFFSET,
613         .mdio_reg_offset        = DM365_EMAC_MDIO_OFFSET,
614         .ctrl_ram_size          = DM365_EMAC_CNTRL_RAM_SIZE,
615         .version                = EMAC_VERSION_2,
616 };
617
618 static struct resource dm365_emac_resources[] = {
619         {
620                 .start  = DM365_EMAC_BASE,
621                 .end    = DM365_EMAC_BASE + 0x47ff,
622                 .flags  = IORESOURCE_MEM,
623         },
624         {
625                 .start  = IRQ_DM365_EMAC_RXTHRESH,
626                 .end    = IRQ_DM365_EMAC_RXTHRESH,
627                 .flags  = IORESOURCE_IRQ,
628         },
629         {
630                 .start  = IRQ_DM365_EMAC_RXPULSE,
631                 .end    = IRQ_DM365_EMAC_RXPULSE,
632                 .flags  = IORESOURCE_IRQ,
633         },
634         {
635                 .start  = IRQ_DM365_EMAC_TXPULSE,
636                 .end    = IRQ_DM365_EMAC_TXPULSE,
637                 .flags  = IORESOURCE_IRQ,
638         },
639         {
640                 .start  = IRQ_DM365_EMAC_MISCPULSE,
641                 .end    = IRQ_DM365_EMAC_MISCPULSE,
642                 .flags  = IORESOURCE_IRQ,
643         },
644 };
645
646 static struct platform_device dm365_emac_device = {
647         .name           = "davinci_emac",
648         .id             = 1,
649         .dev = {
650                 .platform_data  = &dm365_emac_pdata,
651         },
652         .num_resources  = ARRAY_SIZE(dm365_emac_resources),
653         .resource       = dm365_emac_resources,
654 };
655
656 static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
657         [IRQ_VDINT0]                    = 2,
658         [IRQ_VDINT1]                    = 6,
659         [IRQ_VDINT2]                    = 6,
660         [IRQ_HISTINT]                   = 6,
661         [IRQ_H3AINT]                    = 6,
662         [IRQ_PRVUINT]                   = 6,
663         [IRQ_RSZINT]                    = 6,
664         [IRQ_DM365_INSFINT]             = 7,
665         [IRQ_VENCINT]                   = 6,
666         [IRQ_ASQINT]                    = 6,
667         [IRQ_IMXINT]                    = 6,
668         [IRQ_DM365_IMCOPINT]            = 4,
669         [IRQ_USBINT]                    = 4,
670         [IRQ_DM365_RTOINT]              = 7,
671         [IRQ_DM365_TINT5]               = 7,
672         [IRQ_DM365_TINT6]               = 5,
673         [IRQ_CCINT0]                    = 5,
674         [IRQ_CCERRINT]                  = 5,
675         [IRQ_TCERRINT0]                 = 5,
676         [IRQ_TCERRINT]                  = 7,
677         [IRQ_PSCIN]                     = 4,
678         [IRQ_DM365_SPINT2_1]            = 7,
679         [IRQ_DM365_TINT7]               = 7,
680         [IRQ_DM365_SDIOINT0]            = 7,
681         [IRQ_MBXINT]                    = 7,
682         [IRQ_MBRINT]                    = 7,
683         [IRQ_MMCINT]                    = 7,
684         [IRQ_DM365_MMCINT1]             = 7,
685         [IRQ_DM365_PWMINT3]             = 7,
686         [IRQ_DDRINT]                    = 4,
687         [IRQ_AEMIFINT]                  = 2,
688         [IRQ_DM365_SDIOINT1]            = 2,
689         [IRQ_TINT0_TINT12]              = 7,
690         [IRQ_TINT0_TINT34]              = 7,
691         [IRQ_TINT1_TINT12]              = 7,
692         [IRQ_TINT1_TINT34]              = 7,
693         [IRQ_PWMINT0]                   = 7,
694         [IRQ_PWMINT1]                   = 3,
695         [IRQ_PWMINT2]                   = 3,
696         [IRQ_I2C]                       = 3,
697         [IRQ_UARTINT0]                  = 3,
698         [IRQ_UARTINT1]                  = 3,
699         [IRQ_DM365_SPIINT0_0]           = 3,
700         [IRQ_DM365_SPIINT3_0]           = 3,
701         [IRQ_DM365_GPIO0]               = 3,
702         [IRQ_DM365_GPIO1]               = 7,
703         [IRQ_DM365_GPIO2]               = 4,
704         [IRQ_DM365_GPIO3]               = 4,
705         [IRQ_DM365_GPIO4]               = 7,
706         [IRQ_DM365_GPIO5]               = 7,
707         [IRQ_DM365_GPIO6]               = 7,
708         [IRQ_DM365_GPIO7]               = 7,
709         [IRQ_DM365_EMAC_RXTHRESH]       = 7,
710         [IRQ_DM365_EMAC_RXPULSE]        = 7,
711         [IRQ_DM365_EMAC_TXPULSE]        = 7,
712         [IRQ_DM365_EMAC_MISCPULSE]      = 7,
713         [IRQ_DM365_GPIO12]              = 7,
714         [IRQ_DM365_GPIO13]              = 7,
715         [IRQ_DM365_GPIO14]              = 7,
716         [IRQ_DM365_GPIO15]              = 7,
717         [IRQ_DM365_KEYINT]              = 7,
718         [IRQ_DM365_TCERRINT2]           = 7,
719         [IRQ_DM365_TCERRINT3]           = 7,
720         [IRQ_DM365_EMUINT]              = 7,
721 };
722
723 /* Four Transfer Controllers on DM365 */
724 static const s8
725 dm365_queue_tc_mapping[][2] = {
726         /* {event queue no, TC no} */
727         {0, 0},
728         {1, 1},
729         {2, 2},
730         {3, 3},
731         {-1, -1},
732 };
733
734 static const s8
735 dm365_queue_priority_mapping[][2] = {
736         /* {event queue no, Priority} */
737         {0, 7},
738         {1, 7},
739         {2, 7},
740         {3, 0},
741         {-1, -1},
742 };
743
744 static struct edma_soc_info dm365_edma_info[] = {
745         {
746                 .n_channel              = 64,
747                 .n_region               = 4,
748                 .n_slot                 = 256,
749                 .n_tc                   = 4,
750                 .n_cc                   = 1,
751                 .queue_tc_mapping       = dm365_queue_tc_mapping,
752                 .queue_priority_mapping = dm365_queue_priority_mapping,
753                 .default_queue          = EVENTQ_2,
754         },
755 };
756
757 static struct resource edma_resources[] = {
758         {
759                 .name   = "edma_cc0",
760                 .start  = 0x01c00000,
761                 .end    = 0x01c00000 + SZ_64K - 1,
762                 .flags  = IORESOURCE_MEM,
763         },
764         {
765                 .name   = "edma_tc0",
766                 .start  = 0x01c10000,
767                 .end    = 0x01c10000 + SZ_1K - 1,
768                 .flags  = IORESOURCE_MEM,
769         },
770         {
771                 .name   = "edma_tc1",
772                 .start  = 0x01c10400,
773                 .end    = 0x01c10400 + SZ_1K - 1,
774                 .flags  = IORESOURCE_MEM,
775         },
776         {
777                 .name   = "edma_tc2",
778                 .start  = 0x01c10800,
779                 .end    = 0x01c10800 + SZ_1K - 1,
780                 .flags  = IORESOURCE_MEM,
781         },
782         {
783                 .name   = "edma_tc3",
784                 .start  = 0x01c10c00,
785                 .end    = 0x01c10c00 + SZ_1K - 1,
786                 .flags  = IORESOURCE_MEM,
787         },
788         {
789                 .name   = "edma0",
790                 .start  = IRQ_CCINT0,
791                 .flags  = IORESOURCE_IRQ,
792         },
793         {
794                 .name   = "edma0_err",
795                 .start  = IRQ_CCERRINT,
796                 .flags  = IORESOURCE_IRQ,
797         },
798         /* not using TC*_ERR */
799 };
800
801 static struct platform_device dm365_edma_device = {
802         .name                   = "edma",
803         .id                     = 0,
804         .dev.platform_data      = dm365_edma_info,
805         .num_resources          = ARRAY_SIZE(edma_resources),
806         .resource               = edma_resources,
807 };
808
809 static struct map_desc dm365_io_desc[] = {
810         {
811                 .virtual        = IO_VIRT,
812                 .pfn            = __phys_to_pfn(IO_PHYS),
813                 .length         = IO_SIZE,
814                 .type           = MT_DEVICE
815         },
816         {
817                 .virtual        = SRAM_VIRT,
818                 .pfn            = __phys_to_pfn(0x00010000),
819                 .length         = SZ_32K,
820                 /* MT_MEMORY_NONCACHED requires supersection alignment */
821                 .type           = MT_DEVICE,
822         },
823 };
824
825 /* Contents of JTAG ID register used to identify exact cpu type */
826 static struct davinci_id dm365_ids[] = {
827         {
828                 .variant        = 0x0,
829                 .part_no        = 0xb83e,
830                 .manufacturer   = 0x017,
831                 .cpu_id         = DAVINCI_CPU_ID_DM365,
832                 .name           = "dm365_rev1.1",
833         },
834         {
835                 .variant        = 0x8,
836                 .part_no        = 0xb83e,
837                 .manufacturer   = 0x017,
838                 .cpu_id         = DAVINCI_CPU_ID_DM365,
839                 .name           = "dm365_rev1.2",
840         },
841 };
842
843 static void __iomem *dm365_psc_bases[] = {
844         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
845 };
846
847 struct davinci_timer_info dm365_timer_info = {
848         .timers         = davinci_timer_instance,
849         .clockevent_id  = T0_BOT,
850         .clocksource_id = T0_TOP,
851 };
852
853 static struct plat_serial8250_port dm365_serial_platform_data[] = {
854         {
855                 .mapbase        = DAVINCI_UART0_BASE,
856                 .irq            = IRQ_UARTINT0,
857                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
858                                   UPF_IOREMAP,
859                 .iotype         = UPIO_MEM,
860                 .regshift       = 2,
861         },
862         {
863                 .mapbase        = DAVINCI_UART1_BASE,
864                 .irq            = IRQ_UARTINT1,
865                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
866                                   UPF_IOREMAP,
867                 .iotype         = UPIO_MEM,
868                 .regshift       = 2,
869         },
870         {
871                 .flags          = 0
872         },
873 };
874
875 static struct platform_device dm365_serial_device = {
876         .name                   = "serial8250",
877         .id                     = PLAT8250_DEV_PLATFORM,
878         .dev                    = {
879                 .platform_data  = dm365_serial_platform_data,
880         },
881 };
882
883 static struct davinci_soc_info davinci_soc_info_dm365 = {
884         .io_desc                = dm365_io_desc,
885         .io_desc_num            = ARRAY_SIZE(dm365_io_desc),
886         .jtag_id_base           = IO_ADDRESS(0x01c40028),
887         .ids                    = dm365_ids,
888         .ids_num                = ARRAY_SIZE(dm365_ids),
889         .cpu_clks               = dm365_clks,
890         .psc_bases              = dm365_psc_bases,
891         .psc_bases_num          = ARRAY_SIZE(dm365_psc_bases),
892         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
893         .pinmux_pins            = dm365_pins,
894         .pinmux_pins_num        = ARRAY_SIZE(dm365_pins),
895         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
896         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
897         .intc_irq_prios         = dm365_default_priorities,
898         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
899         .timer_info             = &dm365_timer_info,
900         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
901         .gpio_num               = 104,
902         .gpio_irq               = IRQ_DM365_GPIO0,
903         .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
904         .serial_dev             = &dm365_serial_device,
905         .emac_pdata             = &dm365_emac_pdata,
906         .sram_dma               = 0x00010000,
907         .sram_len               = SZ_32K,
908 };
909
910 void __init dm365_init(void)
911 {
912         davinci_common_init(&davinci_soc_info_dm365);
913 }
914
915 static int __init dm365_init_devices(void)
916 {
917         if (!cpu_is_davinci_dm365())
918                 return 0;
919
920         davinci_cfg_reg(DM365_INT_EDMA_CC);
921         platform_device_register(&dm365_edma_device);
922         platform_device_register(&dm365_emac_device);
923
924         return 0;
925 }
926 postcore_initcall(dm365_init_devices);