Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas...
[linux-2.6.git] / arch / arm / mach-davinci / board-mityomapl138.c
1 /*
2  * Critical Link MityOMAP-L138 SoM
3  *
4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
5  *
6  * This file is licensed under the terms of the GNU General Public License
7  * version 2. This program is licensed "as is" without any warranty of
8  * any kind, whether express or implied.
9  */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/console.h>
14 #include <linux/platform_device.h>
15 #include <linux/mtd/partitions.h>
16 #include <linux/regulator/machine.h>
17 #include <linux/i2c.h>
18 #include <linux/i2c/at24.h>
19 #include <linux/etherdevice.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/flash.h>
22
23 #include <asm/mach-types.h>
24 #include <asm/mach/arch.h>
25 #include <mach/common.h>
26 #include <mach/cp_intc.h>
27 #include <mach/da8xx.h>
28 #include <mach/nand.h>
29 #include <mach/mux.h>
30 #include <mach/spi.h>
31
32 #define MITYOMAPL138_PHY_ID             ""
33
34 #define FACTORY_CONFIG_MAGIC    0x012C0138
35 #define FACTORY_CONFIG_VERSION  0x00010001
36
37 /* Data Held in On-Board I2C device */
38 struct factory_config {
39         u32     magic;
40         u32     version;
41         u8      mac[6];
42         u32     fpga_type;
43         u32     spare;
44         u32     serialnumber;
45         char    partnum[32];
46 };
47
48 static struct factory_config factory_config;
49
50 struct part_no_info {
51         const char      *part_no;       /* part number string of interest */
52         int             max_freq;       /* khz */
53 };
54
55 static struct part_no_info mityomapl138_pn_info[] = {
56         {
57                 .part_no        = "L138-C",
58                 .max_freq       = 300000,
59         },
60         {
61                 .part_no        = "L138-D",
62                 .max_freq       = 375000,
63         },
64         {
65                 .part_no        = "L138-F",
66                 .max_freq       = 456000,
67         },
68         {
69                 .part_no        = "1808-C",
70                 .max_freq       = 300000,
71         },
72         {
73                 .part_no        = "1808-D",
74                 .max_freq       = 375000,
75         },
76         {
77                 .part_no        = "1808-F",
78                 .max_freq       = 456000,
79         },
80         {
81                 .part_no        = "1810-D",
82                 .max_freq       = 375000,
83         },
84 };
85
86 #ifdef CONFIG_CPU_FREQ
87 static void mityomapl138_cpufreq_init(const char *partnum)
88 {
89         int i, ret;
90
91         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
92                 /*
93                  * the part number has additional characters beyond what is
94                  * stored in the table.  This information is not needed for
95                  * determining the speed grade, and would require several
96                  * more table entries.  Only check the first N characters
97                  * for a match.
98                  */
99                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
100                              strlen(mityomapl138_pn_info[i].part_no))) {
101                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
102                         break;
103                 }
104         }
105
106         ret = da850_register_cpufreq("pll0_sysclk3");
107         if (ret)
108                 pr_warning("cpufreq registration failed: %d\n", ret);
109 }
110 #else
111 static void mityomapl138_cpufreq_init(const char *partnum) { }
112 #endif
113
114 static void read_factory_config(struct memory_accessor *a, void *context)
115 {
116         int ret;
117         const char *partnum = NULL;
118         struct davinci_soc_info *soc_info = &davinci_soc_info;
119
120         ret = a->read(a, (char *)&factory_config, 0, sizeof(factory_config));
121         if (ret != sizeof(struct factory_config)) {
122                 pr_warning("MityOMAPL138: Read Factory Config Failed: %d\n",
123                                 ret);
124                 goto bad_config;
125         }
126
127         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
128                 pr_warning("MityOMAPL138: Factory Config Magic Wrong (%X)\n",
129                                 factory_config.magic);
130                 goto bad_config;
131         }
132
133         if (factory_config.version != FACTORY_CONFIG_VERSION) {
134                 pr_warning("MityOMAPL138: Factory Config Version Wrong (%X)\n",
135                                 factory_config.version);
136                 goto bad_config;
137         }
138
139         pr_info("MityOMAPL138: Found MAC = %pM\n", factory_config.mac);
140         if (is_valid_ether_addr(factory_config.mac))
141                 memcpy(soc_info->emac_pdata->mac_addr,
142                         factory_config.mac, ETH_ALEN);
143         else
144                 pr_warning("MityOMAPL138: Invalid MAC found "
145                                 "in factory config block\n");
146
147         partnum = factory_config.partnum;
148         pr_info("MityOMAPL138: Part Number = %s\n", partnum);
149
150 bad_config:
151         /* default maximum speed is valid for all platforms */
152         mityomapl138_cpufreq_init(partnum);
153 }
154
155 static struct at24_platform_data mityomapl138_fd_chip = {
156         .byte_len       = 256,
157         .page_size      = 8,
158         .flags          = AT24_FLAG_READONLY | AT24_FLAG_IRUGO,
159         .setup          = read_factory_config,
160         .context        = NULL,
161 };
162
163 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
164         .bus_freq       = 100,  /* kHz */
165         .bus_delay      = 0,    /* usec */
166 };
167
168 /* TPS65023 voltage regulator support */
169 /* 1.2V Core */
170 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
171         {
172                 .supply = "cvdd",
173         },
174 };
175
176 /* 1.8V */
177 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
178         {
179                 .supply = "usb0_vdda18",
180         },
181         {
182                 .supply = "usb1_vdda18",
183         },
184         {
185                 .supply = "ddr_dvdd18",
186         },
187         {
188                 .supply = "sata_vddr",
189         },
190 };
191
192 /* 1.2V */
193 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
194         {
195                 .supply = "sata_vdd",
196         },
197         {
198                 .supply = "usb_cvdd",
199         },
200         {
201                 .supply = "pll0_vdda",
202         },
203         {
204                 .supply = "pll1_vdda",
205         },
206 };
207
208 /* 1.8V Aux LDO, not used */
209 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
210         {
211                 .supply = "1.8v_aux",
212         },
213 };
214
215 /* FPGA VCC Aux (2.5 or 3.3) LDO */
216 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
217         {
218                 .supply = "vccaux",
219         },
220 };
221
222 static struct regulator_init_data tps65023_regulator_data[] = {
223         /* dcdc1 */
224         {
225                 .constraints = {
226                         .min_uV = 1150000,
227                         .max_uV = 1350000,
228                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
229                                           REGULATOR_CHANGE_STATUS,
230                         .boot_on = 1,
231                 },
232                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
233                 .consumer_supplies = tps65023_dcdc1_consumers,
234         },
235         /* dcdc2 */
236         {
237                 .constraints = {
238                         .min_uV = 1800000,
239                         .max_uV = 1800000,
240                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
241                         .boot_on = 1,
242                 },
243                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
244                 .consumer_supplies = tps65023_dcdc2_consumers,
245         },
246         /* dcdc3 */
247         {
248                 .constraints = {
249                         .min_uV = 1200000,
250                         .max_uV = 1200000,
251                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
252                         .boot_on = 1,
253                 },
254                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
255                 .consumer_supplies = tps65023_dcdc3_consumers,
256         },
257         /* ldo1 */
258         {
259                 .constraints = {
260                         .min_uV = 1800000,
261                         .max_uV = 1800000,
262                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
263                         .boot_on = 1,
264                 },
265                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
266                 .consumer_supplies = tps65023_ldo1_consumers,
267         },
268         /* ldo2 */
269         {
270                 .constraints = {
271                         .min_uV = 2500000,
272                         .max_uV = 3300000,
273                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
274                                           REGULATOR_CHANGE_STATUS,
275                         .boot_on = 1,
276                 },
277                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
278                 .consumer_supplies = tps65023_ldo2_consumers,
279         },
280 };
281
282 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
283         {
284                 I2C_BOARD_INFO("tps65023", 0x48),
285                 .platform_data = &tps65023_regulator_data[0],
286         },
287         {
288                 I2C_BOARD_INFO("24c02", 0x50),
289                 .platform_data = &mityomapl138_fd_chip,
290         },
291 };
292
293 static int __init pmic_tps65023_init(void)
294 {
295         return i2c_register_board_info(1, mityomap_tps65023_info,
296                                         ARRAY_SIZE(mityomap_tps65023_info));
297 }
298
299 /*
300  * SPI Devices:
301  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
302  */
303 static struct mtd_partition spi_flash_partitions[] = {
304         [0] = {
305                 .name           = "ubl",
306                 .offset         = 0,
307                 .size           = SZ_64K,
308                 .mask_flags     = MTD_WRITEABLE,
309         },
310         [1] = {
311                 .name           = "u-boot",
312                 .offset         = MTDPART_OFS_APPEND,
313                 .size           = SZ_512K,
314                 .mask_flags     = MTD_WRITEABLE,
315         },
316         [2] = {
317                 .name           = "u-boot-env",
318                 .offset         = MTDPART_OFS_APPEND,
319                 .size           = SZ_64K,
320                 .mask_flags     = MTD_WRITEABLE,
321         },
322         [3] = {
323                 .name           = "periph-config",
324                 .offset         = MTDPART_OFS_APPEND,
325                 .size           = SZ_64K,
326                 .mask_flags     = MTD_WRITEABLE,
327         },
328         [4] = {
329                 .name           = "reserved",
330                 .offset         = MTDPART_OFS_APPEND,
331                 .size           = SZ_256K + SZ_64K,
332         },
333         [5] = {
334                 .name           = "kernel",
335                 .offset         = MTDPART_OFS_APPEND,
336                 .size           = SZ_2M + SZ_1M,
337         },
338         [6] = {
339                 .name           = "fpga",
340                 .offset         = MTDPART_OFS_APPEND,
341                 .size           = SZ_2M,
342         },
343         [7] = {
344                 .name           = "spare",
345                 .offset         = MTDPART_OFS_APPEND,
346                 .size           = MTDPART_SIZ_FULL,
347         },
348 };
349
350 static struct flash_platform_data mityomapl138_spi_flash_data = {
351         .name           = "m25p80",
352         .parts          = spi_flash_partitions,
353         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
354         .type           = "m24p64",
355 };
356
357 static struct davinci_spi_config spi_eprom_config = {
358         .io_type        = SPI_IO_TYPE_DMA,
359         .c2tdelay       = 8,
360         .t2cdelay       = 8,
361 };
362
363 static struct spi_board_info mityomapl138_spi_flash_info[] = {
364         {
365                 .modalias               = "m25p80",
366                 .platform_data          = &mityomapl138_spi_flash_data,
367                 .controller_data        = &spi_eprom_config,
368                 .mode                   = SPI_MODE_0,
369                 .max_speed_hz           = 30000000,
370                 .bus_num                = 1,
371                 .chip_select            = 0,
372         },
373 };
374
375 /*
376  * MityDSP-L138 includes a 256 MByte large-page NAND flash
377  * (128K blocks).
378  */
379 static struct mtd_partition mityomapl138_nandflash_partition[] = {
380         {
381                 .name           = "rootfs",
382                 .offset         = 0,
383                 .size           = SZ_128M,
384                 .mask_flags     = 0, /* MTD_WRITEABLE, */
385         },
386         {
387                 .name           = "homefs",
388                 .offset         = MTDPART_OFS_APPEND,
389                 .size           = MTDPART_SIZ_FULL,
390                 .mask_flags     = 0,
391         },
392 };
393
394 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
395         .parts          = mityomapl138_nandflash_partition,
396         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
397         .ecc_mode       = NAND_ECC_HW,
398         .options        = NAND_USE_FLASH_BBT | NAND_BUSWIDTH_16,
399         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
400 };
401
402 static struct resource mityomapl138_nandflash_resource[] = {
403         {
404                 .start  = DA8XX_AEMIF_CS3_BASE,
405                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
406                 .flags  = IORESOURCE_MEM,
407         },
408         {
409                 .start  = DA8XX_AEMIF_CTL_BASE,
410                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
411                 .flags  = IORESOURCE_MEM,
412         },
413 };
414
415 static struct platform_device mityomapl138_nandflash_device = {
416         .name           = "davinci_nand",
417         .id             = 1,
418         .dev            = {
419                 .platform_data  = &mityomapl138_nandflash_data,
420         },
421         .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
422         .resource       = mityomapl138_nandflash_resource,
423 };
424
425 static struct platform_device *mityomapl138_devices[] __initdata = {
426         &mityomapl138_nandflash_device,
427 };
428
429 static void __init mityomapl138_setup_nand(void)
430 {
431         platform_add_devices(mityomapl138_devices,
432                                  ARRAY_SIZE(mityomapl138_devices));
433 }
434
435 static struct davinci_uart_config mityomapl138_uart_config __initdata = {
436         .enabled_uarts = 0x7,
437 };
438
439 static const short mityomap_mii_pins[] = {
440         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
441         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
442         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
443         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
444         DA850_MDIO_D,
445         -1
446 };
447
448 static const short mityomap_rmii_pins[] = {
449         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
450         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
451         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
452         DA850_MDIO_D,
453         -1
454 };
455
456 static void __init mityomapl138_config_emac(void)
457 {
458         void __iomem *cfg_chip3_base;
459         int ret;
460         u32 val;
461         struct davinci_soc_info *soc_info = &davinci_soc_info;
462
463         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
464
465         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
466         val = __raw_readl(cfg_chip3_base);
467
468         if (soc_info->emac_pdata->rmii_en) {
469                 val |= BIT(8);
470                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
471                 pr_info("RMII PHY configured\n");
472         } else {
473                 val &= ~BIT(8);
474                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
475                 pr_info("MII PHY configured\n");
476         }
477
478         if (ret) {
479                 pr_warning("mii/rmii mux setup failed: %d\n", ret);
480                 return;
481         }
482
483         /* configure the CFGCHIP3 register for RMII or MII */
484         __raw_writel(val, cfg_chip3_base);
485
486         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
487
488         ret = da8xx_register_emac();
489         if (ret)
490                 pr_warning("emac registration failed: %d\n", ret);
491 }
492
493 static struct davinci_pm_config da850_pm_pdata = {
494         .sleepcount = 128,
495 };
496
497 static struct platform_device da850_pm_device = {
498         .name   = "pm-davinci",
499         .dev = {
500                 .platform_data  = &da850_pm_pdata,
501         },
502         .id     = -1,
503 };
504
505 static void __init mityomapl138_init(void)
506 {
507         int ret;
508
509         /* for now, no special EDMA channels are reserved */
510         ret = da850_register_edma(NULL);
511         if (ret)
512                 pr_warning("edma registration failed: %d\n", ret);
513
514         ret = da8xx_register_watchdog();
515         if (ret)
516                 pr_warning("watchdog registration failed: %d\n", ret);
517
518         davinci_serial_init(&mityomapl138_uart_config);
519
520         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
521         if (ret)
522                 pr_warning("i2c0 registration failed: %d\n", ret);
523
524         ret = pmic_tps65023_init();
525         if (ret)
526                 pr_warning("TPS65023 PMIC init failed: %d\n", ret);
527
528         mityomapl138_setup_nand();
529
530         ret = da8xx_register_spi(1, mityomapl138_spi_flash_info,
531                                ARRAY_SIZE(mityomapl138_spi_flash_info));
532         if (ret)
533                 pr_warning("spi 1 registration failed: %d\n", ret);
534
535         mityomapl138_config_emac();
536
537         ret = da8xx_register_rtc();
538         if (ret)
539                 pr_warning("rtc setup failed: %d\n", ret);
540
541         ret = da8xx_register_cpuidle();
542         if (ret)
543                 pr_warning("cpuidle registration failed: %d\n", ret);
544
545         ret = da850_register_pm(&da850_pm_device);
546         if (ret)
547                 pr_warning("da850_evm_init: suspend registration failed: %d\n",
548                                 ret);
549 }
550
551 #ifdef CONFIG_SERIAL_8250_CONSOLE
552 static int __init mityomapl138_console_init(void)
553 {
554         if (!machine_is_mityomapl138())
555                 return 0;
556
557         return add_preferred_console("ttyS", 1, "115200");
558 }
559 console_initcall(mityomapl138_console_init);
560 #endif
561
562 static void __init mityomapl138_map_io(void)
563 {
564         da850_init();
565 }
566
567 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
568         .boot_params    = (DA8XX_DDR_BASE + 0x100),
569         .map_io         = mityomapl138_map_io,
570         .init_irq       = cp_intc_init,
571         .timer          = &davinci_timer,
572         .init_machine   = mityomapl138_init,
573 MACHINE_END