Merge branch 'samsung/exynos5' into next/soc2
[linux-2.6.git] / arch / arm / mach-bcmring / include / mach / entry-macro.S
1 /*****************************************************************************
2 * Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
3 *
4 * Unless you and Broadcom execute a separate written software license
5 * agreement governing use of this software, this software is licensed to you
6 * under the terms of the GNU General Public License version 2, available at
7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8 *
9 * Notwithstanding the above, under no circumstances may you combine this
10 * software in any way with any other Broadcom software provided under a
11 * license other than the GPL, without Broadcom's express prior written
12 * consent.
13 *****************************************************************************/
14
15 /*
16  *
17  * Low-level IRQ helper macros for BCMRing-based platforms
18  *
19  */
20 #include <mach/irqs.h>
21 #include <mach/hardware.h>
22 #include <mach/csp/mm_io.h>
23
24                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
25                 ldr     \base, =(MM_IO_BASE_INTC0)
26                 ldr     \irqstat, [\base, #0]           @ get status
27                 ldr     \irqnr, [\base, #0x10]          @ mask with enable register
28                 ands    \irqstat, \irqstat, \irqnr
29                 mov     \irqnr, #IRQ_INTC0_START
30                 cmp     \irqstat, #0
31                 bne     1001f
32
33                 ldr     \base, =(MM_IO_BASE_INTC1)
34                 ldr     \irqstat, [\base, #0]           @ get status
35                 ldr     \irqnr, [\base, #0x10]          @ mask with enable register
36                 ands    \irqstat, \irqstat, \irqnr
37                 mov     \irqnr, #IRQ_INTC1_START
38                 cmp     \irqstat, #0
39                 bne     1001f
40
41                 ldr     \base, =(MM_IO_BASE_SINTC)
42                 ldr     \irqstat, [\base, #0]           @ get status
43                 ldr     \irqnr, [\base, #0x10]          @ mask with enable register
44                 ands    \irqstat, \irqstat, \irqnr
45                 mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
46                 cmp     \irqstat, #0
47                 beq     1002f
48
49                 mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
50
51 1001:
52                 movs    \tmp, \irqstat, lsl #16
53                 movne   \irqstat, \tmp
54                 addeq   \irqnr, \irqnr, #16
55
56                 movs    \tmp, \irqstat, lsl #8
57                 movne   \irqstat, \tmp
58                 addeq   \irqnr, \irqnr, #8
59
60                 movs    \tmp, \irqstat, lsl #4
61                 movne   \irqstat, \tmp
62                 addeq   \irqnr, \irqnr, #4
63
64                 movs    \tmp, \irqstat, lsl #2
65                 movne   \irqstat, \tmp
66                 addeq   \irqnr, \irqnr, #2
67
68                 movs    \tmp, \irqstat, lsl #1
69                 addeq   \irqnr, \irqnr, #1
70                 orrs    \base, \base, #1
71
72 1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
73                 .endm
74
75                 .macro  get_irqnr_preamble, base, tmp
76                 .endm