582142e049a87391f88ec1aa0e28684188cb221a
[linux-2.6.git] / arch / arm / mach-at91 / setup.c
1 /*
2  * Copyright (C) 2007 Atmel Corporation.
3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4  *
5  * Under GPLv2
6  */
7
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/mm.h>
11 #include <linux/pm.h>
12 #include <linux/of_address.h>
13
14 #include <asm/system_misc.h>
15 #include <asm/mach/map.h>
16
17 #include <mach/hardware.h>
18 #include <mach/cpu.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_shdwc.h>
22
23 #include "soc.h"
24 #include "generic.h"
25
26 struct at91_init_soc __initdata at91_boot_soc;
27
28 struct at91_socinfo at91_soc_initdata;
29 EXPORT_SYMBOL(at91_soc_initdata);
30
31 void __init at91rm9200_set_type(int type)
32 {
33         if (type == ARCH_REVISON_9200_PQFP)
34                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
35         else
36                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
37
38         pr_info("AT91: filled in soc subtype: %s\n",
39                 at91_get_soc_subtype(&at91_soc_initdata));
40 }
41
42 void __init at91_init_irq_default(void)
43 {
44         at91_init_interrupts(at91_boot_soc.default_irq_priority);
45 }
46
47 void __init at91_init_interrupts(unsigned int *priority)
48 {
49         /* Initialize the AIC interrupt controller */
50         at91_aic_init(priority);
51
52         /* Enable GPIO interrupts */
53         at91_gpio_irq_setup();
54 }
55
56 void __iomem *at91_ramc_base[2];
57 EXPORT_SYMBOL_GPL(at91_ramc_base);
58
59 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
60 {
61         if (id < 0 || id > 1) {
62                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
63                 BUG();
64         }
65         at91_ramc_base[id] = ioremap(addr, size);
66         if (!at91_ramc_base[id])
67                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
68 }
69
70 static struct map_desc sram_desc[2] __initdata;
71
72 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
73 {
74         struct map_desc *desc = &sram_desc[bank];
75
76         desc->virtual = AT91_IO_VIRT_BASE - length;
77         if (bank > 0)
78                 desc->virtual -= sram_desc[bank - 1].length;
79
80         desc->pfn = __phys_to_pfn(base);
81         desc->length = length;
82         desc->type = MT_DEVICE;
83
84         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
85                 base, length, desc->virtual);
86
87         iotable_init(desc, 1);
88 }
89
90 static struct map_desc at91_io_desc __initdata = {
91         .virtual        = AT91_VA_BASE_SYS,
92         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
93         .length         = SZ_16K,
94         .type           = MT_DEVICE,
95 };
96
97 static void __init soc_detect(u32 dbgu_base)
98 {
99         u32 cidr, socid;
100
101         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
102         socid = cidr & ~AT91_CIDR_VERSION;
103
104         switch (socid) {
105         case ARCH_ID_AT91RM9200:
106                 at91_soc_initdata.type = AT91_SOC_RM9200;
107                 at91_boot_soc = at91rm9200_soc;
108                 break;
109
110         case ARCH_ID_AT91SAM9260:
111                 at91_soc_initdata.type = AT91_SOC_SAM9260;
112                 at91_boot_soc = at91sam9260_soc;
113                 break;
114
115         case ARCH_ID_AT91SAM9261:
116                 at91_soc_initdata.type = AT91_SOC_SAM9261;
117                 at91_boot_soc = at91sam9261_soc;
118                 break;
119
120         case ARCH_ID_AT91SAM9263:
121                 at91_soc_initdata.type = AT91_SOC_SAM9263;
122                 at91_boot_soc = at91sam9263_soc;
123                 break;
124
125         case ARCH_ID_AT91SAM9G20:
126                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
127                 at91_boot_soc = at91sam9260_soc;
128                 break;
129
130         case ARCH_ID_AT91SAM9G45:
131                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
132                 if (cidr == ARCH_ID_AT91SAM9G45ES)
133                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
134                 at91_boot_soc = at91sam9g45_soc;
135                 break;
136
137         case ARCH_ID_AT91SAM9RL64:
138                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
139                 at91_boot_soc = at91sam9rl_soc;
140                 break;
141
142         case ARCH_ID_AT91SAM9X5:
143                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
144                 at91_boot_soc = at91sam9x5_soc;
145                 break;
146         }
147
148         /* at91sam9g10 */
149         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
150                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
151                 at91_boot_soc = at91sam9261_soc;
152         }
153         /* at91sam9xe */
154         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
155                 at91_soc_initdata.type = AT91_SOC_SAM9260;
156                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
157                 at91_boot_soc = at91sam9260_soc;
158         }
159
160         if (!at91_soc_is_detected())
161                 return;
162
163         at91_soc_initdata.cidr = cidr;
164
165         /* sub version of soc */
166         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
167
168         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
169                 switch (at91_soc_initdata.exid) {
170                 case ARCH_EXID_AT91SAM9M10:
171                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
172                         break;
173                 case ARCH_EXID_AT91SAM9G46:
174                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
175                         break;
176                 case ARCH_EXID_AT91SAM9M11:
177                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
178                         break;
179                 }
180         }
181
182         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
183                 switch (at91_soc_initdata.exid) {
184                 case ARCH_EXID_AT91SAM9G15:
185                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
186                         break;
187                 case ARCH_EXID_AT91SAM9G35:
188                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
189                         break;
190                 case ARCH_EXID_AT91SAM9X35:
191                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
192                         break;
193                 case ARCH_EXID_AT91SAM9G25:
194                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
195                         break;
196                 case ARCH_EXID_AT91SAM9X25:
197                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
198                         break;
199                 }
200         }
201 }
202
203 static const char *soc_name[] = {
204         [AT91_SOC_RM9200]       = "at91rm9200",
205         [AT91_SOC_SAM9260]      = "at91sam9260",
206         [AT91_SOC_SAM9261]      = "at91sam9261",
207         [AT91_SOC_SAM9263]      = "at91sam9263",
208         [AT91_SOC_SAM9G10]      = "at91sam9g10",
209         [AT91_SOC_SAM9G20]      = "at91sam9g20",
210         [AT91_SOC_SAM9G45]      = "at91sam9g45",
211         [AT91_SOC_SAM9RL]       = "at91sam9rl",
212         [AT91_SOC_SAM9X5]       = "at91sam9x5",
213         [AT91_SOC_NONE]         = "Unknown"
214 };
215
216 const char *at91_get_soc_type(struct at91_socinfo *c)
217 {
218         return soc_name[c->type];
219 }
220 EXPORT_SYMBOL(at91_get_soc_type);
221
222 static const char *soc_subtype_name[] = {
223         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
224         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
225         [AT91_SOC_SAM9XE]       = "at91sam9xe",
226         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
227         [AT91_SOC_SAM9M10]      = "at91sam9m10",
228         [AT91_SOC_SAM9G46]      = "at91sam9g46",
229         [AT91_SOC_SAM9M11]      = "at91sam9m11",
230         [AT91_SOC_SAM9G15]      = "at91sam9g15",
231         [AT91_SOC_SAM9G35]      = "at91sam9g35",
232         [AT91_SOC_SAM9X35]      = "at91sam9x35",
233         [AT91_SOC_SAM9G25]      = "at91sam9g25",
234         [AT91_SOC_SAM9X25]      = "at91sam9x25",
235         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
236 };
237
238 const char *at91_get_soc_subtype(struct at91_socinfo *c)
239 {
240         return soc_subtype_name[c->subtype];
241 }
242 EXPORT_SYMBOL(at91_get_soc_subtype);
243
244 void __init at91_map_io(void)
245 {
246         /* Map peripherals */
247         iotable_init(&at91_io_desc, 1);
248
249         at91_soc_initdata.type = AT91_SOC_NONE;
250         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
251
252         soc_detect(AT91_BASE_DBGU0);
253         if (!at91_soc_is_detected())
254                 soc_detect(AT91_BASE_DBGU1);
255
256         if (!at91_soc_is_detected())
257                 panic("AT91: Impossible to detect the SOC type");
258
259         pr_info("AT91: Detected soc type: %s\n",
260                 at91_get_soc_type(&at91_soc_initdata));
261         pr_info("AT91: Detected soc subtype: %s\n",
262                 at91_get_soc_subtype(&at91_soc_initdata));
263
264         if (!at91_soc_is_enabled())
265                 panic("AT91: Soc not enabled");
266
267         if (at91_boot_soc.map_io)
268                 at91_boot_soc.map_io();
269 }
270
271 void __iomem *at91_shdwc_base = NULL;
272
273 static void at91sam9_poweroff(void)
274 {
275         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
276 }
277
278 void __init at91_ioremap_shdwc(u32 base_addr)
279 {
280         at91_shdwc_base = ioremap(base_addr, 16);
281         if (!at91_shdwc_base)
282                 panic("Impossible to ioremap at91_shdwc_base\n");
283         pm_power_off = at91sam9_poweroff;
284 }
285
286 void __iomem *at91_rstc_base;
287
288 void __init at91_ioremap_rstc(u32 base_addr)
289 {
290         at91_rstc_base = ioremap(base_addr, 16);
291         if (!at91_rstc_base)
292                 panic("Impossible to ioremap at91_rstc_base\n");
293 }
294
295 void __iomem *at91_matrix_base;
296 EXPORT_SYMBOL_GPL(at91_matrix_base);
297
298 void __init at91_ioremap_matrix(u32 base_addr)
299 {
300         at91_matrix_base = ioremap(base_addr, 512);
301         if (!at91_matrix_base)
302                 panic("Impossible to ioremap at91_matrix_base\n");
303 }
304
305 #if defined(CONFIG_OF)
306 static struct of_device_id rstc_ids[] = {
307         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
308         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
309         { /*sentinel*/ }
310 };
311
312 static void at91_dt_rstc(void)
313 {
314         struct device_node *np;
315         const struct of_device_id *of_id;
316
317         np = of_find_matching_node(NULL, rstc_ids);
318         if (!np)
319                 panic("unable to find compatible rstc node in dtb\n");
320
321         at91_rstc_base = of_iomap(np, 0);
322         if (!at91_rstc_base)
323                 panic("unable to map rstc cpu registers\n");
324
325         of_id = of_match_node(rstc_ids, np);
326         if (!of_id)
327                 panic("AT91: rtsc no restart function availlable\n");
328
329         arm_pm_restart = of_id->data;
330
331         of_node_put(np);
332 }
333
334 static struct of_device_id ramc_ids[] = {
335         { .compatible = "atmel,at91sam9260-sdramc" },
336         { .compatible = "atmel,at91sam9g45-ddramc" },
337         { /*sentinel*/ }
338 };
339
340 static void at91_dt_ramc(void)
341 {
342         struct device_node *np;
343
344         np = of_find_matching_node(NULL, ramc_ids);
345         if (!np)
346                 panic("unable to find compatible ram conroller node in dtb\n");
347
348         at91_ramc_base[0] = of_iomap(np, 0);
349         if (!at91_ramc_base[0])
350                 panic("unable to map ramc[0] cpu registers\n");
351         /* the controller may have 2 banks */
352         at91_ramc_base[1] = of_iomap(np, 1);
353
354         of_node_put(np);
355 }
356
357 static struct of_device_id shdwc_ids[] = {
358         { .compatible = "atmel,at91sam9260-shdwc", },
359         { .compatible = "atmel,at91sam9rl-shdwc", },
360         { .compatible = "atmel,at91sam9x5-shdwc", },
361         { /*sentinel*/ }
362 };
363
364 static const char *shdwc_wakeup_modes[] = {
365         [AT91_SHDW_WKMODE0_NONE]        = "none",
366         [AT91_SHDW_WKMODE0_HIGH]        = "high",
367         [AT91_SHDW_WKMODE0_LOW]         = "low",
368         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
369 };
370
371 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
372 {
373         const char *pm;
374         int err, i;
375
376         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
377         if (err < 0)
378                 return AT91_SHDW_WKMODE0_ANYLEVEL;
379
380         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
381                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
382                         return i;
383
384         return -ENODEV;
385 }
386
387 static void at91_dt_shdwc(void)
388 {
389         struct device_node *np;
390         int wakeup_mode;
391         u32 reg;
392         u32 mode = 0;
393
394         np = of_find_matching_node(NULL, shdwc_ids);
395         if (!np) {
396                 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
397                 return;
398         }
399
400         at91_shdwc_base = of_iomap(np, 0);
401         if (!at91_shdwc_base)
402                 panic("AT91: unable to map shdwc cpu registers\n");
403
404         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
405         if (wakeup_mode < 0) {
406                 pr_warn("AT91: shdwc unknown wakeup mode\n");
407                 goto end;
408         }
409
410         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
411                 if (reg > AT91_SHDW_CPTWK0_MAX) {
412                         pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
413                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
414                         reg = AT91_SHDW_CPTWK0_MAX;
415                 }
416                 mode |= AT91_SHDW_CPTWK0_(reg);
417         }
418
419         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
420                         mode |= AT91_SHDW_RTCWKEN;
421
422         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
423                         mode |= AT91_SHDW_RTTWKEN;
424
425         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
426
427 end:
428         pm_power_off = at91sam9_poweroff;
429
430         of_node_put(np);
431 }
432
433 void __init at91_dt_initialize(void)
434 {
435         at91_dt_rstc();
436         at91_dt_ramc();
437         at91_dt_shdwc();
438
439         /* Init clock subsystem */
440         at91_dt_clock_init();
441
442         /* Register the processor-specific clocks */
443         at91_boot_soc.register_clocks();
444
445         at91_boot_soc.init();
446 }
447 #endif
448
449 void __init at91_initialize(unsigned long main_clock)
450 {
451         at91_boot_soc.ioremap_registers();
452
453         /* Init clock subsystem */
454         at91_clock_init(main_clock);
455
456         /* Register the processor-specific clocks */
457         at91_boot_soc.register_clocks();
458
459         at91_boot_soc.init();
460 }