ARM: at91: rm9200: remake the BGA as default version
[linux-2.6.git] / arch / arm / mach-at91 / setup.c
1 /*
2  * Copyright (C) 2007 Atmel Corporation.
3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
4  *
5  * Under GPLv2
6  */
7
8 #include <linux/module.h>
9 #include <linux/io.h>
10 #include <linux/mm.h>
11 #include <linux/pm.h>
12 #include <linux/of_address.h>
13
14 #include <asm/system_misc.h>
15 #include <asm/mach/map.h>
16
17 #include <mach/hardware.h>
18 #include <mach/cpu.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_shdwc.h>
22
23 #include "soc.h"
24 #include "generic.h"
25
26 struct at91_init_soc __initdata at91_boot_soc;
27
28 struct at91_socinfo at91_soc_initdata;
29 EXPORT_SYMBOL(at91_soc_initdata);
30
31 void __init at91rm9200_set_type(int type)
32 {
33         if (type == ARCH_REVISON_9200_PQFP)
34                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
35         else
36                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
37
38         pr_info("AT91: filled in soc subtype: %s\n",
39                 at91_get_soc_subtype(&at91_soc_initdata));
40 }
41
42 void __init at91_init_irq_default(void)
43 {
44         at91_init_interrupts(at91_boot_soc.default_irq_priority);
45 }
46
47 void __init at91_init_interrupts(unsigned int *priority)
48 {
49         /* Initialize the AIC interrupt controller */
50         at91_aic_init(priority);
51
52         /* Enable GPIO interrupts */
53         at91_gpio_irq_setup();
54 }
55
56 void __iomem *at91_ramc_base[2];
57 EXPORT_SYMBOL_GPL(at91_ramc_base);
58
59 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
60 {
61         if (id < 0 || id > 1) {
62                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
63                 BUG();
64         }
65         at91_ramc_base[id] = ioremap(addr, size);
66         if (!at91_ramc_base[id])
67                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
68 }
69
70 static struct map_desc sram_desc[2] __initdata;
71
72 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
73 {
74         struct map_desc *desc = &sram_desc[bank];
75
76         desc->virtual = AT91_IO_VIRT_BASE - length;
77         if (bank > 0)
78                 desc->virtual -= sram_desc[bank - 1].length;
79
80         desc->pfn = __phys_to_pfn(base);
81         desc->length = length;
82         desc->type = MT_DEVICE;
83
84         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
85                 base, length, desc->virtual);
86
87         iotable_init(desc, 1);
88 }
89
90 static struct map_desc at91_io_desc __initdata = {
91         .virtual        = AT91_VA_BASE_SYS,
92         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
93         .length         = SZ_16K,
94         .type           = MT_DEVICE,
95 };
96
97 static void __init soc_detect(u32 dbgu_base)
98 {
99         u32 cidr, socid;
100
101         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
102         socid = cidr & ~AT91_CIDR_VERSION;
103
104         switch (socid) {
105         case ARCH_ID_AT91RM9200:
106                 at91_soc_initdata.type = AT91_SOC_RM9200;
107                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE)
108                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
109                 at91_boot_soc = at91rm9200_soc;
110                 break;
111
112         case ARCH_ID_AT91SAM9260:
113                 at91_soc_initdata.type = AT91_SOC_SAM9260;
114                 at91_boot_soc = at91sam9260_soc;
115                 break;
116
117         case ARCH_ID_AT91SAM9261:
118                 at91_soc_initdata.type = AT91_SOC_SAM9261;
119                 at91_boot_soc = at91sam9261_soc;
120                 break;
121
122         case ARCH_ID_AT91SAM9263:
123                 at91_soc_initdata.type = AT91_SOC_SAM9263;
124                 at91_boot_soc = at91sam9263_soc;
125                 break;
126
127         case ARCH_ID_AT91SAM9G20:
128                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
129                 at91_boot_soc = at91sam9260_soc;
130                 break;
131
132         case ARCH_ID_AT91SAM9G45:
133                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
134                 if (cidr == ARCH_ID_AT91SAM9G45ES)
135                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
136                 at91_boot_soc = at91sam9g45_soc;
137                 break;
138
139         case ARCH_ID_AT91SAM9RL64:
140                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
141                 at91_boot_soc = at91sam9rl_soc;
142                 break;
143
144         case ARCH_ID_AT91SAM9X5:
145                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
146                 at91_boot_soc = at91sam9x5_soc;
147                 break;
148         }
149
150         /* at91sam9g10 */
151         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
152                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
153                 at91_boot_soc = at91sam9261_soc;
154         }
155         /* at91sam9xe */
156         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
157                 at91_soc_initdata.type = AT91_SOC_SAM9260;
158                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
159                 at91_boot_soc = at91sam9260_soc;
160         }
161
162         if (!at91_soc_is_detected())
163                 return;
164
165         at91_soc_initdata.cidr = cidr;
166
167         /* sub version of soc */
168         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
169
170         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
171                 switch (at91_soc_initdata.exid) {
172                 case ARCH_EXID_AT91SAM9M10:
173                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
174                         break;
175                 case ARCH_EXID_AT91SAM9G46:
176                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
177                         break;
178                 case ARCH_EXID_AT91SAM9M11:
179                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
180                         break;
181                 }
182         }
183
184         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
185                 switch (at91_soc_initdata.exid) {
186                 case ARCH_EXID_AT91SAM9G15:
187                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
188                         break;
189                 case ARCH_EXID_AT91SAM9G35:
190                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
191                         break;
192                 case ARCH_EXID_AT91SAM9X35:
193                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
194                         break;
195                 case ARCH_EXID_AT91SAM9G25:
196                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
197                         break;
198                 case ARCH_EXID_AT91SAM9X25:
199                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
200                         break;
201                 }
202         }
203 }
204
205 static const char *soc_name[] = {
206         [AT91_SOC_RM9200]       = "at91rm9200",
207         [AT91_SOC_SAM9260]      = "at91sam9260",
208         [AT91_SOC_SAM9261]      = "at91sam9261",
209         [AT91_SOC_SAM9263]      = "at91sam9263",
210         [AT91_SOC_SAM9G10]      = "at91sam9g10",
211         [AT91_SOC_SAM9G20]      = "at91sam9g20",
212         [AT91_SOC_SAM9G45]      = "at91sam9g45",
213         [AT91_SOC_SAM9RL]       = "at91sam9rl",
214         [AT91_SOC_SAM9X5]       = "at91sam9x5",
215         [AT91_SOC_NONE]         = "Unknown"
216 };
217
218 const char *at91_get_soc_type(struct at91_socinfo *c)
219 {
220         return soc_name[c->type];
221 }
222 EXPORT_SYMBOL(at91_get_soc_type);
223
224 static const char *soc_subtype_name[] = {
225         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
226         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
227         [AT91_SOC_SAM9XE]       = "at91sam9xe",
228         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
229         [AT91_SOC_SAM9M10]      = "at91sam9m10",
230         [AT91_SOC_SAM9G46]      = "at91sam9g46",
231         [AT91_SOC_SAM9M11]      = "at91sam9m11",
232         [AT91_SOC_SAM9G15]      = "at91sam9g15",
233         [AT91_SOC_SAM9G35]      = "at91sam9g35",
234         [AT91_SOC_SAM9X35]      = "at91sam9x35",
235         [AT91_SOC_SAM9G25]      = "at91sam9g25",
236         [AT91_SOC_SAM9X25]      = "at91sam9x25",
237         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
238 };
239
240 const char *at91_get_soc_subtype(struct at91_socinfo *c)
241 {
242         return soc_subtype_name[c->subtype];
243 }
244 EXPORT_SYMBOL(at91_get_soc_subtype);
245
246 void __init at91_map_io(void)
247 {
248         /* Map peripherals */
249         iotable_init(&at91_io_desc, 1);
250
251         at91_soc_initdata.type = AT91_SOC_NONE;
252         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
253
254         soc_detect(AT91_BASE_DBGU0);
255         if (!at91_soc_is_detected())
256                 soc_detect(AT91_BASE_DBGU1);
257
258         if (!at91_soc_is_detected())
259                 panic("AT91: Impossible to detect the SOC type");
260
261         pr_info("AT91: Detected soc type: %s\n",
262                 at91_get_soc_type(&at91_soc_initdata));
263         pr_info("AT91: Detected soc subtype: %s\n",
264                 at91_get_soc_subtype(&at91_soc_initdata));
265
266         if (!at91_soc_is_enabled())
267                 panic("AT91: Soc not enabled");
268
269         if (at91_boot_soc.map_io)
270                 at91_boot_soc.map_io();
271 }
272
273 void __iomem *at91_shdwc_base = NULL;
274
275 static void at91sam9_poweroff(void)
276 {
277         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
278 }
279
280 void __init at91_ioremap_shdwc(u32 base_addr)
281 {
282         at91_shdwc_base = ioremap(base_addr, 16);
283         if (!at91_shdwc_base)
284                 panic("Impossible to ioremap at91_shdwc_base\n");
285         pm_power_off = at91sam9_poweroff;
286 }
287
288 void __iomem *at91_rstc_base;
289
290 void __init at91_ioremap_rstc(u32 base_addr)
291 {
292         at91_rstc_base = ioremap(base_addr, 16);
293         if (!at91_rstc_base)
294                 panic("Impossible to ioremap at91_rstc_base\n");
295 }
296
297 void __iomem *at91_matrix_base;
298 EXPORT_SYMBOL_GPL(at91_matrix_base);
299
300 void __init at91_ioremap_matrix(u32 base_addr)
301 {
302         at91_matrix_base = ioremap(base_addr, 512);
303         if (!at91_matrix_base)
304                 panic("Impossible to ioremap at91_matrix_base\n");
305 }
306
307 #if defined(CONFIG_OF)
308 static struct of_device_id rstc_ids[] = {
309         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
310         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
311         { /*sentinel*/ }
312 };
313
314 static void at91_dt_rstc(void)
315 {
316         struct device_node *np;
317         const struct of_device_id *of_id;
318
319         np = of_find_matching_node(NULL, rstc_ids);
320         if (!np)
321                 panic("unable to find compatible rstc node in dtb\n");
322
323         at91_rstc_base = of_iomap(np, 0);
324         if (!at91_rstc_base)
325                 panic("unable to map rstc cpu registers\n");
326
327         of_id = of_match_node(rstc_ids, np);
328         if (!of_id)
329                 panic("AT91: rtsc no restart function availlable\n");
330
331         arm_pm_restart = of_id->data;
332
333         of_node_put(np);
334 }
335
336 static struct of_device_id ramc_ids[] = {
337         { .compatible = "atmel,at91sam9260-sdramc" },
338         { .compatible = "atmel,at91sam9g45-ddramc" },
339         { /*sentinel*/ }
340 };
341
342 static void at91_dt_ramc(void)
343 {
344         struct device_node *np;
345
346         np = of_find_matching_node(NULL, ramc_ids);
347         if (!np)
348                 panic("unable to find compatible ram conroller node in dtb\n");
349
350         at91_ramc_base[0] = of_iomap(np, 0);
351         if (!at91_ramc_base[0])
352                 panic("unable to map ramc[0] cpu registers\n");
353         /* the controller may have 2 banks */
354         at91_ramc_base[1] = of_iomap(np, 1);
355
356         of_node_put(np);
357 }
358
359 static struct of_device_id shdwc_ids[] = {
360         { .compatible = "atmel,at91sam9260-shdwc", },
361         { .compatible = "atmel,at91sam9rl-shdwc", },
362         { .compatible = "atmel,at91sam9x5-shdwc", },
363         { /*sentinel*/ }
364 };
365
366 static const char *shdwc_wakeup_modes[] = {
367         [AT91_SHDW_WKMODE0_NONE]        = "none",
368         [AT91_SHDW_WKMODE0_HIGH]        = "high",
369         [AT91_SHDW_WKMODE0_LOW]         = "low",
370         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
371 };
372
373 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
374 {
375         const char *pm;
376         int err, i;
377
378         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
379         if (err < 0)
380                 return AT91_SHDW_WKMODE0_ANYLEVEL;
381
382         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
383                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
384                         return i;
385
386         return -ENODEV;
387 }
388
389 static void at91_dt_shdwc(void)
390 {
391         struct device_node *np;
392         int wakeup_mode;
393         u32 reg;
394         u32 mode = 0;
395
396         np = of_find_matching_node(NULL, shdwc_ids);
397         if (!np) {
398                 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
399                 return;
400         }
401
402         at91_shdwc_base = of_iomap(np, 0);
403         if (!at91_shdwc_base)
404                 panic("AT91: unable to map shdwc cpu registers\n");
405
406         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
407         if (wakeup_mode < 0) {
408                 pr_warn("AT91: shdwc unknown wakeup mode\n");
409                 goto end;
410         }
411
412         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
413                 if (reg > AT91_SHDW_CPTWK0_MAX) {
414                         pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
415                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
416                         reg = AT91_SHDW_CPTWK0_MAX;
417                 }
418                 mode |= AT91_SHDW_CPTWK0_(reg);
419         }
420
421         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
422                         mode |= AT91_SHDW_RTCWKEN;
423
424         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
425                         mode |= AT91_SHDW_RTTWKEN;
426
427         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
428
429 end:
430         pm_power_off = at91sam9_poweroff;
431
432         of_node_put(np);
433 }
434
435 void __init at91_dt_initialize(void)
436 {
437         at91_dt_rstc();
438         at91_dt_ramc();
439         at91_dt_shdwc();
440
441         /* Init clock subsystem */
442         at91_dt_clock_init();
443
444         /* Register the processor-specific clocks */
445         at91_boot_soc.register_clocks();
446
447         at91_boot_soc.init();
448 }
449 #endif
450
451 void __init at91_initialize(unsigned long main_clock)
452 {
453         at91_boot_soc.ioremap_registers();
454
455         /* Init clock subsystem */
456         at91_clock_init(main_clock);
457
458         /* Register the processor-specific clocks */
459         at91_boot_soc.register_clocks();
460
461         at91_boot_soc.init();
462 }