ARM: at91: make sdram/ddr register base soc independent
[linux-2.6.git] / arch / arm / mach-at91 / pm.c
1 /*
2  * arch/arm/mach-at91/pm.c
3  * AT91 Power Management
4  *
5  * Copyright (C) 2005 David Brownell
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  */
12
13 #include <linux/gpio.h>
14 #include <linux/suspend.h>
15 #include <linux/sched.h>
16 #include <linux/proc_fs.h>
17 #include <linux/interrupt.h>
18 #include <linux/sysfs.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/io.h>
22
23 #include <asm/irq.h>
24 #include <linux/atomic.h>
25 #include <asm/mach/time.h>
26 #include <asm/mach/irq.h>
27
28 #include <mach/at91_pmc.h>
29 #include <mach/cpu.h>
30
31 #include "generic.h"
32 #include "pm.h"
33
34 /*
35  * Show the reason for the previous system reset.
36  */
37
38 #include <mach/at91_rstc.h>
39 #include <mach/at91_shdwc.h>
40
41 static void __init show_reset_status(void)
42 {
43         static char reset[] __initdata = "reset";
44
45         static char general[] __initdata = "general";
46         static char wakeup[] __initdata = "wakeup";
47         static char watchdog[] __initdata = "watchdog";
48         static char software[] __initdata = "software";
49         static char user[] __initdata = "user";
50         static char unknown[] __initdata = "unknown";
51
52         static char signal[] __initdata = "signal";
53         static char rtc[] __initdata = "rtc";
54         static char rtt[] __initdata = "rtt";
55         static char restore[] __initdata = "power-restored";
56
57         char *reason, *r2 = reset;
58         u32 reset_type, wake_type;
59
60         if (!at91_shdwc_base || !at91_rstc_base)
61                 return;
62
63         reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
64         wake_type = at91_shdwc_read(AT91_SHDW_SR);
65
66         switch (reset_type) {
67         case AT91_RSTC_RSTTYP_GENERAL:
68                 reason = general;
69                 break;
70         case AT91_RSTC_RSTTYP_WAKEUP:
71                 /* board-specific code enabled the wakeup sources */
72                 reason = wakeup;
73
74                 /* "wakeup signal" */
75                 if (wake_type & AT91_SHDW_WAKEUP0)
76                         r2 = signal;
77                 else {
78                         r2 = reason;
79                         if (wake_type & AT91_SHDW_RTTWK)        /* rtt wakeup */
80                                 reason = rtt;
81                         else if (wake_type & AT91_SHDW_RTCWK)   /* rtc wakeup */
82                                 reason = rtc;
83                         else if (wake_type == 0)        /* power-restored wakeup */
84                                 reason = restore;
85                         else                            /* unknown wakeup */
86                                 reason = unknown;
87                 }
88                 break;
89         case AT91_RSTC_RSTTYP_WATCHDOG:
90                 reason = watchdog;
91                 break;
92         case AT91_RSTC_RSTTYP_SOFTWARE:
93                 reason = software;
94                 break;
95         case AT91_RSTC_RSTTYP_USER:
96                 reason = user;
97                 break;
98         default:
99                 reason = unknown;
100                 break;
101         }
102         pr_info("AT91: Starting after %s %s\n", reason, r2);
103 }
104
105 static int at91_pm_valid_state(suspend_state_t state)
106 {
107         switch (state) {
108                 case PM_SUSPEND_ON:
109                 case PM_SUSPEND_STANDBY:
110                 case PM_SUSPEND_MEM:
111                         return 1;
112
113                 default:
114                         return 0;
115         }
116 }
117
118
119 static suspend_state_t target_state;
120
121 /*
122  * Called after processes are frozen, but before we shutdown devices.
123  */
124 static int at91_pm_begin(suspend_state_t state)
125 {
126         target_state = state;
127         return 0;
128 }
129
130 /*
131  * Verify that all the clocks are correct before entering
132  * slow-clock mode.
133  */
134 static int at91_pm_verify_clocks(void)
135 {
136         unsigned long scsr;
137         int i;
138
139         scsr = at91_sys_read(AT91_PMC_SCSR);
140
141         /* USB must not be using PLLB */
142         if (cpu_is_at91rm9200()) {
143                 if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
144                         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
145                         return 0;
146                 }
147         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
148                         || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
149                 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
150                         pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
151                         return 0;
152                 }
153         }
154
155 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
156         /* PCK0..PCK3 must be disabled, or configured to use clk32k */
157         for (i = 0; i < 4; i++) {
158                 u32 css;
159
160                 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
161                         continue;
162
163                 css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
164                 if (css != AT91_PMC_CSS_SLOW) {
165                         pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
166                         return 0;
167                 }
168         }
169 #endif
170
171         return 1;
172 }
173
174 /*
175  * Call this from platform driver suspend() to see how deeply to suspend.
176  * For example, some controllers (like OHCI) need one of the PLL clocks
177  * in order to act as a wakeup source, and those are not available when
178  * going into slow clock mode.
179  *
180  * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
181  * the very same problem (but not using at91 main_clk), and it'd be better
182  * to add one generic API rather than lots of platform-specific ones.
183  */
184 int at91_suspend_entering_slow_clock(void)
185 {
186         return (target_state == PM_SUSPEND_MEM);
187 }
188 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
189
190
191 static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1);
192
193 #ifdef CONFIG_AT91_SLOW_CLOCK
194 extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1);
195 extern u32 at91_slow_clock_sz;
196 #endif
197
198 static void __iomem *at91_pmc_base = (void __iomem*)(AT91_VA_BASE_SYS + AT91_PMC);
199 void __iomem *at91_ramc_base[2];
200
201 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
202 {
203         if (id < 0 || id > 1) {
204                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
205                 BUG();
206         }
207         at91_ramc_base[id] = ioremap(addr, size);
208         if (!at91_ramc_base[id])
209                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
210 }
211
212 static int at91_pm_enter(suspend_state_t state)
213 {
214         at91_gpio_suspend();
215         at91_irq_suspend();
216
217         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
218                         /* remember all the always-wake irqs */
219                         (at91_sys_read(AT91_PMC_PCSR)
220                                         | (1 << AT91_ID_FIQ)
221                                         | (1 << AT91_ID_SYS)
222                                         | (at91_extern_irq))
223                                 & at91_aic_read(AT91_AIC_IMR),
224                         state);
225
226         switch (state) {
227                 /*
228                  * Suspend-to-RAM is like STANDBY plus slow clock mode, so
229                  * drivers must suspend more deeply:  only the master clock
230                  * controller may be using the main oscillator.
231                  */
232                 case PM_SUSPEND_MEM:
233                         /*
234                          * Ensure that clocks are in a valid state.
235                          */
236                         if (!at91_pm_verify_clocks())
237                                 goto error;
238
239                         /*
240                          * Enter slow clock mode by switching over to clk32k and
241                          * turning off the main oscillator; reverse on wakeup.
242                          */
243                         if (slow_clock) {
244 #ifdef CONFIG_AT91_SLOW_CLOCK
245                                 /* copy slow_clock handler to SRAM, and call it */
246                                 memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
247 #endif
248                                 slow_clock(at91_pmc_base, at91_ramc_base[0], at91_ramc_base[1]);
249                                 break;
250                         } else {
251                                 pr_info("AT91: PM - no slow clock mode enabled ...\n");
252                                 /* FALLTHROUGH leaving master clock alone */
253                         }
254
255                 /*
256                  * STANDBY mode has *all* drivers suspended; ignores irqs not
257                  * marked as 'wakeup' event sources; and reduces DRAM power.
258                  * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
259                  * nothing fancy done with main or cpu clocks.
260                  */
261                 case PM_SUSPEND_STANDBY:
262                         /*
263                          * NOTE: the Wait-for-Interrupt instruction needs to be
264                          * in icache so no SDRAM accesses are needed until the
265                          * wakeup IRQ occurs and self-refresh is terminated.
266                          * For ARM 926 based chips, this requirement is weaker
267                          * as at91sam9 can access a RAM in self-refresh mode.
268                          */
269                         at91_standby();
270                         break;
271
272                 case PM_SUSPEND_ON:
273                         cpu_do_idle();
274                         break;
275
276                 default:
277                         pr_debug("AT91: PM - bogus suspend state %d\n", state);
278                         goto error;
279         }
280
281         pr_debug("AT91: PM - wakeup %08x\n",
282                         at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
283
284 error:
285         target_state = PM_SUSPEND_ON;
286         at91_irq_resume();
287         at91_gpio_resume();
288         return 0;
289 }
290
291 /*
292  * Called right prior to thawing processes.
293  */
294 static void at91_pm_end(void)
295 {
296         target_state = PM_SUSPEND_ON;
297 }
298
299
300 static const struct platform_suspend_ops at91_pm_ops = {
301         .valid  = at91_pm_valid_state,
302         .begin  = at91_pm_begin,
303         .enter  = at91_pm_enter,
304         .end    = at91_pm_end,
305 };
306
307 static int __init at91_pm_init(void)
308 {
309 #ifdef CONFIG_AT91_SLOW_CLOCK
310         slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
311 #endif
312
313         pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
314
315 #ifdef CONFIG_ARCH_AT91RM9200
316         /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
317         at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
318 #endif
319
320         suspend_set_ops(&at91_pm_ops);
321
322         show_reset_status();
323         return 0;
324 }
325 arch_initcall(at91_pm_init);