Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6.git] / arch / arm / mach-at91 / include / mach / at91sam9g45.h
1 /*
2  * Chip-specific header file for the AT91SAM9G45 family
3  *
4  *  Copyright (C) 2008-2009 Atmel Corporation.
5  *
6  * Common definitions.
7  * Based on AT91SAM9G45 preliminary datasheet.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14
15 #ifndef AT91SAM9G45_H
16 #define AT91SAM9G45_H
17
18 /*
19  * Peripheral identifiers/interrupts.
20  */
21 #define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
22 #define AT91_ID_SYS             1       /* System Controller Interrupt */
23 #define AT91SAM9G45_ID_PIOA     2       /* Parallel I/O Controller A */
24 #define AT91SAM9G45_ID_PIOB     3       /* Parallel I/O Controller B */
25 #define AT91SAM9G45_ID_PIOC     4       /* Parallel I/O Controller C */
26 #define AT91SAM9G45_ID_PIODE    5       /* Parallel I/O Controller D and E */
27 #define AT91SAM9G45_ID_TRNG     6       /* True Random Number Generator */
28 #define AT91SAM9G45_ID_US0      7       /* USART 0 */
29 #define AT91SAM9G45_ID_US1      8       /* USART 1 */
30 #define AT91SAM9G45_ID_US2      9       /* USART 2 */
31 #define AT91SAM9G45_ID_US3      10      /* USART 3 */
32 #define AT91SAM9G45_ID_MCI0     11      /* High Speed Multimedia Card Interface 0 */
33 #define AT91SAM9G45_ID_TWI0     12      /* Two-Wire Interface 0 */
34 #define AT91SAM9G45_ID_TWI1     13      /* Two-Wire Interface 1 */
35 #define AT91SAM9G45_ID_SPI0     14      /* Serial Peripheral Interface 0 */
36 #define AT91SAM9G45_ID_SPI1     15      /* Serial Peripheral Interface 1 */
37 #define AT91SAM9G45_ID_SSC0     16      /* Synchronous Serial Controller 0 */
38 #define AT91SAM9G45_ID_SSC1     17      /* Synchronous Serial Controller 1 */
39 #define AT91SAM9G45_ID_TCB      18      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
40 #define AT91SAM9G45_ID_PWMC     19      /* Pulse Width Modulation Controller */
41 #define AT91SAM9G45_ID_TSC      20      /* Touch Screen ADC Controller */
42 #define AT91SAM9G45_ID_DMA      21      /* DMA Controller */
43 #define AT91SAM9G45_ID_UHPHS    22      /* USB Host High Speed */
44 #define AT91SAM9G45_ID_LCDC     23      /* LCD Controller */
45 #define AT91SAM9G45_ID_AC97C    24      /* AC97 Controller */
46 #define AT91SAM9G45_ID_EMAC     25      /* Ethernet MAC */
47 #define AT91SAM9G45_ID_ISI      26      /* Image Sensor Interface */
48 #define AT91SAM9G45_ID_UDPHS    27      /* USB Device High Speed */
49 #define AT91SAM9G45_ID_AESTDESSHA 28    /* AES + T-DES + SHA */
50 #define AT91SAM9G45_ID_MCI1     29      /* High Speed Multimedia Card Interface 1 */
51 #define AT91SAM9G45_ID_VDEC     30      /* Video Decoder */
52 #define AT91SAM9G45_ID_IRQ0     31      /* Advanced Interrupt Controller */
53
54 /*
55  * User Peripheral physical base addresses.
56  */
57 #define AT91SAM9G45_BASE_UDPHS          0xfff78000
58 #define AT91SAM9G45_BASE_TCB0           0xfff7c000
59 #define AT91SAM9G45_BASE_TC0            0xfff7c000
60 #define AT91SAM9G45_BASE_TC1            0xfff7c040
61 #define AT91SAM9G45_BASE_TC2            0xfff7c080
62 #define AT91SAM9G45_BASE_MCI0           0xfff80000
63 #define AT91SAM9G45_BASE_TWI0           0xfff84000
64 #define AT91SAM9G45_BASE_TWI1           0xfff88000
65 #define AT91SAM9G45_BASE_US0            0xfff8c000
66 #define AT91SAM9G45_BASE_US1            0xfff90000
67 #define AT91SAM9G45_BASE_US2            0xfff94000
68 #define AT91SAM9G45_BASE_US3            0xfff98000
69 #define AT91SAM9G45_BASE_SSC0           0xfff9c000
70 #define AT91SAM9G45_BASE_SSC1           0xfffa0000
71 #define AT91SAM9G45_BASE_SPI0           0xfffa4000
72 #define AT91SAM9G45_BASE_SPI1           0xfffa8000
73 #define AT91SAM9G45_BASE_AC97C          0xfffac000
74 #define AT91SAM9G45_BASE_TSC            0xfffb0000
75 #define AT91SAM9G45_BASE_ISI            0xfffb4000
76 #define AT91SAM9G45_BASE_PWMC           0xfffb8000
77 #define AT91SAM9G45_BASE_EMAC           0xfffbc000
78 #define AT91SAM9G45_BASE_AES            0xfffc0000
79 #define AT91SAM9G45_BASE_TDES           0xfffc4000
80 #define AT91SAM9G45_BASE_SHA            0xfffc8000
81 #define AT91SAM9G45_BASE_TRNG           0xfffcc000
82 #define AT91SAM9G45_BASE_MCI1           0xfffd0000
83 #define AT91SAM9G45_BASE_TCB1           0xfffd4000
84 #define AT91SAM9G45_BASE_TC3            0xfffd4000
85 #define AT91SAM9G45_BASE_TC4            0xfffd4040
86 #define AT91SAM9G45_BASE_TC5            0xfffd4080
87 #define AT91_BASE_SYS                   0xffffe200
88
89 /*
90  * System Peripherals (offset from AT91_BASE_SYS)
91  */
92 #define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
93 #define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
94 #define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
95 #define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
96 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
97 #define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
98 #define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
99 #define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
100 #define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
101 #define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
102 #define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
103 #define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
104 #define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
105 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
106 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
107 #define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
108 #define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
109 #define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
110 #define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
111 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
112 #define AT91_RTC        (0xfffffdb0 - AT91_BASE_SYS)
113
114 #define AT91_USART0     AT91SAM9G45_BASE_US0
115 #define AT91_USART1     AT91SAM9G45_BASE_US1
116 #define AT91_USART2     AT91SAM9G45_BASE_US2
117 #define AT91_USART3     AT91SAM9G45_BASE_US3
118
119 /*
120  * Internal Memory.
121  */
122 #define AT91SAM9G45_SRAM_BASE   0x00300000      /* Internal SRAM base address */
123 #define AT91SAM9G45_SRAM_SIZE   SZ_64K          /* Internal SRAM size (64Kb) */
124
125 #define AT91SAM9G45_ROM_BASE    0x00400000      /* Internal ROM base address */
126 #define AT91SAM9G45_ROM_SIZE    SZ_64K          /* Internal ROM size (64Kb) */
127
128 #define AT91SAM9G45_LCDC_BASE   0x00500000      /* LCD Controller */
129 #define AT91SAM9G45_UDPHS_FIFO  0x00600000      /* USB Device HS controller */
130 #define AT91SAM9G45_OHCI_BASE   0x00700000      /* USB Host controller (OHCI) */
131 #define AT91SAM9G45_EHCI_BASE   0x00800000      /* USB Host controller (EHCI) */
132 #define AT91SAM9G45_VDEC_BASE   0x00900000      /* Video Decoder Controller */
133
134 #define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
135
136 #define CONSISTENT_DMA_SIZE     SZ_4M
137
138 /*
139  * DMA peripheral identifiers
140  * for hardware handshaking interface
141  */
142 #define AT_DMA_ID_MCI0           0
143 #define AT_DMA_ID_SPI0_TX        1
144 #define AT_DMA_ID_SPI0_RX        2
145 #define AT_DMA_ID_SPI1_TX        3
146 #define AT_DMA_ID_SPI1_RX        4
147 #define AT_DMA_ID_SSC0_TX        5
148 #define AT_DMA_ID_SSC0_RX        6
149 #define AT_DMA_ID_SSC1_TX        7
150 #define AT_DMA_ID_SSC1_RX        8
151 #define AT_DMA_ID_AC97_TX        9
152 #define AT_DMA_ID_AC97_RX       10
153 #define AT_DMA_ID_MCI1          13
154
155 #endif