ARM: at91: make sdram/ddr register base soc independent
[linux-2.6.git] / arch / arm / mach-at91 / at91sam9rl.c
1 /*
2  * arch/arm/mach-at91/at91sam9rl.c
3  *
4  *  Copyright (C) 2005 SAN People
5  *  Copyright (C) 2007 Atmel Corporation
6  *
7  * This file is subject to the terms and conditions of the GNU General Public
8  * License.  See the file COPYING in the main directory of this archive for
9  * more details.
10  */
11
12 #include <linux/module.h>
13
14 #include <asm/proc-fns.h>
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <mach/cpu.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91sam9rl.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23
24 #include "soc.h"
25 #include "generic.h"
26 #include "clock.h"
27 #include "sam9_smc.h"
28
29 /* --------------------------------------------------------------------
30  *  Clocks
31  * -------------------------------------------------------------------- */
32
33 /*
34  * The peripheral clocks.
35  */
36 static struct clk pioA_clk = {
37         .name           = "pioA_clk",
38         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOA,
39         .type           = CLK_TYPE_PERIPHERAL,
40 };
41 static struct clk pioB_clk = {
42         .name           = "pioB_clk",
43         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOB,
44         .type           = CLK_TYPE_PERIPHERAL,
45 };
46 static struct clk pioC_clk = {
47         .name           = "pioC_clk",
48         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOC,
49         .type           = CLK_TYPE_PERIPHERAL,
50 };
51 static struct clk pioD_clk = {
52         .name           = "pioD_clk",
53         .pmc_mask       = 1 << AT91SAM9RL_ID_PIOD,
54         .type           = CLK_TYPE_PERIPHERAL,
55 };
56 static struct clk usart0_clk = {
57         .name           = "usart0_clk",
58         .pmc_mask       = 1 << AT91SAM9RL_ID_US0,
59         .type           = CLK_TYPE_PERIPHERAL,
60 };
61 static struct clk usart1_clk = {
62         .name           = "usart1_clk",
63         .pmc_mask       = 1 << AT91SAM9RL_ID_US1,
64         .type           = CLK_TYPE_PERIPHERAL,
65 };
66 static struct clk usart2_clk = {
67         .name           = "usart2_clk",
68         .pmc_mask       = 1 << AT91SAM9RL_ID_US2,
69         .type           = CLK_TYPE_PERIPHERAL,
70 };
71 static struct clk usart3_clk = {
72         .name           = "usart3_clk",
73         .pmc_mask       = 1 << AT91SAM9RL_ID_US3,
74         .type           = CLK_TYPE_PERIPHERAL,
75 };
76 static struct clk mmc_clk = {
77         .name           = "mci_clk",
78         .pmc_mask       = 1 << AT91SAM9RL_ID_MCI,
79         .type           = CLK_TYPE_PERIPHERAL,
80 };
81 static struct clk twi0_clk = {
82         .name           = "twi0_clk",
83         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI0,
84         .type           = CLK_TYPE_PERIPHERAL,
85 };
86 static struct clk twi1_clk = {
87         .name           = "twi1_clk",
88         .pmc_mask       = 1 << AT91SAM9RL_ID_TWI1,
89         .type           = CLK_TYPE_PERIPHERAL,
90 };
91 static struct clk spi_clk = {
92         .name           = "spi_clk",
93         .pmc_mask       = 1 << AT91SAM9RL_ID_SPI,
94         .type           = CLK_TYPE_PERIPHERAL,
95 };
96 static struct clk ssc0_clk = {
97         .name           = "ssc0_clk",
98         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC0,
99         .type           = CLK_TYPE_PERIPHERAL,
100 };
101 static struct clk ssc1_clk = {
102         .name           = "ssc1_clk",
103         .pmc_mask       = 1 << AT91SAM9RL_ID_SSC1,
104         .type           = CLK_TYPE_PERIPHERAL,
105 };
106 static struct clk tc0_clk = {
107         .name           = "tc0_clk",
108         .pmc_mask       = 1 << AT91SAM9RL_ID_TC0,
109         .type           = CLK_TYPE_PERIPHERAL,
110 };
111 static struct clk tc1_clk = {
112         .name           = "tc1_clk",
113         .pmc_mask       = 1 << AT91SAM9RL_ID_TC1,
114         .type           = CLK_TYPE_PERIPHERAL,
115 };
116 static struct clk tc2_clk = {
117         .name           = "tc2_clk",
118         .pmc_mask       = 1 << AT91SAM9RL_ID_TC2,
119         .type           = CLK_TYPE_PERIPHERAL,
120 };
121 static struct clk pwm_clk = {
122         .name           = "pwm_clk",
123         .pmc_mask       = 1 << AT91SAM9RL_ID_PWMC,
124         .type           = CLK_TYPE_PERIPHERAL,
125 };
126 static struct clk tsc_clk = {
127         .name           = "tsc_clk",
128         .pmc_mask       = 1 << AT91SAM9RL_ID_TSC,
129         .type           = CLK_TYPE_PERIPHERAL,
130 };
131 static struct clk dma_clk = {
132         .name           = "dma_clk",
133         .pmc_mask       = 1 << AT91SAM9RL_ID_DMA,
134         .type           = CLK_TYPE_PERIPHERAL,
135 };
136 static struct clk udphs_clk = {
137         .name           = "udphs_clk",
138         .pmc_mask       = 1 << AT91SAM9RL_ID_UDPHS,
139         .type           = CLK_TYPE_PERIPHERAL,
140 };
141 static struct clk lcdc_clk = {
142         .name           = "lcdc_clk",
143         .pmc_mask       = 1 << AT91SAM9RL_ID_LCDC,
144         .type           = CLK_TYPE_PERIPHERAL,
145 };
146 static struct clk ac97_clk = {
147         .name           = "ac97_clk",
148         .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
149         .type           = CLK_TYPE_PERIPHERAL,
150 };
151
152 static struct clk *periph_clocks[] __initdata = {
153         &pioA_clk,
154         &pioB_clk,
155         &pioC_clk,
156         &pioD_clk,
157         &usart0_clk,
158         &usart1_clk,
159         &usart2_clk,
160         &usart3_clk,
161         &mmc_clk,
162         &twi0_clk,
163         &twi1_clk,
164         &spi_clk,
165         &ssc0_clk,
166         &ssc1_clk,
167         &tc0_clk,
168         &tc1_clk,
169         &tc2_clk,
170         &pwm_clk,
171         &tsc_clk,
172         &dma_clk,
173         &udphs_clk,
174         &lcdc_clk,
175         &ac97_clk,
176         // irq0
177 };
178
179 static struct clk_lookup periph_clocks_lookups[] = {
180         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
181         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
182         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
183         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
184         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
185         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
186         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
187         CLKDEV_CON_ID("pioA", &pioA_clk),
188         CLKDEV_CON_ID("pioB", &pioB_clk),
189         CLKDEV_CON_ID("pioC", &pioC_clk),
190         CLKDEV_CON_ID("pioD", &pioD_clk),
191 };
192
193 static struct clk_lookup usart_clocks_lookups[] = {
194         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
195         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
196         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
197         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
198         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
199 };
200
201 /*
202  * The two programmable clocks.
203  * You must configure pin multiplexing to bring these signals out.
204  */
205 static struct clk pck0 = {
206         .name           = "pck0",
207         .pmc_mask       = AT91_PMC_PCK0,
208         .type           = CLK_TYPE_PROGRAMMABLE,
209         .id             = 0,
210 };
211 static struct clk pck1 = {
212         .name           = "pck1",
213         .pmc_mask       = AT91_PMC_PCK1,
214         .type           = CLK_TYPE_PROGRAMMABLE,
215         .id             = 1,
216 };
217
218 static void __init at91sam9rl_register_clocks(void)
219 {
220         int i;
221
222         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
223                 clk_register(periph_clocks[i]);
224
225         clkdev_add_table(periph_clocks_lookups,
226                          ARRAY_SIZE(periph_clocks_lookups));
227         clkdev_add_table(usart_clocks_lookups,
228                          ARRAY_SIZE(usart_clocks_lookups));
229
230         clk_register(&pck0);
231         clk_register(&pck1);
232 }
233
234 static struct clk_lookup console_clock_lookup;
235
236 void __init at91sam9rl_set_console_clock(int id)
237 {
238         if (id >= ARRAY_SIZE(usart_clocks_lookups))
239                 return;
240
241         console_clock_lookup.con_id = "usart";
242         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
243         clkdev_add(&console_clock_lookup);
244 }
245
246 /* --------------------------------------------------------------------
247  *  GPIO
248  * -------------------------------------------------------------------- */
249
250 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
251         {
252                 .id             = AT91SAM9RL_ID_PIOA,
253                 .regbase        = AT91SAM9RL_BASE_PIOA,
254         }, {
255                 .id             = AT91SAM9RL_ID_PIOB,
256                 .regbase        = AT91SAM9RL_BASE_PIOB,
257         }, {
258                 .id             = AT91SAM9RL_ID_PIOC,
259                 .regbase        = AT91SAM9RL_BASE_PIOC,
260         }, {
261                 .id             = AT91SAM9RL_ID_PIOD,
262                 .regbase        = AT91SAM9RL_BASE_PIOD,
263         }
264 };
265
266 /* --------------------------------------------------------------------
267  *  AT91SAM9RL processor initialization
268  * -------------------------------------------------------------------- */
269
270 static void __init at91sam9rl_map_io(void)
271 {
272         unsigned long sram_size;
273
274         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
275                 case AT91_CIDR_SRAMSIZ_32K:
276                         sram_size = 2 * SZ_16K;
277                         break;
278                 case AT91_CIDR_SRAMSIZ_16K:
279                 default:
280                         sram_size = SZ_16K;
281         }
282
283         /* Map SRAM */
284         at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
285 }
286
287 static void __init at91sam9rl_ioremap_registers(void)
288 {
289         at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
290         at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
291         at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
292         at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
293         at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
294         at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
295 }
296
297 static void __init at91sam9rl_initialize(void)
298 {
299         arm_pm_idle = at91sam9_idle;
300         arm_pm_restart = at91sam9_alt_restart;
301         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
302
303         /* Register GPIO subsystem */
304         at91_gpio_init(at91sam9rl_gpio, 4);
305 }
306
307 /* --------------------------------------------------------------------
308  *  Interrupt initialization
309  * -------------------------------------------------------------------- */
310
311 /*
312  * The default interrupt priority levels (0 = lowest, 7 = highest).
313  */
314 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
315         7,      /* Advanced Interrupt Controller */
316         7,      /* System Peripherals */
317         1,      /* Parallel IO Controller A */
318         1,      /* Parallel IO Controller B */
319         1,      /* Parallel IO Controller C */
320         1,      /* Parallel IO Controller D */
321         5,      /* USART 0 */
322         5,      /* USART 1 */
323         5,      /* USART 2 */
324         5,      /* USART 3 */
325         0,      /* Multimedia Card Interface */
326         6,      /* Two-Wire Interface 0 */
327         6,      /* Two-Wire Interface 1 */
328         5,      /* Serial Peripheral Interface */
329         4,      /* Serial Synchronous Controller 0 */
330         4,      /* Serial Synchronous Controller 1 */
331         0,      /* Timer Counter 0 */
332         0,      /* Timer Counter 1 */
333         0,      /* Timer Counter 2 */
334         0,
335         0,      /* Touch Screen Controller */
336         0,      /* DMA Controller */
337         2,      /* USB Device High speed port */
338         2,      /* LCD Controller */
339         6,      /* AC97 Controller */
340         0,
341         0,
342         0,
343         0,
344         0,
345         0,
346         0,      /* Advanced Interrupt Controller */
347 };
348
349 struct at91_init_soc __initdata at91sam9rl_soc = {
350         .map_io = at91sam9rl_map_io,
351         .default_irq_priority = at91sam9rl_default_irq_priority,
352         .ioremap_registers = at91sam9rl_ioremap_registers,
353         .register_clocks = at91sam9rl_register_clocks,
354         .init = at91sam9rl_initialize,
355 };