Merge tag 'split-asm_system_h-for-linus-20120328' of git://git.kernel.org/pub/scm...
[linux-2.6.git] / arch / arm / mach-at91 / at91sam9g45.c
1 /*
2  *  Chip-specific setup code for the AT91SAM9G45 family
3  *
4  *  Copyright (C) 2009 Atmel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  */
12
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9g45.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/cpu.h>
23
24 #include "soc.h"
25 #include "generic.h"
26 #include "clock.h"
27 #include "sam9_smc.h"
28
29 /* --------------------------------------------------------------------
30  *  Clocks
31  * -------------------------------------------------------------------- */
32
33 /*
34  * The peripheral clocks.
35  */
36 static struct clk pioA_clk = {
37         .name           = "pioA_clk",
38         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOA,
39         .type           = CLK_TYPE_PERIPHERAL,
40 };
41 static struct clk pioB_clk = {
42         .name           = "pioB_clk",
43         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOB,
44         .type           = CLK_TYPE_PERIPHERAL,
45 };
46 static struct clk pioC_clk = {
47         .name           = "pioC_clk",
48         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOC,
49         .type           = CLK_TYPE_PERIPHERAL,
50 };
51 static struct clk pioDE_clk = {
52         .name           = "pioDE_clk",
53         .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
54         .type           = CLK_TYPE_PERIPHERAL,
55 };
56 static struct clk trng_clk = {
57         .name           = "trng_clk",
58         .pmc_mask       = 1 << AT91SAM9G45_ID_TRNG,
59         .type           = CLK_TYPE_PERIPHERAL,
60 };
61 static struct clk usart0_clk = {
62         .name           = "usart0_clk",
63         .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
64         .type           = CLK_TYPE_PERIPHERAL,
65 };
66 static struct clk usart1_clk = {
67         .name           = "usart1_clk",
68         .pmc_mask       = 1 << AT91SAM9G45_ID_US1,
69         .type           = CLK_TYPE_PERIPHERAL,
70 };
71 static struct clk usart2_clk = {
72         .name           = "usart2_clk",
73         .pmc_mask       = 1 << AT91SAM9G45_ID_US2,
74         .type           = CLK_TYPE_PERIPHERAL,
75 };
76 static struct clk usart3_clk = {
77         .name           = "usart3_clk",
78         .pmc_mask       = 1 << AT91SAM9G45_ID_US3,
79         .type           = CLK_TYPE_PERIPHERAL,
80 };
81 static struct clk mmc0_clk = {
82         .name           = "mci0_clk",
83         .pmc_mask       = 1 << AT91SAM9G45_ID_MCI0,
84         .type           = CLK_TYPE_PERIPHERAL,
85 };
86 static struct clk twi0_clk = {
87         .name           = "twi0_clk",
88         .pmc_mask       = 1 << AT91SAM9G45_ID_TWI0,
89         .type           = CLK_TYPE_PERIPHERAL,
90 };
91 static struct clk twi1_clk = {
92         .name           = "twi1_clk",
93         .pmc_mask       = 1 << AT91SAM9G45_ID_TWI1,
94         .type           = CLK_TYPE_PERIPHERAL,
95 };
96 static struct clk spi0_clk = {
97         .name           = "spi0_clk",
98         .pmc_mask       = 1 << AT91SAM9G45_ID_SPI0,
99         .type           = CLK_TYPE_PERIPHERAL,
100 };
101 static struct clk spi1_clk = {
102         .name           = "spi1_clk",
103         .pmc_mask       = 1 << AT91SAM9G45_ID_SPI1,
104         .type           = CLK_TYPE_PERIPHERAL,
105 };
106 static struct clk ssc0_clk = {
107         .name           = "ssc0_clk",
108         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC0,
109         .type           = CLK_TYPE_PERIPHERAL,
110 };
111 static struct clk ssc1_clk = {
112         .name           = "ssc1_clk",
113         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
114         .type           = CLK_TYPE_PERIPHERAL,
115 };
116 static struct clk tcb0_clk = {
117         .name           = "tcb0_clk",
118         .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
119         .type           = CLK_TYPE_PERIPHERAL,
120 };
121 static struct clk pwm_clk = {
122         .name           = "pwm_clk",
123         .pmc_mask       = 1 << AT91SAM9G45_ID_PWMC,
124         .type           = CLK_TYPE_PERIPHERAL,
125 };
126 static struct clk tsc_clk = {
127         .name           = "tsc_clk",
128         .pmc_mask       = 1 << AT91SAM9G45_ID_TSC,
129         .type           = CLK_TYPE_PERIPHERAL,
130 };
131 static struct clk dma_clk = {
132         .name           = "dma_clk",
133         .pmc_mask       = 1 << AT91SAM9G45_ID_DMA,
134         .type           = CLK_TYPE_PERIPHERAL,
135 };
136 static struct clk uhphs_clk = {
137         .name           = "uhphs_clk",
138         .pmc_mask       = 1 << AT91SAM9G45_ID_UHPHS,
139         .type           = CLK_TYPE_PERIPHERAL,
140 };
141 static struct clk lcdc_clk = {
142         .name           = "lcdc_clk",
143         .pmc_mask       = 1 << AT91SAM9G45_ID_LCDC,
144         .type           = CLK_TYPE_PERIPHERAL,
145 };
146 static struct clk ac97_clk = {
147         .name           = "ac97_clk",
148         .pmc_mask       = 1 << AT91SAM9G45_ID_AC97C,
149         .type           = CLK_TYPE_PERIPHERAL,
150 };
151 static struct clk macb_clk = {
152         .name           = "pclk",
153         .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
154         .type           = CLK_TYPE_PERIPHERAL,
155 };
156 static struct clk isi_clk = {
157         .name           = "isi_clk",
158         .pmc_mask       = 1 << AT91SAM9G45_ID_ISI,
159         .type           = CLK_TYPE_PERIPHERAL,
160 };
161 static struct clk udphs_clk = {
162         .name           = "udphs_clk",
163         .pmc_mask       = 1 << AT91SAM9G45_ID_UDPHS,
164         .type           = CLK_TYPE_PERIPHERAL,
165 };
166 static struct clk mmc1_clk = {
167         .name           = "mci1_clk",
168         .pmc_mask       = 1 << AT91SAM9G45_ID_MCI1,
169         .type           = CLK_TYPE_PERIPHERAL,
170 };
171
172 /* Video decoder clock - Only for sam9m10/sam9m11 */
173 static struct clk vdec_clk = {
174         .name           = "vdec_clk",
175         .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
176         .type           = CLK_TYPE_PERIPHERAL,
177 };
178
179 static struct clk *periph_clocks[] __initdata = {
180         &pioA_clk,
181         &pioB_clk,
182         &pioC_clk,
183         &pioDE_clk,
184         &trng_clk,
185         &usart0_clk,
186         &usart1_clk,
187         &usart2_clk,
188         &usart3_clk,
189         &mmc0_clk,
190         &twi0_clk,
191         &twi1_clk,
192         &spi0_clk,
193         &spi1_clk,
194         &ssc0_clk,
195         &ssc1_clk,
196         &tcb0_clk,
197         &pwm_clk,
198         &tsc_clk,
199         &dma_clk,
200         &uhphs_clk,
201         &lcdc_clk,
202         &ac97_clk,
203         &macb_clk,
204         &isi_clk,
205         &udphs_clk,
206         &mmc1_clk,
207         // irq0
208 };
209
210 static struct clk_lookup periph_clocks_lookups[] = {
211         /* One additional fake clock for macb_hclk */
212         CLKDEV_CON_ID("hclk", &macb_clk),
213         /* One additional fake clock for ohci */
214         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
215         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
216         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
217         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
218         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
219         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
220         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
221         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
222         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
223         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
224         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
225         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
226         CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
227         /* more usart lookup table for DT entries */
228         CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
229         CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
230         CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
231         CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
232         CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
233         /* more tc lookup table for DT entries */
234         CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
235         CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
236         CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
237         CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
238         /* fake hclk clock */
239         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
240         CLKDEV_CON_ID("pioA", &pioA_clk),
241         CLKDEV_CON_ID("pioB", &pioB_clk),
242         CLKDEV_CON_ID("pioC", &pioC_clk),
243         CLKDEV_CON_ID("pioD", &pioDE_clk),
244         CLKDEV_CON_ID("pioE", &pioDE_clk),
245 };
246
247 static struct clk_lookup usart_clocks_lookups[] = {
248         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
249         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
250         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
251         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
252         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
253 };
254
255 /*
256  * The two programmable clocks.
257  * You must configure pin multiplexing to bring these signals out.
258  */
259 static struct clk pck0 = {
260         .name           = "pck0",
261         .pmc_mask       = AT91_PMC_PCK0,
262         .type           = CLK_TYPE_PROGRAMMABLE,
263         .id             = 0,
264 };
265 static struct clk pck1 = {
266         .name           = "pck1",
267         .pmc_mask       = AT91_PMC_PCK1,
268         .type           = CLK_TYPE_PROGRAMMABLE,
269         .id             = 1,
270 };
271
272 static void __init at91sam9g45_register_clocks(void)
273 {
274         int i;
275
276         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
277                 clk_register(periph_clocks[i]);
278
279         clkdev_add_table(periph_clocks_lookups,
280                          ARRAY_SIZE(periph_clocks_lookups));
281         clkdev_add_table(usart_clocks_lookups,
282                          ARRAY_SIZE(usart_clocks_lookups));
283
284         if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
285                 clk_register(&vdec_clk);
286
287         clk_register(&pck0);
288         clk_register(&pck1);
289 }
290
291 static struct clk_lookup console_clock_lookup;
292
293 void __init at91sam9g45_set_console_clock(int id)
294 {
295         if (id >= ARRAY_SIZE(usart_clocks_lookups))
296                 return;
297
298         console_clock_lookup.con_id = "usart";
299         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
300         clkdev_add(&console_clock_lookup);
301 }
302
303 /* --------------------------------------------------------------------
304  *  GPIO
305  * -------------------------------------------------------------------- */
306
307 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
308         {
309                 .id             = AT91SAM9G45_ID_PIOA,
310                 .regbase        = AT91SAM9G45_BASE_PIOA,
311         }, {
312                 .id             = AT91SAM9G45_ID_PIOB,
313                 .regbase        = AT91SAM9G45_BASE_PIOB,
314         }, {
315                 .id             = AT91SAM9G45_ID_PIOC,
316                 .regbase        = AT91SAM9G45_BASE_PIOC,
317         }, {
318                 .id             = AT91SAM9G45_ID_PIODE,
319                 .regbase        = AT91SAM9G45_BASE_PIOD,
320         }, {
321                 .id             = AT91SAM9G45_ID_PIODE,
322                 .regbase        = AT91SAM9G45_BASE_PIOE,
323         }
324 };
325
326 /* --------------------------------------------------------------------
327  *  AT91SAM9G45 processor initialization
328  * -------------------------------------------------------------------- */
329
330 static void __init at91sam9g45_map_io(void)
331 {
332         at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
333         init_consistent_dma_size(SZ_4M);
334 }
335
336 static void __init at91sam9g45_ioremap_registers(void)
337 {
338         at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
339         at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
340         at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
341         at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
342         at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
343         at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
344         at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
345 }
346
347 static void __init at91sam9g45_initialize(void)
348 {
349         arm_pm_idle = at91sam9_idle;
350         arm_pm_restart = at91sam9g45_restart;
351         at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
352
353         /* Register GPIO subsystem */
354         at91_gpio_init(at91sam9g45_gpio, 5);
355 }
356
357 /* --------------------------------------------------------------------
358  *  Interrupt initialization
359  * -------------------------------------------------------------------- */
360
361 /*
362  * The default interrupt priority levels (0 = lowest, 7 = highest).
363  */
364 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
365         7,      /* Advanced Interrupt Controller (FIQ) */
366         7,      /* System Peripherals */
367         1,      /* Parallel IO Controller A */
368         1,      /* Parallel IO Controller B */
369         1,      /* Parallel IO Controller C */
370         1,      /* Parallel IO Controller D and E */
371         0,
372         5,      /* USART 0 */
373         5,      /* USART 1 */
374         5,      /* USART 2 */
375         5,      /* USART 3 */
376         0,      /* Multimedia Card Interface 0 */
377         6,      /* Two-Wire Interface 0 */
378         6,      /* Two-Wire Interface 1 */
379         5,      /* Serial Peripheral Interface 0 */
380         5,      /* Serial Peripheral Interface 1 */
381         4,      /* Serial Synchronous Controller 0 */
382         4,      /* Serial Synchronous Controller 1 */
383         0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
384         0,      /* Pulse Width Modulation Controller */
385         0,      /* Touch Screen Controller */
386         0,      /* DMA Controller */
387         2,      /* USB Host High Speed port */
388         3,      /* LDC Controller */
389         5,      /* AC97 Controller */
390         3,      /* Ethernet */
391         0,      /* Image Sensor Interface */
392         2,      /* USB Device High speed port */
393         0,
394         0,      /* Multimedia Card Interface 1 */
395         0,
396         0,      /* Advanced Interrupt Controller (IRQ0) */
397 };
398
399 struct at91_init_soc __initdata at91sam9g45_soc = {
400         .map_io = at91sam9g45_map_io,
401         .default_irq_priority = at91sam9g45_default_irq_priority,
402         .ioremap_registers = at91sam9g45_ioremap_registers,
403         .register_clocks = at91sam9g45_register_clocks,
404         .init = at91sam9g45_initialize,
405 };