[SCSI] bnx2i: Fixed the endian on TTT for NOP out transmission
[linux-2.6.git] / arch / arm / mach-at91 / at91sam9261.c
1 /*
2  * arch/arm/mach-at91/at91sam9261.c
3  *
4  *  Copyright (C) 2005 SAN People
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  */
12
13 #include <linux/module.h>
14 #include <linux/pm.h>
15
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <mach/cpu.h>
20 #include <mach/at91sam9261.h>
21 #include <mach/at91_pmc.h>
22 #include <mach/at91_rstc.h>
23 #include <mach/at91_shdwc.h>
24
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
28
29 /* --------------------------------------------------------------------
30  *  Clocks
31  * -------------------------------------------------------------------- */
32
33 /*
34  * The peripheral clocks.
35  */
36 static struct clk pioA_clk = {
37         .name           = "pioA_clk",
38         .pmc_mask       = 1 << AT91SAM9261_ID_PIOA,
39         .type           = CLK_TYPE_PERIPHERAL,
40 };
41 static struct clk pioB_clk = {
42         .name           = "pioB_clk",
43         .pmc_mask       = 1 << AT91SAM9261_ID_PIOB,
44         .type           = CLK_TYPE_PERIPHERAL,
45 };
46 static struct clk pioC_clk = {
47         .name           = "pioC_clk",
48         .pmc_mask       = 1 << AT91SAM9261_ID_PIOC,
49         .type           = CLK_TYPE_PERIPHERAL,
50 };
51 static struct clk usart0_clk = {
52         .name           = "usart0_clk",
53         .pmc_mask       = 1 << AT91SAM9261_ID_US0,
54         .type           = CLK_TYPE_PERIPHERAL,
55 };
56 static struct clk usart1_clk = {
57         .name           = "usart1_clk",
58         .pmc_mask       = 1 << AT91SAM9261_ID_US1,
59         .type           = CLK_TYPE_PERIPHERAL,
60 };
61 static struct clk usart2_clk = {
62         .name           = "usart2_clk",
63         .pmc_mask       = 1 << AT91SAM9261_ID_US2,
64         .type           = CLK_TYPE_PERIPHERAL,
65 };
66 static struct clk mmc_clk = {
67         .name           = "mci_clk",
68         .pmc_mask       = 1 << AT91SAM9261_ID_MCI,
69         .type           = CLK_TYPE_PERIPHERAL,
70 };
71 static struct clk udc_clk = {
72         .name           = "udc_clk",
73         .pmc_mask       = 1 << AT91SAM9261_ID_UDP,
74         .type           = CLK_TYPE_PERIPHERAL,
75 };
76 static struct clk twi_clk = {
77         .name           = "twi_clk",
78         .pmc_mask       = 1 << AT91SAM9261_ID_TWI,
79         .type           = CLK_TYPE_PERIPHERAL,
80 };
81 static struct clk spi0_clk = {
82         .name           = "spi0_clk",
83         .pmc_mask       = 1 << AT91SAM9261_ID_SPI0,
84         .type           = CLK_TYPE_PERIPHERAL,
85 };
86 static struct clk spi1_clk = {
87         .name           = "spi1_clk",
88         .pmc_mask       = 1 << AT91SAM9261_ID_SPI1,
89         .type           = CLK_TYPE_PERIPHERAL,
90 };
91 static struct clk ssc0_clk = {
92         .name           = "ssc0_clk",
93         .pmc_mask       = 1 << AT91SAM9261_ID_SSC0,
94         .type           = CLK_TYPE_PERIPHERAL,
95 };
96 static struct clk ssc1_clk = {
97         .name           = "ssc1_clk",
98         .pmc_mask       = 1 << AT91SAM9261_ID_SSC1,
99         .type           = CLK_TYPE_PERIPHERAL,
100 };
101 static struct clk ssc2_clk = {
102         .name           = "ssc2_clk",
103         .pmc_mask       = 1 << AT91SAM9261_ID_SSC2,
104         .type           = CLK_TYPE_PERIPHERAL,
105 };
106 static struct clk tc0_clk = {
107         .name           = "tc0_clk",
108         .pmc_mask       = 1 << AT91SAM9261_ID_TC0,
109         .type           = CLK_TYPE_PERIPHERAL,
110 };
111 static struct clk tc1_clk = {
112         .name           = "tc1_clk",
113         .pmc_mask       = 1 << AT91SAM9261_ID_TC1,
114         .type           = CLK_TYPE_PERIPHERAL,
115 };
116 static struct clk tc2_clk = {
117         .name           = "tc2_clk",
118         .pmc_mask       = 1 << AT91SAM9261_ID_TC2,
119         .type           = CLK_TYPE_PERIPHERAL,
120 };
121 static struct clk ohci_clk = {
122         .name           = "ohci_clk",
123         .pmc_mask       = 1 << AT91SAM9261_ID_UHP,
124         .type           = CLK_TYPE_PERIPHERAL,
125 };
126 static struct clk lcdc_clk = {
127         .name           = "lcdc_clk",
128         .pmc_mask       = 1 << AT91SAM9261_ID_LCDC,
129         .type           = CLK_TYPE_PERIPHERAL,
130 };
131
132 static struct clk *periph_clocks[] __initdata = {
133         &pioA_clk,
134         &pioB_clk,
135         &pioC_clk,
136         &usart0_clk,
137         &usart1_clk,
138         &usart2_clk,
139         &mmc_clk,
140         &udc_clk,
141         &twi_clk,
142         &spi0_clk,
143         &spi1_clk,
144         &ssc0_clk,
145         &ssc1_clk,
146         &ssc2_clk,
147         &tc0_clk,
148         &tc1_clk,
149         &tc2_clk,
150         &ohci_clk,
151         &lcdc_clk,
152         // irq0 .. irq2
153 };
154
155 static struct clk_lookup periph_clocks_lookups[] = {
156         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
157         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
158         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
159         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
160         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
161         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
162         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
163         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
164 };
165
166 static struct clk_lookup usart_clocks_lookups[] = {
167         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
168         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
169         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
170         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
171 };
172
173 /*
174  * The four programmable clocks.
175  * You must configure pin multiplexing to bring these signals out.
176  */
177 static struct clk pck0 = {
178         .name           = "pck0",
179         .pmc_mask       = AT91_PMC_PCK0,
180         .type           = CLK_TYPE_PROGRAMMABLE,
181         .id             = 0,
182 };
183 static struct clk pck1 = {
184         .name           = "pck1",
185         .pmc_mask       = AT91_PMC_PCK1,
186         .type           = CLK_TYPE_PROGRAMMABLE,
187         .id             = 1,
188 };
189 static struct clk pck2 = {
190         .name           = "pck2",
191         .pmc_mask       = AT91_PMC_PCK2,
192         .type           = CLK_TYPE_PROGRAMMABLE,
193         .id             = 2,
194 };
195 static struct clk pck3 = {
196         .name           = "pck3",
197         .pmc_mask       = AT91_PMC_PCK3,
198         .type           = CLK_TYPE_PROGRAMMABLE,
199         .id             = 3,
200 };
201
202 /* HClocks */
203 static struct clk hck0 = {
204         .name           = "hck0",
205         .pmc_mask       = AT91_PMC_HCK0,
206         .type           = CLK_TYPE_SYSTEM,
207         .id             = 0,
208 };
209 static struct clk hck1 = {
210         .name           = "hck1",
211         .pmc_mask       = AT91_PMC_HCK1,
212         .type           = CLK_TYPE_SYSTEM,
213         .id             = 1,
214 };
215
216 static void __init at91sam9261_register_clocks(void)
217 {
218         int i;
219
220         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
221                 clk_register(periph_clocks[i]);
222
223         clkdev_add_table(periph_clocks_lookups,
224                          ARRAY_SIZE(periph_clocks_lookups));
225         clkdev_add_table(usart_clocks_lookups,
226                          ARRAY_SIZE(usart_clocks_lookups));
227
228         clk_register(&pck0);
229         clk_register(&pck1);
230         clk_register(&pck2);
231         clk_register(&pck3);
232
233         clk_register(&hck0);
234         clk_register(&hck1);
235 }
236
237 static struct clk_lookup console_clock_lookup;
238
239 void __init at91sam9261_set_console_clock(int id)
240 {
241         if (id >= ARRAY_SIZE(usart_clocks_lookups))
242                 return;
243
244         console_clock_lookup.con_id = "usart";
245         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
246         clkdev_add(&console_clock_lookup);
247 }
248
249 /* --------------------------------------------------------------------
250  *  GPIO
251  * -------------------------------------------------------------------- */
252
253 static struct at91_gpio_bank at91sam9261_gpio[] = {
254         {
255                 .id             = AT91SAM9261_ID_PIOA,
256                 .offset         = AT91_PIOA,
257                 .clock          = &pioA_clk,
258         }, {
259                 .id             = AT91SAM9261_ID_PIOB,
260                 .offset         = AT91_PIOB,
261                 .clock          = &pioB_clk,
262         }, {
263                 .id             = AT91SAM9261_ID_PIOC,
264                 .offset         = AT91_PIOC,
265                 .clock          = &pioC_clk,
266         }
267 };
268
269 static void at91sam9261_poweroff(void)
270 {
271         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
272 }
273
274
275 /* --------------------------------------------------------------------
276  *  AT91SAM9261 processor initialization
277  * -------------------------------------------------------------------- */
278
279 static void __init at91sam9261_map_io(void)
280 {
281         if (cpu_is_at91sam9g10())
282                 at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
283         else
284                 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
285 }
286
287 static void __init at91sam9261_initialize(void)
288 {
289         at91_arch_reset = at91sam9_alt_reset;
290         pm_power_off = at91sam9261_poweroff;
291         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
292                         | (1 << AT91SAM9261_ID_IRQ2);
293
294         /* Register GPIO subsystem */
295         at91_gpio_init(at91sam9261_gpio, 3);
296 }
297
298 /* --------------------------------------------------------------------
299  *  Interrupt initialization
300  * -------------------------------------------------------------------- */
301
302 /*
303  * The default interrupt priority levels (0 = lowest, 7 = highest).
304  */
305 static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
306         7,      /* Advanced Interrupt Controller */
307         7,      /* System Peripherals */
308         1,      /* Parallel IO Controller A */
309         1,      /* Parallel IO Controller B */
310         1,      /* Parallel IO Controller C */
311         0,
312         5,      /* USART 0 */
313         5,      /* USART 1 */
314         5,      /* USART 2 */
315         0,      /* Multimedia Card Interface */
316         2,      /* USB Device Port */
317         6,      /* Two-Wire Interface */
318         5,      /* Serial Peripheral Interface 0 */
319         5,      /* Serial Peripheral Interface 1 */
320         4,      /* Serial Synchronous Controller 0 */
321         4,      /* Serial Synchronous Controller 1 */
322         4,      /* Serial Synchronous Controller 2 */
323         0,      /* Timer Counter 0 */
324         0,      /* Timer Counter 1 */
325         0,      /* Timer Counter 2 */
326         2,      /* USB Host port */
327         3,      /* LCD Controller */
328         0,
329         0,
330         0,
331         0,
332         0,
333         0,
334         0,
335         0,      /* Advanced Interrupt Controller */
336         0,      /* Advanced Interrupt Controller */
337         0,      /* Advanced Interrupt Controller */
338 };
339
340 struct at91_init_soc __initdata at91sam9261_soc = {
341         .map_io = at91sam9261_map_io,
342         .default_irq_priority = at91sam9261_default_irq_priority,
343         .register_clocks = at91sam9261_register_clocks,
344         .init = at91sam9261_initialize,
345 };