Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
[linux-2.6.git] / arch / arm / mach-at91 / at91cap9.c
1 /*
2  * arch/arm/mach-at91/at91cap9.c
3  *
4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6  *  Copyright (C) 2007 Atmel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  */
14
15 #include <linux/module.h>
16 #include <linux/pm.h>
17
18 #include <asm/irq.h>
19 #include <asm/mach/arch.h>
20 #include <asm/mach/map.h>
21
22 #include <mach/cpu.h>
23 #include <mach/at91cap9.h>
24 #include <mach/at91_pmc.h>
25 #include <mach/at91_rstc.h>
26 #include <mach/at91_shdwc.h>
27
28 #include "generic.h"
29 #include "clock.h"
30
31 static struct map_desc at91cap9_io_desc[] __initdata = {
32         {
33                 .virtual        = AT91_VA_BASE_SYS,
34                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
35                 .length         = SZ_16K,
36                 .type           = MT_DEVICE,
37         }, {
38                 .virtual        = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
39                 .pfn            = __phys_to_pfn(AT91CAP9_SRAM_BASE),
40                 .length         = AT91CAP9_SRAM_SIZE,
41                 .type           = MT_DEVICE,
42         },
43 };
44
45 /* --------------------------------------------------------------------
46  *  Clocks
47  * -------------------------------------------------------------------- */
48
49 /*
50  * The peripheral clocks.
51  */
52 static struct clk pioABCD_clk = {
53         .name           = "pioABCD_clk",
54         .pmc_mask       = 1 << AT91CAP9_ID_PIOABCD,
55         .type           = CLK_TYPE_PERIPHERAL,
56 };
57 static struct clk mpb0_clk = {
58         .name           = "mpb0_clk",
59         .pmc_mask       = 1 << AT91CAP9_ID_MPB0,
60         .type           = CLK_TYPE_PERIPHERAL,
61 };
62 static struct clk mpb1_clk = {
63         .name           = "mpb1_clk",
64         .pmc_mask       = 1 << AT91CAP9_ID_MPB1,
65         .type           = CLK_TYPE_PERIPHERAL,
66 };
67 static struct clk mpb2_clk = {
68         .name           = "mpb2_clk",
69         .pmc_mask       = 1 << AT91CAP9_ID_MPB2,
70         .type           = CLK_TYPE_PERIPHERAL,
71 };
72 static struct clk mpb3_clk = {
73         .name           = "mpb3_clk",
74         .pmc_mask       = 1 << AT91CAP9_ID_MPB3,
75         .type           = CLK_TYPE_PERIPHERAL,
76 };
77 static struct clk mpb4_clk = {
78         .name           = "mpb4_clk",
79         .pmc_mask       = 1 << AT91CAP9_ID_MPB4,
80         .type           = CLK_TYPE_PERIPHERAL,
81 };
82 static struct clk usart0_clk = {
83         .name           = "usart0_clk",
84         .pmc_mask       = 1 << AT91CAP9_ID_US0,
85         .type           = CLK_TYPE_PERIPHERAL,
86 };
87 static struct clk usart1_clk = {
88         .name           = "usart1_clk",
89         .pmc_mask       = 1 << AT91CAP9_ID_US1,
90         .type           = CLK_TYPE_PERIPHERAL,
91 };
92 static struct clk usart2_clk = {
93         .name           = "usart2_clk",
94         .pmc_mask       = 1 << AT91CAP9_ID_US2,
95         .type           = CLK_TYPE_PERIPHERAL,
96 };
97 static struct clk mmc0_clk = {
98         .name           = "mci0_clk",
99         .pmc_mask       = 1 << AT91CAP9_ID_MCI0,
100         .type           = CLK_TYPE_PERIPHERAL,
101 };
102 static struct clk mmc1_clk = {
103         .name           = "mci1_clk",
104         .pmc_mask       = 1 << AT91CAP9_ID_MCI1,
105         .type           = CLK_TYPE_PERIPHERAL,
106 };
107 static struct clk can_clk = {
108         .name           = "can_clk",
109         .pmc_mask       = 1 << AT91CAP9_ID_CAN,
110         .type           = CLK_TYPE_PERIPHERAL,
111 };
112 static struct clk twi_clk = {
113         .name           = "twi_clk",
114         .pmc_mask       = 1 << AT91CAP9_ID_TWI,
115         .type           = CLK_TYPE_PERIPHERAL,
116 };
117 static struct clk spi0_clk = {
118         .name           = "spi0_clk",
119         .pmc_mask       = 1 << AT91CAP9_ID_SPI0,
120         .type           = CLK_TYPE_PERIPHERAL,
121 };
122 static struct clk spi1_clk = {
123         .name           = "spi1_clk",
124         .pmc_mask       = 1 << AT91CAP9_ID_SPI1,
125         .type           = CLK_TYPE_PERIPHERAL,
126 };
127 static struct clk ssc0_clk = {
128         .name           = "ssc0_clk",
129         .pmc_mask       = 1 << AT91CAP9_ID_SSC0,
130         .type           = CLK_TYPE_PERIPHERAL,
131 };
132 static struct clk ssc1_clk = {
133         .name           = "ssc1_clk",
134         .pmc_mask       = 1 << AT91CAP9_ID_SSC1,
135         .type           = CLK_TYPE_PERIPHERAL,
136 };
137 static struct clk ac97_clk = {
138         .name           = "ac97_clk",
139         .pmc_mask       = 1 << AT91CAP9_ID_AC97C,
140         .type           = CLK_TYPE_PERIPHERAL,
141 };
142 static struct clk tcb_clk = {
143         .name           = "tcb_clk",
144         .pmc_mask       = 1 << AT91CAP9_ID_TCB,
145         .type           = CLK_TYPE_PERIPHERAL,
146 };
147 static struct clk pwm_clk = {
148         .name           = "pwm_clk",
149         .pmc_mask       = 1 << AT91CAP9_ID_PWMC,
150         .type           = CLK_TYPE_PERIPHERAL,
151 };
152 static struct clk macb_clk = {
153         .name           = "macb_clk",
154         .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
155         .type           = CLK_TYPE_PERIPHERAL,
156 };
157 static struct clk aestdes_clk = {
158         .name           = "aestdes_clk",
159         .pmc_mask       = 1 << AT91CAP9_ID_AESTDES,
160         .type           = CLK_TYPE_PERIPHERAL,
161 };
162 static struct clk adc_clk = {
163         .name           = "adc_clk",
164         .pmc_mask       = 1 << AT91CAP9_ID_ADC,
165         .type           = CLK_TYPE_PERIPHERAL,
166 };
167 static struct clk isi_clk = {
168         .name           = "isi_clk",
169         .pmc_mask       = 1 << AT91CAP9_ID_ISI,
170         .type           = CLK_TYPE_PERIPHERAL,
171 };
172 static struct clk lcdc_clk = {
173         .name           = "lcdc_clk",
174         .pmc_mask       = 1 << AT91CAP9_ID_LCDC,
175         .type           = CLK_TYPE_PERIPHERAL,
176 };
177 static struct clk dma_clk = {
178         .name           = "dma_clk",
179         .pmc_mask       = 1 << AT91CAP9_ID_DMA,
180         .type           = CLK_TYPE_PERIPHERAL,
181 };
182 static struct clk udphs_clk = {
183         .name           = "udphs_clk",
184         .pmc_mask       = 1 << AT91CAP9_ID_UDPHS,
185         .type           = CLK_TYPE_PERIPHERAL,
186 };
187 static struct clk ohci_clk = {
188         .name           = "ohci_clk",
189         .pmc_mask       = 1 << AT91CAP9_ID_UHP,
190         .type           = CLK_TYPE_PERIPHERAL,
191 };
192
193 static struct clk *periph_clocks[] __initdata = {
194         &pioABCD_clk,
195         &mpb0_clk,
196         &mpb1_clk,
197         &mpb2_clk,
198         &mpb3_clk,
199         &mpb4_clk,
200         &usart0_clk,
201         &usart1_clk,
202         &usart2_clk,
203         &mmc0_clk,
204         &mmc1_clk,
205         &can_clk,
206         &twi_clk,
207         &spi0_clk,
208         &spi1_clk,
209         &ssc0_clk,
210         &ssc1_clk,
211         &ac97_clk,
212         &tcb_clk,
213         &pwm_clk,
214         &macb_clk,
215         &aestdes_clk,
216         &adc_clk,
217         &isi_clk,
218         &lcdc_clk,
219         &dma_clk,
220         &udphs_clk,
221         &ohci_clk,
222         // irq0 .. irq1
223 };
224
225 static struct clk_lookup periph_clocks_lookups[] = {
226         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
227         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
228         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
229         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
230         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
231         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
232         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
233         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
234         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
235 };
236
237 static struct clk_lookup usart_clocks_lookups[] = {
238         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
239         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
240         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
241         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
242 };
243
244 /*
245  * The four programmable clocks.
246  * You must configure pin multiplexing to bring these signals out.
247  */
248 static struct clk pck0 = {
249         .name           = "pck0",
250         .pmc_mask       = AT91_PMC_PCK0,
251         .type           = CLK_TYPE_PROGRAMMABLE,
252         .id             = 0,
253 };
254 static struct clk pck1 = {
255         .name           = "pck1",
256         .pmc_mask       = AT91_PMC_PCK1,
257         .type           = CLK_TYPE_PROGRAMMABLE,
258         .id             = 1,
259 };
260 static struct clk pck2 = {
261         .name           = "pck2",
262         .pmc_mask       = AT91_PMC_PCK2,
263         .type           = CLK_TYPE_PROGRAMMABLE,
264         .id             = 2,
265 };
266 static struct clk pck3 = {
267         .name           = "pck3",
268         .pmc_mask       = AT91_PMC_PCK3,
269         .type           = CLK_TYPE_PROGRAMMABLE,
270         .id             = 3,
271 };
272
273 static void __init at91cap9_register_clocks(void)
274 {
275         int i;
276
277         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
278                 clk_register(periph_clocks[i]);
279
280         clkdev_add_table(periph_clocks_lookups,
281                          ARRAY_SIZE(periph_clocks_lookups));
282         clkdev_add_table(usart_clocks_lookups,
283                          ARRAY_SIZE(usart_clocks_lookups));
284
285         clk_register(&pck0);
286         clk_register(&pck1);
287         clk_register(&pck2);
288         clk_register(&pck3);
289 }
290
291 static struct clk_lookup console_clock_lookup;
292
293 void __init at91cap9_set_console_clock(int id)
294 {
295         if (id >= ARRAY_SIZE(usart_clocks_lookups))
296                 return;
297
298         console_clock_lookup.con_id = "usart";
299         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
300         clkdev_add(&console_clock_lookup);
301 }
302
303 /* --------------------------------------------------------------------
304  *  GPIO
305  * -------------------------------------------------------------------- */
306
307 static struct at91_gpio_bank at91cap9_gpio[] = {
308         {
309                 .id             = AT91CAP9_ID_PIOABCD,
310                 .offset         = AT91_PIOA,
311                 .clock          = &pioABCD_clk,
312         }, {
313                 .id             = AT91CAP9_ID_PIOABCD,
314                 .offset         = AT91_PIOB,
315                 .clock          = &pioABCD_clk,
316         }, {
317                 .id             = AT91CAP9_ID_PIOABCD,
318                 .offset         = AT91_PIOC,
319                 .clock          = &pioABCD_clk,
320         }, {
321                 .id             = AT91CAP9_ID_PIOABCD,
322                 .offset         = AT91_PIOD,
323                 .clock          = &pioABCD_clk,
324         }
325 };
326
327 static void at91cap9_reset(void)
328 {
329         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
330 }
331
332 static void at91cap9_poweroff(void)
333 {
334         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
335 }
336
337
338 /* --------------------------------------------------------------------
339  *  AT91CAP9 processor initialization
340  * -------------------------------------------------------------------- */
341
342 void __init at91cap9_map_io(void)
343 {
344         /* Map peripherals */
345         iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
346 }
347
348 void __init at91cap9_initialize(unsigned long main_clock)
349 {
350         at91_arch_reset = at91cap9_reset;
351         pm_power_off = at91cap9_poweroff;
352         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
353
354         /* Init clock subsystem */
355         at91_clock_init(main_clock);
356
357         /* Register the processor-specific clocks */
358         at91cap9_register_clocks();
359
360         /* Register GPIO subsystem */
361         at91_gpio_init(at91cap9_gpio, 4);
362
363         /* Remember the silicon revision */
364         if (cpu_is_at91cap9_revB())
365                 system_rev = 0xB;
366         else if (cpu_is_at91cap9_revC())
367                 system_rev = 0xC;
368 }
369
370 /* --------------------------------------------------------------------
371  *  Interrupt initialization
372  * -------------------------------------------------------------------- */
373
374 /*
375  * The default interrupt priority levels (0 = lowest, 7 = highest).
376  */
377 static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
378         7,      /* Advanced Interrupt Controller (FIQ) */
379         7,      /* System Peripherals */
380         1,      /* Parallel IO Controller A, B, C and D */
381         0,      /* MP Block Peripheral 0 */
382         0,      /* MP Block Peripheral 1 */
383         0,      /* MP Block Peripheral 2 */
384         0,      /* MP Block Peripheral 3 */
385         0,      /* MP Block Peripheral 4 */
386         5,      /* USART 0 */
387         5,      /* USART 1 */
388         5,      /* USART 2 */
389         0,      /* Multimedia Card Interface 0 */
390         0,      /* Multimedia Card Interface 1 */
391         3,      /* CAN */
392         6,      /* Two-Wire Interface */
393         5,      /* Serial Peripheral Interface 0 */
394         5,      /* Serial Peripheral Interface 1 */
395         4,      /* Serial Synchronous Controller 0 */
396         4,      /* Serial Synchronous Controller 1 */
397         5,      /* AC97 Controller */
398         0,      /* Timer Counter 0, 1 and 2 */
399         0,      /* Pulse Width Modulation Controller */
400         3,      /* Ethernet */
401         0,      /* Advanced Encryption Standard, Triple DES*/
402         0,      /* Analog-to-Digital Converter */
403         0,      /* Image Sensor Interface */
404         3,      /* LCD Controller */
405         0,      /* DMA Controller */
406         2,      /* USB Device Port */
407         2,      /* USB Host port */
408         0,      /* Advanced Interrupt Controller (IRQ0) */
409         0,      /* Advanced Interrupt Controller (IRQ1) */
410 };
411
412 void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
413 {
414         if (!priority)
415                 priority = at91cap9_default_irq_priority;
416
417         /* Initialize the AIC interrupt controller */
418         at91_aic_init(priority);
419
420         /* Enable GPIO interrupts */
421         at91_gpio_irq_setup();
422 }